DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (e.g., Claims 1-14) in the reply filed on September 2nd, 2026, is acknowledged. Therefore, the restriction/election requirement dated July 21st, 2026, is hereby made FINAL.
Status of Claims
Pursuant to Applicant’s reply to restriction/election requirement filed July 21st, 2026, Claims 15-18 are withdrawn as being drawn to a non-elected invention and Claims 1-14 are pending the within examination.
Information Disclosure Statement
The information disclosure statement (IDS) filed on April 3rd, 2024 is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
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Annotated Fig.8C – Siemieniec
Claim(s) 1-2, 6-7, 9, and 12 is/are rejected under 35 U.S.C 102(a)(1) as being anticipated over Siemieniec et al. (US 20170125520 A1), hereinafter Siemieniec.
As to Claim 1, Siemieniec teaches: A transistor device (semiconductor device 500, Fig.8C, [0041] “semiconductor device 500 including a plurality of identical IGFET (insulated gate field effect transistor) cells TC”), comprising:
a semiconductor substrate (contact portion 129, [0065] “contact portion 129 may be a heavily doped base substrate or a heavily doped layer”) having a first major surface (first surface 101); and
one or more transistor cells, each transistor cell ([0045] ”Each transistor cell IC includes a field electrode structure 160 extending from the first surface 101 into the semiconductor body 100 down to a bottom plane BP”) comprising:
a columnar trench (field electrode structure 160, [0045] “field electrode structure 160 is effective as a compensation structure and includes a conductive spicular or needle-shaped field electrode 165 and a field dielectric 161 surrounding the field electrode 165.”) formed in the semiconductor substrate (contact portion 129), wherein the columnar trench (field electrode structure 160) comprises a field dielectric (diode dielectric 141, field dielectrics 161), a base (bottom of field electrode structure 160, Fig.8C), and a side wall, wherein the side wall extends from the base (bottom of field electrode structure 160, Fig.8C) to the first major surface (first surface 101) and the field dielectric (diode dielectric 141, field dielectrics 161) lines the base and side wall of the columnar trench (field electrode structure 160, Fig. 8C), wherein a first thickness of the field dielectric (diode dielectric 141, field dielectrics 161) at a first distance (upper part of diode dielectric 141, Fig.8C) from the base (bottom of field electrode structure 160, Fig.8C) is smaller than a second thickness of the field dielectric at a second distance (lower part of field dielectrics 161, Fig.8C) from the base (bottom of field electrode structure 160, Fig.8C), wherein the first distance is greater than the second distance (Fig. 8C);
a columnar field plate (diode electrodes 145, field electrodes 165) arranged in the columnar trench (field electrode structure 160), wherein a first perimeter of the columnar field plate (diode electrodes 145, field electrodes 165) at the first distance (upper portion of diode electrode 145, Fig. 8B-8C) is greater than a second perimeter of the columnar field plate (diode electrodes 145, field electrodes 165) at the second distance (lower portion of field electrodes 165, Fig. 8B-8C); and
a mesa (cell mesa 170) arranged around the columnar trench (field electrode structure 160, Fig. 8B, Fig.8C).
As to Claim 2, Siemieniec teaches: The transistor device (semiconductor device 500, Fig. 8C) of claim 1, further comprising a contact (contact structures 315) located at least partially within the columnar trench (field electrode structure 160) and forming an electrical contact (Fig. 8C, [0074] “Contact structures 315 extend through openings in the interlayer dielectric 210 and electrically connect the first load electrode 310 with at least the source zones 110, and, optionally, with the field electrodes 165 of the transistor cells”) between the field plate (diode electrodes 145, field electrodes 165) and the mesa (cell mesa 170).
As to Claim 6, Siemieniec teaches: The transistor device of claim 1 (semiconductor device 500, Fig. 8C), wherein the mesa (cell mesa 170) comprises a drift region (drift zone 121) of a first conductivity type ([0047] “The contiguous section CS includes a first drift zone section 121 a of a first conductivity type”, a body region (body zone 115) of a second conductivity type that opposes the first conductivity type ([0053] “cell mesa 170 includes a body zone 115 of a second conductivity type opposite to the first conductivity type and forms a first pn junction pn1 with the drift zone 121”), the body region (body zone 115) being arranged on the drift region (Fig. 8C, drift zone 121), and a source region of the first conductivity type (source zone 110, [0053] “source zones 110 of the first conductivity type”) arranged on the body region (Fig. 8C, body zone 115).
As to Claim 7, Siemieniec teaches: The transistor device of claim 6 (semiconductor device 500, Fig. 8C), further comprising a contact (contact structures 315) located at least partially within the columnar trench (field electrode structure 160) and forming an electrical contact (Fig. 8C, [0074] “Contact structures 315 extend through openings in the interlayer dielectric 210 and electrically connect the first load electrode 310 with at least the source zones 110, and, optionally, with the field electrodes 165 of the transistor cells”) between the field plate (diode electrodes 145, field electrodes 165) and the mesa (cell mesa 170), wherein the contact (contact structures 315) is in electrical contact (Fig. 8C, [0105] “Contact structures 315 extend…into the diode electrodes 145…contact structures 315 b extend…through openings in the interlayer dielectric 210 and the source zones 110 into the body zones 115”) with the field plate (diode electrodes 145, field electrodes 165), the source region (source zone 110), and the body region (body zone 115).
As to Claim 9, Siemieniec teaches: The transistor device (semiconductor device 500, Fig. 8C) of claim 6, wherein at the first distance, the columnar trenches (field electrode structures 160) is adjacent to the drift region (Fig. 8C, drift zone 121), and wherein at the second distance, the columnar trench (field electrode structure 160) is adjacent to the drift region (Fig. 8C, drift zone 121).
As to Claim 12, Siemieniec teaches: The transistor device of claim 1 (semiconductor device 500, Fig. 8C), wherein the one or more transistor cells further comprise:
a gate trench (gate structures 150) formed in the mesa (cell mesa 170), wherein the gate trench (gate structures 150) comprises a base and a side wall (Fig. 8C);
a gate dielectric (gate dielectric 151) that lines the base and side wall of the gate trench (Fig. 8C, gate structures 150); and
a gate electrode (gate electrode 155) arranged in the gate trench (Fig. 8C, gate structures 150), wherein the gate trench (gate structures 150) surrounds the columnar trench (Fig. 8C, field electrode structure 160).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
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Annotated Fig. 2 - Denison
Claim(s) 3-4 is/are rejected under 35 U.S.C 103 as being unpatentable over Siemieniec as being applied to Claim(s) 1-2, 6-7, 9, and 12 above, and in further view of Laven et al. (US 20160300945 A1) hereinafter Laven.
As to Claim 3, Siemieniec teaches: The transistor device (semiconductor device 500, Fig. 8C) of claim 2,
Siemieniec does not explicitly teach: wherein a central region of the field plate remains uncovered by the contact. Siemieniec does disclose a field plate [diode electrodes 145, field electrodes 165] and contact [contact structures 315] but fails to teach the central region of the field plate remaining uncovered by the contact.
However, in an analogous art, Laven teaches: wherein a central region of the field plate (first buried electrode 515) remains uncovered by the contact (contact structure 315, Fig. 2E). Further, Laven discloses a contact [contact structure 315] that is located partially within the columnar trench [cell trench structures 510] and the contact [contact structure 315] forms an electrical connection (Fig. 2E, [0081] “contact structures 315 electrically connecting the first electrode structure 310 with the first buried electrodes 515, the body zones 115 and the source zones 110 of the semiconductor mesas 150”) between a field plate [first buried electrode 515] and mesa [semiconductor mesa 150] which is analogous to Siemieniec teachings.
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to apply the teaching of Laven to modify the transistor device as taught by Siemieniec. One would be motivated to do so as this feature is advantageous for providing electrical contacts to impurity zones which contributes to providing semiconductor structures with narrowing mesas in a reliable and low-cost manner (Laven, [0001]).
As to Claim 4, Siemieniec teaches: The transistor device (semiconductor device 500, Fig. 8C) of claim 2, wherein the contact (contact structures 315)
Siemieniec does not explicitly teach: has a width that is greater than the first thickness of the field dielectric. Siemieniec does disclose a field dielectric [diode dielectric 141, field dielectrics 161] and contact [contact structures 315] but fails to teach the contact as having a width greater than the first thickness of the dielectric.
However, in an analogous art, Laven teaches: has a width that is greater than the first thickness of the field dielectric (first insulator layer 516, Fig. 3C). Laven explicitly teaches the contact [contact structure 315] which is wider than the field dielectric [first insulator layer 516] shown in Fig. 3C.
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to apply the teaching of Laven to modify the transistor device as taught by Siemieniec. One would be motivated to do so as this feature is advantageous for providing semiconductor devices with narrow semiconductor mesas and small distances between neighboring cell trench structures at a low cost (Laven, [0001]).
Claim(s) 5 and 10 is/are rejected under 35 U.S.C 103 as being unpatentable over Siemieniec as being applied to Claim(s) 1-2, 6-7, 9, and 12 above, and in further view of Denison et al. (US 20100264486 A1) hereinafter Denison.
As to Claim 5, Siemieniec teaches: The transistor device (semiconductor device 500, Fig. 8C) of claim 1,
Siemieniec does not explicitly teach: wherein a third perimeter of the columnar field plate at a third distance from the base is larger than the first perimeter, and wherein the third distance is greater than the first distance. Siemieniec does disclose a first [upper portion of diode electrode 145, Fig. 8B-8C] and second perimeter [lower part of field electrodes 165, Fig. 8B-8C] of the columnar field plate [diode electrodes 145, field electrodes 165] but remains silent on a third perimeter of the columnar field plate.
However, in analogous art, Denison teaches: wherein a third perimeter (Fig.2, field plate 260 above upper section 275) of the columnar field plate (field plate 260) at a third distance from the base is larger than the first perimeter (Fig. 2, field plate 260 in lower section 280), and wherein the third distance is greater than the first distance (Fig. 2). Based on Fig. 2, the field plate 260 in the section above upper section 275 is wider compared to the field plate in lower section 280, therefore the third perimeter is greater than the first and second perimeter. The first perimeter corresponds to the perimeter of the field plate 260 in the upper section 275 at a first distance. The second perimeter corresponds to the perimeter of the field plate 260 in the lower section 280 at a second distance.
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to apply the teaching of Denison to supplement columnar field plate taught by Siemieniec to include an added third perimeter wherein the third distance is greater than the first distance. One would be motivated to do so as the feature is advantageous in minimizing product of the device area which further results in lower power dissipation during operation of the device (Denison, [0002]).
As to Claim 10, Siemieniec teaches: The transistor device (semiconductor device 500, Fig. 8C) of claim 1, wherein the side face of the field plate (Fig. 8C, diode electrodes 145, field electrodes 165) comprises a step such that an upper portion of the field plate (Fig. 8C, upper part of diode electrodes 145, field electrodes 165) has a width that is greater than a width of a lower portion of the field plate (Fig. 8C, lower part of diode electrodes 145, field electrodes 165)
Siemieniec does not explicitly teach: and such that the field dielectric has a first thickness t1 in a first region of the side wall of the columnar trench and a second thickness t2 in a second region of the side wall of the columnar trench, and wherein t1 ≤ 1.15 t2 or t1 ≤ 1.2 t2 or t1 ≤ 1.5 t2. Siemieniec does disclose a step on the side face of the field plate such that the upper portion of the field plate has a greater width than the lower portion of the field plate but does not teach different ratios of thickness between two portions.
However, in analogous art, Denison teaches: and such that the field dielectric (field plate dielectric 270) has a first thickness t1 (T3, [0023] ”an upper section 275 has a thickness T3”) in a first region of the side wall of the columnar trench (Fig. 2, trench 240) and a second thickness t2 (T4, [0023] ”lower section 280 has a thickness T4 that is greater than T3”) in a second region of the side wall of the columnar trench (Fig. 2, trench 240), and wherein t1 ≤ 1.15 t2 or t1 ≤ 1.2 t2 or t1 ≤ 1.5 t2 ([0023] “a nonuniformity of the electric field between the end points of path 330, e.g., between the top and the bottom of the region 265, may be limited to no greater than about 20%.”). The claims recite one of the relationships listed between t1 and t2, Denison discloses a relationship between T3 and T4 as T3 ≤ 1.2 T4 which satisfies this limit.
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to apply the teaching of Denison to modify the field dielectric as taught by Siemieniec to include a ratio of difference in thickness between the upper and lower portion of the field dielectric. One would be motivated to do so as the difference in thickness allows for a more uniform potential distribution in the drift region by increasing the capacitive coupling of the plate through thinner portions of the dielectric (Denison, [0025]).
Claim(s) 8 is/are rejected under 35 U.S.C 103 as being unpatentable over Siemieniec as being applied to Claim(s) 1-2, 6-7, 9, and 12 above, and in further view of Siemieniec et al. (US 20210242340 A1) hereinafter Siemieniec (2021).
As to Claim 8, Siemieniec teaches: The transistor device (semiconductor device 500, Fig. 8C) of claim 6,
Siemieniec does not explicitly teach wherein a doping concentration in the drift region and adjacent to the columnar trench increases along a direction pointing from the first major surface to a second major surface of the semiconductor substrate opposing the first major surface. Siemieniec does disclose a drift region [drift zone 121], columnar trench [field electrode structure 160], a first major surface [first surface 101], and a second major surface [second surface 102] but fails to teach a directional increase of doping concentration in the drift region.
However, in an analogous art, Siemieniec (2021) teaches: wherein a doping concentration in the drift region (drift region 106) and adjacent to the columnar trench (trench 110) increases (Fig. 2A) along a direction pointing from the first major surface to a second major surface of the semiconductor substrate opposing the first major surface (Fig. 2B, [0022] “has a generally linearly graded (upper) first doping profile (DP_drain1) which increases from the body region 104 toward a bottom 128 of the trench 110 that includes the field electrode 124”).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to apply the teaching of Siemieniec (2021) to modify the transistor device as taught by Siemieniec. One would be motivated to do so as this feature lowers the on-resistance of the device and the Figures-of-Merit (FOM) including FOM gate total charge and FOM output charge (Siemieniec (2021), [0016]).
Claim(s) 11 is/are rejected under 35 U.S.C 103 as being unpatentable over Siemieniec as being applied to Claim(s) 1-2, 6-7, 9, and 12 above, and in further view of Siemieniec et al. (US 20160064548 A1) hereinafter Siemieniec (2016).
As to Claim 11, Siemieniec teaches: The transistor device of claim 1 (semiconductor device 500, Fig. 8C), wherein the one or more columnar trenches (field electrode structures 160)
Siemieniec does not explicitly teach: are arranged in offset rows. Siemieniec does teach the formation of the columnar trenches as a matrix-like formation [Fig. 8B].
However, in analogous art, Siemieniec (2016) teaches: are arranged in offset rows (Fig. 6A-6B, [0087] “field electrode structures 160 arranged in shifted lines, wherein the odd lines are shifted to the even lines by one half of the distance between two neighboring transistor cells TC or two neighboring field electrode structures 160.”).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to apply the teaching of Siemieniec (2016) to modify the arrangement of columnar trenches as taught by Siemieniec to be arranged in offset rows. One would be motivated to do so to as columnar trenches arranges in offset rows allow for a larger volume of trenches on the mesa optimizing the number of features located on semiconductor device, potentially reducing ohmic losses (Siemieniec (2016), [0002]).
Claim(s) 13-14 is/are rejected under 35 U.S.C 103 as being unpatentable over Siemieniec as being applied to Claim(s) 1-2, 6-7, 9, and 12 above, and in further view of Chen et al. (US 10720499 B2) hereinafter Chen.
As to Claim 13, Siemieniec teaches: The transistor device of claim 1 (semiconductor device 500, Fig. 8C), wherein the one or more transistor cells further comprise:
Siemieniec does not explicitly teach: a planar gate electrode arranged on the mesa, wherein the planar gate electrode laterally surrounds the columnar trench. Siemieniec does disclose a mesa [cell mesa 170] and a columnar trench [field electrode structure 160] where a trench gate electrode arrangement [Fig. 8C] is used but fails to teach a planar gate electrode arrangement.
However, in analogous art, Chen teaches: a planar gate electrode (planar gate MOS transistor 156, [C.1, L.23-30] “configured as a planar gate structure… can configured as a trench gate structure where a second polysilicon gate sits on top of polysilicon inside a gate trench”) arranged on the mesa (Fig. 1B), wherein the planar gate electrode (planar gate MOS transistor 156) laterally surrounds the columnar trench (Fig. 1B).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to apply the teaching of Chen to modify the gate electrode as taught by Siemieniec to use a planar gate electrode arranged on the mesa as an equivalent option to a trench gate electrode. One would be motivated to do so as a planar gate electrode can predictably be used as a known alternative that achieves a reasonable level of success when performing the gating function.
As to Claim 14, Siemieniec teaches: The transistor device (semiconductor device 500, Fig. 8C) of claim 1, wherein the field dielectric
Siemieniec does not explicitly teach: comprises a first layer and a second layer, wherein the first thickness of the field dielectric is substantially equal to a thickness of the first layer, and wherein the second thickness of the field dielectric is substantially equal to the sum of the thickness of the first layer and the thickness of the second layer. Siemieniec does teach a field dielectric [diode dielectric 141, field dielectrics 161] having an upper [upper part of diode dielectric 141, Fig.8C] and lower portion [bottom of field electrode structure 160, Fig.8C] fails to disclose the composition of the field dielectric as two layers with varying thickness.
However, in analogous art, Chen teaches: comprises a first layer (first dielectric liner layer 140) and a second layer (second dielectric liner layer 142), wherein the first thickness of the field dielectric is substantially equal to a thickness of the first layer, and wherein the second thickness of the field dielectric is substantially equal to the sum of the thickness of the first layer and the thickness of the second layer (Fig. 1A, [C.2 L.36-39] ; [C.3 L.59 – C.4 L25]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to apply the teaching of Chen to modify the composition of the field dielectric as taught by Siemieniec to comprise a first and second layer of varying thickness. One would be motivated to do so as to tune the dielectric constant of the dielectric features (Chen , [C.3 L.9-27]). Further, the varying thickness of the dielectric layers affects etching rates (Chen , [C.1 L.13-22]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mashal Ahmed whose telephone number is (571)270-1754. The examiner can normally be reached M-F, 9AM to 5 PM.
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/MASHAL AHMED/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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