Prosecution Insights
Last updated: April 19, 2026
Application No. 18/625,326

MULTILAYER CERAMIC CAPACITOR AND MOUNTING STRUCTURE FOR MULTILAYER CERAMIC CAPACITOR

Non-Final OA §103
Filed
Apr 03, 2024
Examiner
THOMAS, ERIC W
Art Unit
2848
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Murata Manufacturing Co. Ltd.
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
81%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allow Rate
1019 granted / 1237 resolved
+14.4% vs TC avg
Minimal -2% lift
Without
With
+-1.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
41 currently pending
Career history
1278
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
47.7%
+7.7% vs TC avg
§102
34.1%
-5.9% vs TC avg
§112
8.9%
-31.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1237 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujita et al. (US 2016/0093439) in view of Kato et al. (US 5,135,606). PNG media_image1.png 310 484 media_image1.png Greyscale PNG media_image2.png 258 370 media_image2.png Greyscale Regarding claim 1, Fujii et al. disclose in fig. 1 & 7, a multilayer ceramic capacitor (100) comprising: a capacitor body (11) including a multilayer body in which dielectric layers (13) and internal electrode layers (14) are alternately laminated, a first external electrode (12), and a second external electrode (12); and an interposer (21) adjacent to one surface (112) of the capacitor body (11) facing in a lamination direction (T); wherein the multilayer body (11) includes a multilayer-body first main surface (111) and a multilayer-body second main surface (112) opposite to each other in the lamination direction (T), a multilayer-body first end surface (113) and a multilayer-body second end (114) surface opposite to each other in a length direction (L) orthogonal or substantially orthogonal to the lamination direction (T), and a multilayer-body first side surface (115) and a multilayer-body second side surface (116) that are opposite to each other in a width direction (W) orthogonal or substantially orthogonal to both the lamination direction (T) and the length direction (L); the first external electrode (12) is provided on the multilayer-body first end surface (113); the second external electrode (12) is provided on the multilayer-body second end surface (114); the interposer (21) includes an interposer body (21), a first pillar connector (24), and a second pillar connector (24); the interposer body includes an interposer-body first main surface (21a) facing the capacitor body (11), an interposer-body second main surface (21b) opposite to the interposer-body first main surface (21a), and a first through hole (24) and a second through hole (24) penetrating through the interposer body (21) from the interposer-body first main surface (21a) to the interposer-body second main surface (21b); the first pillar (24) includes a metal material including a metal (copper – [0071]) with a melting point of about 230°C or higher as a main component, and being provided in the first through hole (24) and conductively connected to the first external electrode (12); the second pillar (24) includes a metal material including a metal (copper – [0071]) with a melting point of about 230°C or higher as a main component, and being provided in the second through hole (24) and conductively connected to the second external electrode (12); Fujita et al. disclose the claimed invention except for the first pillar and the second pillar protrude from at least one of the interposer-body first main surface or the interposer-body second main surface. Kato et al. disclose a process for preparing an electrical connection (134) contained in a substrate (135) wherein the electrical connection comprises a pillar that protrudes from the substrate (135 - Fig. 3-4). It would have been obvious to a person of ordinary skill in the electrical connection art to form the device of Fujita et al. so that the first pillar and the second pillar protrude from at least one of the interposer-body first main surface or the interposer-body second main surface, since such a modification would form pillars having high connection stability. Regarding claim 2, Fujita et al. disclose the metal is Cu [0071]; and a content of Cu in the metal material is about 60% by weight or more [0071]. Regarding claim 3, the modified Fujita et al. disclose in plan view of the interposer-body first main surface (21a), at least a portion of the first pillar covers an opening peripheral edge portion of the first through hole (24), and/or at least a portion of the second pillar covers an opening peripheral edge portion of the second through hole (24). Regarding claim 4, the modified Fujita et al. disclose in plan view of the interposer-body second main surface (21b) , at least a portion of the first pillar (24) covers an opening peripheral edge portion of the first through hole (24), and/or at least a portion of the second pillar (24) covers an opening peripheral edge portion of the second through hole (24). Regarding claim 5, the modified Fujita et al. disclose a dimension (T2 - see annotated figure below) of the first through hole (24) in the length direction (L) is equal to or greater than about 0.5 times a dimension (T1 – see annotated figure below) of the first external electrode (12) in the length direction (see annotated figure below); and a dimension of the second through hole (24) in the length direction (L) is equal to or greater than about 0.5 times a dimension of the second external electrode (12) in the length direction (L). PNG media_image3.png 325 316 media_image3.png Greyscale Regarding claim 6, the modified Fujita et al. disclose a dimension of the first through hole (24) in the length direction (L) is equal to or less than about 1.1 times a dimension of the first external electrode (12) in the length direction (L); and a dimension of the second through hole (24) in the length direction (L) is equal to or less than about 1.1 times a dimension of the second external electrode (12) in the length direction (L – see fig. 12). Regarding claim 7, the modified Fujita et al. disclose the first pillar (24) includes a portion protruding from the interposer-body first main surface (21a) and having a dimension of about 100 µm or less in the lamination direction (Kato et al. – Fig. 4, d3 – Table 1); the first pillar (24) includes a portion protruding from the interposer-body second main surface (21b) and having a dimension of about 100 µm or less in the lamination direction (Kato et al. – Fig. 4, d4 – table 1); the second pillar (24) includes a portion protruding from the interposer-body first main surface (21a) and having a dimension of about 100 µm or less in the lamination direction (Kato et al. – Fig. 4, d3 – Table 1); and the second pillar includes a portion protruding from the interposer-body second main surface (21b) and having a dimension of about 100 µm or less in the lamination direction (Kato et al. – Fig. 4, d4 – Table 1). Regarding claim 8, Fujita et al. disclose the interposer body (21) has a dimension of about 30 µm or more in the lamination direction [0125]. Regarding claim 9, Fujita et al. disclose the interposer body has a dimension of about 300 µm or less in the lamination direction [0125]. Regarding claim 10, the modified Fujita et al. disclose the first pillar is directly connected to the first external electrode (24 & Kato et al. – Fig 4); and the second pillar is directly connected to the second external electrode (24 & Kato et al. – Fig. 4). Regarding claim 11, the modified Fujita et al. disclose a mounting structure (circuit board – [0070]) for a multilayer ceramic capacitor, the mounting structure [0070] comprising: the multilayer ceramic capacitor according to claim 1; and a mounting board (circuit board – [0070]) including a first land [0070] and a second land [0070]; wherein the mounting board (circuit board – [0070]) being positioned such that the interposer (21) is sandwiched between the mounting board (circuit board – [0070]) and the capacitor body (11); the first land [0070] is conductively connected to the first pillar (24 & Kato et al. – Fig. 4); and the second land [0070] is conductively connected to the second pillar (24 & Kato et al. – Fig. 4). Regarding claim 12, Fujita et al. disclose the metal is Cu [0071]; and a content of Cu in the metal material is about 60% by weight or more [0071]. Regarding claim 13, the modified Fujita et al. disclose in plan view of the interposer-body first main surface (21a), at least a portion of the first pillar covers an opening peripheral edge portion of the first through hole (24), and/or at least a portion of the second pillar covers an opening peripheral edge portion of the second through hole (24). Regarding claim 14, the modified Fujita et al. disclose in plan view of the interposer-body second main surface (21b) , at least a portion of the first pillar (24) covers an opening peripheral edge portion of the first through hole (24), and/or at least a portion of the second pillar (24) covers an opening peripheral edge portion of the second through hole (24). Regarding claim 15, the modified Fujita et al. disclose a dimension (T2 - see annotated figure below) of the first through hole (24) in the length direction (L) is equal to or greater than about 0.5 times a dimension (T1 – see annotated figure below) of the first external electrode (12) in the length direction (see annotated figure below); and a dimension of the second through hole (24) in the length direction (L) is equal to or greater than about 0.5 times a dimension of the second external electrode (12) in the length direction (L). PNG media_image3.png 325 316 media_image3.png Greyscale Regarding claim 16, the modified Fujita et al. disclose a dimension of the first through hole (24) in the length direction (L) is equal to or less than about 1.1 times a dimension of the first external electrode (12) in the length direction (L); and a dimension of the second through hole (24) in the length direction (L) is equal to or less than about 1.1 times a dimension of the second external electrode (12) in the length direction (L – see fig. 12). Regarding claim 17, the modified Fujita et al. disclose the first pillar (24) includes a portion protruding from the interposer-body first main surface (21a) and having a dimension of about 100 µm or less in the lamination direction (Kato et al. – Fig. 4, d3 – Table 1); the first pillar (24) includes a portion protruding from the interposer-body second main surface (21b) and having a dimension of about 100 µm or less in the lamination direction (Kato et al. – Fig. 4, d4 – table 1); the second pillar (24) includes a portion protruding from the interposer-body first main surface (21a) and having a dimension of about 100 µm or less in the lamination direction (Kato et al. – Fig. 4, d3 – Table 1); and the second pillar includes a portion protruding from the interposer-body second main surface (21b) and having a dimension of about 100 µm or less in the lamination direction (Kato et al. – Fig. 4, d4 – Table 1). Regarding claim 18, Fujita et al. disclose the interposer body (21) has a dimension of about 30 µm or more in the lamination direction [0125]. Regarding claim 19, Fujita et al. disclose the interposer body has a dimension of about 300 µm or less in the lamination direction [0125]. Regarding claim 20, the modified Fujita et al. disclose the first pillar is directly connected to the first external electrode (24 & Kato et al. – Fig 4); and the second pillar is directly connected to the second external electrode (24 & Kato et al. – Fig. 4). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2020/0343044 A1 US 2020/0118743 A1 US 2017/0290161 A1 US 2016/0372265 A1 Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC THOMAS whose telephone number is (571)272-1985. The examiner can normally be reached Monday-Friday, 6:00 AM-2:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERIC W THOMAS/Primary Examiner, Art Unit 2848 ERIC THOMAS Primary Examiner Art Unit 2848
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Prosecution Timeline

Apr 03, 2024
Application Filed
Jan 28, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12603224
MULTILAYERED CAPACITOR
2y 5m to grant Granted Apr 14, 2026
Patent 12603233
CAPACITOR
2y 5m to grant Granted Apr 14, 2026
Patent 12603232
CAPACITOR
2y 5m to grant Granted Apr 14, 2026
Patent 12592347
ELECTROLYTIC CAPACITOR INCLUDING AN ENLARGED SURFACE LAYER AND A DIELECTRIC OXIDE FILM FORMED ON THE ENLARGED SURFACE LAYER
2y 5m to grant Granted Mar 31, 2026
Patent 12593701
DIRECT MOLDED ELECTRIC DEVICE
2y 5m to grant Granted Mar 31, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
81%
With Interview (-1.7%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 1237 resolved cases by this examiner. Grant probability derived from career allow rate.

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