DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This communication is in response to the application filed on 04/03/2024.
Claims 1-20 are pending and are rejected.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/03/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 11-14, 16, 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Bart (EP 2110996 A1) in view of Devriendt (US 20210149563 A1).
Regarding claim 1, Bart teaches a method comprising:
identifying, in a first network, a path group consisting of a plurality of data paths between a first endpoint and a second endpoint, the plurality of data paths including at least a first data path and a second data path ([0036], fig. 1, the DSLAM 102 is in this case equipped with an embodiment of a device according to the present invention to support multiple QoS differentiated transmission paths on the link between the DSLAM 102 and the CPE, 1031 to 103n), wherein a first link speed of the first data path is slower than a second link speed of the second data path ([0037] there are 4 data transmission paths, each with a different interleaving depth, the selector may put the highest two priorities (first link speed) on the fastest DSL line transmission path, the next two priorities on the second transmission path and so forth, with the lowest two priorities (second link speed) on the slowest but best protected data transmission path);
adjusting, in response to the latency value associated with the first data path meeting a service level requirement, a path selection mechanism to favor the first data path over the second data path ([0024] if the device is connected to both a "fast" latency channel in the sense of the xDSL standards, which offers lower protection, and a slower but well protected interleaved channel, the device can select the DSL line transmission path based on the acceptable delay for each packet and place packets with a delay requirement below the delay caused by the protection on this "fast" channel; [0026] the device may select the fastest DSL line transmission path for a few of the highest delay priorities and use the slowest of the two DSL line transmission paths for all other priorities (favor the first data path over the second data path)).
Bart does not explicitly teach
determining a latency value associated the first data path;
Devriendt teaches
determining a latency value associated the first data path ([0009] the hierarchical address may include a plurality of hierarchy level identifiers corresponding to a hierarchical path from at least one controller node to a selected storage element; [0064] selecting a slower path for users and processes that do not require low latency).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Bart disclosure, the first communication link latency is measured, as taught by Devriendt. One would be motivated to do so to optimize the power efficiency of a distributed storage system (DSS) by choosing storage paths that allow for storage and retrieval of data blocks in a power efficient way.
Regarding claim 2, Bart and Devriendt teach the method of claim 1, wherein Bart further teaches the path selection mechanism is adjusted by setting a preference parameter indicating a preference for at least one of a link speed and a data path ([0037] The storage can then indicate that non-interleaved data channel and the lowest priorities should be transported on the slower interleaved data channel).
Regarding claim 3, Bart and Devriendt teach the method of claim 1, wherein Bart further teaches the path selection mechanism is adjusted by adjusting a ranking of the plurality of data paths in the path group ([0007] Another important aspect of QoS is delay variation. Delay variation is typically kept within bounds in packet networks by scheduling for delay priority, by segregating (Internet Protocol) packets or (Ethernet) frames in different queues).
Regarding claim 4, Bart and Devriendt teach the method of claim 1, wherein Bart further teaches the path selection mechanism is adjusted by changing a path selection policy ([0013] by selecting the first logical transmission path or second logical transmission path based on quality of service information related to the data packets).
Regarding claims 5, 13, and 18, Bart and Devriendt teach all limitations of parent claim 1, Bart further teaches:
transmitting, based on the adjusted path selection mechanism, a packet using the first data path instead of the second data path (0013] , by selecting the first logical transmission path or second logical transmission path based on quality of service information related to the data packets, the effort in configuring a network can greatly be reduced and the use of multiple transmission paths can be added to existing networks with little effort).
Regarding claim 6, Bart and Devriendt teach the method of claim 1, wherein Bart further teaches the latency value is based on an end-to-end transaction time for packets transmitted from the first endpoint to the second endpoint ([0021] The third logical transmission path uses some of the time frames or bandwidth of the first and/second logical transmission path to transport its data).
Regarding claim 7, Bart and Devriendt teach the method of claim 6, wherein the plurality of data paths traverses the first network and a second network; and wherein a latency of a path accounts for a first latency within the first network and a second latency within the second network ([0037] The xDSL transmitter 200 in this particular example is built to transmit on e.g. two ch annels, an interleaved channel which offers more protection at higher delay and a noninterleaved channel which offers a lower delay but at a lower level of protection for the transported data).
Regarding claims 8, 14, and 19, Bart and Devriendt teach all limitations of parent claims 1, 12, Bart further teaches:
reducing, based on the first data path meeting the service level requirement, a link speed of a particular data path in the path group ([0030] This way, the traffic flowing through the operator network will be placed on appropriate DSL line transmission paths to meet seamlessly the quality of service requirements for all the traffic flowing through the network, up to the subscriber CPE).
Regarding claims 11 and 16, Bart and Devriendt teach all limitations of parent claims 1 and 12, wherein Bart further teaches the first network is storage area network that utilizes a Fibre Channel policy ([0113] Computer code embodied on a computer-readable medium may be transmitted using any appropriate medium, including but not limited to, wireless, wired, optical fiber cable, radio frequency (RF), etc., or any suitable combination of the foregoing).
Regarding claim 12, Bart teaches an apparatus comprising:
a processing device; and memory operatively coupled to the processing device ([0041] a computer system, a processor), wherein the memory stores computer program instructions that, when executed, cause the processing device to:
identify, in a first network, a path group consisting of a plurality of data paths between a first endpoint and a second endpoint, the plurality of data paths including at least a first data path and a second data path ([0036], fig. 1, the DSLAM 102 is in this case equipped with an embodiment of a device according to the present invention to support multiple QoS differentiated transmission paths on the link between the DSLAM 102 and the CPE, 1031 to 103n), wherein a first link speed of the first data path is slower than a second link speed of the second data path ([0037] there are 4 data transmission paths, each with a different interleaving depth, the selector may put the highest two priorities (first link speed) on the fastest DSL line transmission path, the next two priorities on the second transmission path and so forth, with the lowest two priorities (second link speed) on the slowest but best protected data transmission path);
determine a latency value associated the first data path; and
adjust, in response to the latency value associated with the first data path meeting a
service level requirement, a path selection mechanism to favor the first data path over the second data path ([0024] if the device is connected to both a "fast" latency channel in the sense of the xDSL standards, which offers lower protection, and a slower but well protected interleaved channel, the device can select the DSL line transmission path based on the acceptable delay for each packet and place packets with a delay requirement below the delay caused by the protection on this "fast" channel; [0026] the device may select the fastest DSL line transmission path for a few of the highest delay priorities and use the slowest of the two DSL line transmission paths for all other priorities (favor the first data path over the second data path)).
Bart does not explicitly teach
determining a latency value associated the first data path;
Devriendt teaches
determining a latency value associated the first data path ([0009] the hierarchical address may include a plurality of hierarchy level identifiers corresponding to a hierarchical path from at least one controller node to a selected storage element; [0064] selecting a slower path for users and processes that do not require low latency).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Bart disclosure, the first communication link latency is measured, as taught by Devriendt. One would be motivated to do so to optimize the power efficiency of a distributed storage system (DSS) by choosing storage paths that allow for storage and retrieval of data blocks in a power efficient way.
Regarding claim 17, Bart teaches a computer program product comprising a computer readable storage medium, wherein the computer readable storage medium comprises computer program instructions that, when executed:
identify, in a first network, a path group consisting of a plurality of data paths between a first endpoint and a second endpoint, the plurality of data paths including at least a first data path and a second data path ([0036], fig. 1, the DSLAM 102 is in this case equipped with an embodiment of a device according to the present invention to support multiple QoS differentiated transmission paths on the link between the DSLAM 102 and the CPE, 1031 to 103n), wherein a first link speed of the first data path is slower than a second link speed of the second data path ([0037] there are 4 data transmission paths, each with a different interleaving depth, the selector may put the highest two priorities (first link speed) on the fastest DSL line transmission path, the next two priorities on the second transmission path and so forth, with the lowest two priorities (second link speed) on the slowest but best protected data transmission path);
adjust, in response to the latency value associated with the first data path meeting a service level requirement, a path selection mechanism to favor the first data path over the second data path ([0024] if the device is connected to both a "fast" latency channel in the sense of the xDSL standards, which offers lower protection, and a slower but well protected interleaved channel, the device can select the DSL line transmission path based on the acceptable delay for each packet and place packets with a delay requirement below the delay caused by the protection on this "fast" channel; [0026] the device may select the fastest DSL line transmission path for a few of the highest delay priorities and use the slowest of the two DSL line transmission paths for all other priorities (favor the first data path over the second data path)).
Bart does not explicitly teach
determine a latency value associated the first data path;
Devriendt teaches
determining a latency value associated the first data path ([0009] the hierarchical address may include a plurality of hierarchy level identifiers corresponding to a hierarchical path from at least one controller node to a selected storage element; [0064] selecting a slower path for users and processes that do not require low latency).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Bart disclosure, the first communication link latency is measured, as taught by Devriendt. One would be motivated to do so to optimize the power efficiency of a distributed storage system (DSS) by choosing storage paths that allow for storage and retrieval of data blocks in a power efficient way.
Claims 9-10, 15, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Bart (EP 2110996 A1) in view of Devriendt (US 20210149563 A1) and further in view of Zong (US 20250247341 A1).
Regarding claims 9, 15, and 20, Bart and Devriendt teach all limitations of parent claims 1, 12, and 17, Bart does not explicitly teach:
reducing a link speed of a particular data path in the path group responsive to determining that a utilization of the particular data path has decreased.
Zong teaches
reducing a link speed of a particular data path in the path group responsive to determining that a utilization of the particular data path has decreased ([0072] the speed of data requests may be dynamically adjusted based on the evaluation of the utilization level of the DBCPU resource, in order to maintain the utilization level of the DBCPU resource within a predetermined target range).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Bart disclosure, the speed of data request is dynamically adjust to either increase or decrease, as taught by Zong. One would be motivated to do so that the utilization level of the computing resource is maintained within a predetermined target range.
Regarding claim 10, Bart, Devriendt, and Zong teach the method of claim 9, wherein Zong further teaches an amount of reduction in the link speed is determined based on a utilization of the particular data path and a predetermined headroom ([0055] The speed of data requests received at the DBCPU resource (from the top contributing user, after the throttling) and a utilization level of the DBCPU resource may be evaluated. As is commonly known in the art, the speed of data requests may be indicative of a quota that allows the queue to emit a request).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention made to include in the Bart disclosure, the speed of data request is dynamically adjust to either increase or decrease, as taught by Zong. One would be motivated to do so that the utilization level of the computing resource is maintained within a predetermined target range.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Huang (US 20210331067 A1) and Lin (US 20210266814 A1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH NGUYEN whose telephone number is (571)270-0657. The examiner can normally be reached M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Umar Cheema can be reached at 5712703037. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANH NGUYEN/Primary Examiner, Art Unit 2458