DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-10, 12-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kaneda et al. (US 20150102510 hereinafter Kaneda).
In regards to claim 1, Kaneda discloses;” A wiring substrate (abstract, paragraph 0005), comprising: a first build-up part comprising a plurality of first insulating layers, a plurality of first conductor layers, and a plurality of via conductors (Fig. 1A (12)); and a second build-up part comprising a plurality of second insulating layers and a plurality of second conductor layers and formed such that the first build-up part is laminated on the second build-up part (Fig. 1A (11)), that a minimum wiring width of wirings in the first conductor layers is smaller than a minimum wiring width of wirings in the second conductor layers (Fig. 1A (shown, paragraph 0054)), and that a minimum inter-wiring distance of the wirings in the first conductor layers is smaller than a minimum inter-wiring distance of the wirings in the second conductor layers (paragraph’s 0057 and 0079 give the sizes)), wherein the first build-up part is formed such that the first conductor layers and the via conductors include a first layer and a second layer formed on the first layer such that the first layer in each of the via conductors is covering an inner wall surface in a respective via opening and has a first portion and a second portion electrically connected to the first portion and that the first portion has a portion formed closer to a center of the respective via opening than the second portion (Fig. 1A (shown)).”
In regards to claim 2, Kaneda discloses;” The wiring substrate according to claim 1, wherein the first build-up part is formed such that the wirings in the first conductor layers have an aspect ratio in a range of 2.0 to 4.0 (paragraph 0079 where width of 2 μm and thickness of 1 μm meet requirements).”
In regards to claim 3, Kaneda discloses;” The wiring substrate according to claim 1, wherein the first build-up part is formed such that the wirings in the first conductor layers have a minimum wiring width of 3 μm or less and a minimum inter-wiring distance of 3 μm or less (paragraph 0079).”
In regards to claim 4, Kaneda discloses;” The wiring substrate according to claim 1, wherein the first build-up part is formed such that the first portion in the first layer of each of the via conductors has a front end part formed closer to the center of the respective via opening than a rear end part of the second portion in the first layer of each of the via conductors (Fig. 1B shows via smaller at bottom than top).”
In regards to claim 5, Kaneda discloses;” The wiring substrate according to claim 1, wherein the first build-up part is formed such that the first portion and second portion in the first layer of each of the via conductors are formed in a same process (paragraph’s 0045 0059-0063).”
In regards to claim 6, Kaneda discloses;” The wiring substrate according to claim 1, wherein the first build-up part is formed such that the first portion and second portion in the first layer of each of the via conductors are formed in a same process (paragraph’s 0045 0059-0063).”
In regards to claim 7, Kaneda discloses;” The wiring substrate according to claim 1, wherein the first build-up part is formed such that the first layer of each of the via conductors includes a lower layer covering the inner wall surface and an upper layer formed on the lower layer and that the lower layer has a lower-layer first portion in the first portion and a lower-layer second portion in the second portion (paragraph’s 0080 0123 discloses a seed layer is commonly used to form vias).”
In regards to claim 8, Kaneda discloses;” The wiring substrate according to claim 7, wherein the lower-layer first portion has a lower-layer front end part formed closer to the center of the respective via opening than a lower-layer rear end part of the lower-layer second portion (Fig 1A (shows all vias have a bottom smaller than the top and the high density layer vias are smaller at the bottom than the low density vis bottom).”
In regards to claim 9, Kaneda discloses;” The wiring substrate according to claim 7, wherein the lower layer has a steplike shape (Fig. 5B (shows vias have a step top as disclosed by applicant).”
In regards to claim 10, Kaneda discloses;” The wiring substrate according to claim 1, wherein the first build-up part is formed such that the first insulating layers include resin and filler particles having flat parts such that the flat parts of the filler particles and the resin are forming the inner wall surface in the respective via opening (paragraph 0078).”
In regards to claim 12, Kaneda discloses;” The wiring substrate according to claim 1, wherein the first build-up part is formed such that the respective via opening has a shape reduced in diameter in a direction from the second build-up part toward the first build-up part (Fig. 1A (shown)).”
In regards to claim 13, Kaneda discloses;” The wiring substrate according to claim 1, wherein the first build-up part is formed such that each of the first conductor layers has a thickness of 7 μm or less (paragraph 0079), and the second build-up part is formed such that each of the second conductor layers has a thickness of 10 μm or more (paragraph 0058).”
In regards to claim 14, Kaneda discloses;” The wiring substrate according to claim 1, further comprising: a third build-up part formed on the second build-up part on an opposite side with respect to the first build-up part and comprising a third insulating layer and a third conductor layer (Fig. 1A shows core (20) with a third wiring (41,42,43,44,45) build up).”
In regards to claim 15, Kaneda discloses;” The wiring substrate according to claim 2, wherein the first build-up part is formed such that the wirings in the first conductor layers have a minimum wiring width of 3 μm or less and a minimum inter-wiring distance of 3 μm or less (paragraph 0079).”
In regards to claim 16, Kaneda discloses;” The wiring substrate according to claim 2, wherein the first build-up part is formed such that the first portion in the first layer of each of the via conductors has a front end part formed closer to the center of the respective via opening than a rear end part of the second portion in the first layer of each of the via conductors (Fig. 1A shows all via have a smaller bottom than top).”
In regards to claim 17, Kaneda discloses;” The wiring substrate according to claim 2, wherein the first build-up part is formed such that the first portion and second portion in the first layer of each of the via conductors are formed in a same process (paragraph’s 0045 0059-0063).”
In regards to claim 18, Kaneda discloses;” The wiring substrate according to claim 2, wherein the first build-up part is formed such that the first layer formed on the inner wall surface has a step-like shape (Fig. 1B (shows vias have a step top as disclosed by applicant).”
In regards to claim 19, Kaneda discloses;” A method for manufacturing a wiring substrate (abstract, paragraph 0005), comprising: forming a first build-up part comprising a plurality of first insulating layers and a plurality of first conductor layers (Fig. 1A (12)), and a plurality of via conductors; and forming a second build-up part comprising a plurality of second insulating layers and a plurality of second conductor layers such that the second build-up part is laminated on the first build-up part (Fig. 1A (11)), that a minimum wiring width of wirings in the first conductor layers is smaller than a minimum wiring width of wirings in the second conductor layers (Fig. 1A (shown, paragraph 0054)), and that a minimum inter-wiring distance of the wirings in the first conductor layers is smaller than a minimum inter-wiring distance of the wirings in the second conductor layers (paragraph’s 0057 and 0079 give the sizes)), wherein the first build-up part is formed such that the first conductor layers and the via conductors includes a first layer and a second layer formed on the first layer such that the first layer in each of the via conductors is covering an inner wall surface in a respective via opening and has a first portion and a second portion electrically connected to the first portion and that the first portion has a portion formed closer to a center of the respective via opening than the second portion (paragraph’s 0080 0123 discloses a seed layer is commonly used to form vias).”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 11 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kaneda et al. (US 20150102510 hereinafter Kaneda) as applied to claims 10 and 19 above, and further in view of HWANG et al. (US 20220071716 hereinafter Hwang).
In regards to claim 11, Kaneda discloses;” The wiring substrate according to claim 10”, but does not directly disclose;” wherein the first build-up part is formed such that the inner wall surface in the respective via opening has steps formed between the resin and the flat parts.”
However, Kaneda does disclose that insulation layers made of a thermosetting resin containing a filler and would have some particles of the filler exposed when forming a via structure in the insulation layer.
Hwang discloses a structure of insulation layers containing a resin and a filler (paragraph 0008).
As shown in Fig. 13, when some portion of the filler particles are remover (paragraph’s 0120, 0141, 0142) creating a surface roughness. And when a seed layer is applied, steps are formed on the side walls of the via structure. It would have been within the capabilities of a skilled artisan to understand that surface roughness would produce a similar result in other via structures. Therefore, using the teachings of Hwang with that of Kaneda, the claimed invention is disclosed.
In regards to claim 20, Kaneda discloses;” The method of claim 19, wherein the forming the first build-up part includes forming the plurality of first insulating layers comprising resin and filler particles and forming a plurality of via openings for the via conductors in the first insulating layers (Paragraph’s 0077-0080”, but does not directly disclose;” such that protruding portions of the filler particles protruding from inner wall surfaces in the via openings are removed and that the resin and the filler particles having flat parts form the inner wall surfaces in the via openings.”
Hwang discloses a structure of insulation layers containing a resin and a filler (paragraph 0008).
As shown in Fig. 13, when some portion of the filler particles are remover (paragraph paragraph’s 0120, 0141, 0142) and that the filler is a flat surface that is formed on the inner surface of the via wall.
It would have been within the capabilities of a skilled artisan to understand that removal of the filler when forming a via would produce a similar result in other via structures. Therefore, using the teachings of Hwang with that of Kaneda, the claimed invention is disclosed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL F MCALLISTER whose telephone number is (571)272-2453. The examiner can normally be reached Monday-Friday 7 AM-4 PM.
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/MICHAEL F MCALLISTER/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847