DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) filed on April 3, 2024 has been considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of claims 1-15 drawn to Group I in the reply filed on August 19, 2026 is acknowledged. Examiner further acknowledges the addition of claims 21-25 by means of amendment. Claims 21-25 appear to be commensurate with elected Group I (claims 1-15) and no new matter is present.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7-9, 14, and 24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 7 and 14 recite the limitation "the source/drain structures include a dielectric spacer on sidewalls of an epitaxially grown, doped semiconductor between the epitaxially grown, doped semiconductor and the platform". It is unclear if the “epitaxially grown, doped semiconductor” or the “dielectric spacer” is “between the epitaxially grown, doped semiconductor and the platform” and the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of this limitation.
For purposes of Examination, the Examiner will interpret “the source/drain structures include a dielectric spacer on sidewalls of an epitaxially grown, doped semiconductor between the epitaxially grown, doped semiconductor and the platform” as “the source/drain structures include a dielectric spacer on sidewalls of an epitaxially grown, doped semiconductor, wherein the dielectric spacer is between the epitaxially grown, doped semiconductor and the platform”.
Claim 24 recites the limitation "forming the source/drain structures comprises epitaxially growing a doped semiconductor such that the dielectric spacer is on sidewalls of the epitaxially grown, doped semiconductor between the epitaxially grown, doped semiconductor and the platform". It is unclear if the “epitaxially grown, doped semiconductor” or the “dielectric spacer” is “between the epitaxially grown, doped semiconductor and the platform” and the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of this limitation.
For purposes of examination, the Examiner will interpret “forming the source/drain structures comprises epitaxially growing a doped semiconductor such that the dielectric spacer is on sidewalls of the epitaxially grown, doped semiconductor between the epitaxially grown, doped semiconductor and the platform” as “forming the source/drain structures comprises epitaxially growing a doped semiconductor such that the dielectric spacer is on sidewalls of the epitaxially grown, doped semiconductor, wherein the dielectric spacer is between the epitaxially grown, doped semiconductor and the platform.”
The balance of claims are rejected for being dependent upon an already rejected claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4, 7-10, and 21-25 are rejected under 35 U.S.C. 103 as being unpatentable over PARK (US 20230027413 A1) in view of HASAN (US 20230197855 A1).
Claim 1, PARK discloses a semiconductor device (field-effect transistor device, Annotated Fig. 13), comprising:
a substrate (substrate 102, Annotated Fig. 13);
a channel layer (active layer 108a, hereinafter channel layer 108a, is formed on substrate 102, [0029], Annotated Fig. 13);
a gate stack on and around the channel layer 108a (stack 100, hereinafter gate stack 100, includes a work function metal layer that is formed in the voids that fully surround portions of the channel layer 108a, [0056], Annotated Fig. 13); and
first sidewall spacers on the gate stack 100, above the channel layer 108a (first spacer layer 302`, hereinafter first sidewall spacers 302`, are on the gate stack 100, above the channel layer 108a, Annotated Fig. 13); and
source/drain structures (source/drain regions 702, hereinafter source/drain structures 702, are formed, [0045], Annotated Fig. 13).
PARK does not explicitly disclose the semiconductor device, comprising:
the substrate having a platform that is raised relative to a remainder of a top surface of the substrate, wherein the platform includes a stepped profile with a top portion having a smaller width than a width of a base portion;
the channel layer over the platform; and
the source/drain structures over the platform.
However, HASAN discloses a semiconductor device (gate-all-around integrated circuit structure, [0006], First Annotated Fig. 4), comprising:
a substrate having a platform that is raised relative to a remainder of a top surface of the substrate (substrate 102 having a sub-fin 104, hereinafter platform 104, protruding through isolation structures 106, [0024], First Annotated Fig. 4), wherein the platform 104 includes a stepped profile (stepped profile in First Annotated Fig. 4) with a top portion having a smaller width than a width of a base portion (top portion is visually shown to have a smaller width than the width of the bottom portion of the stepped profile in First Annotated Fig. 4);
a channel layer over the platform 104 (nanowires 108, hereinafter channel layer 108, are silicon nanowires and can be considered a channel layer over platform 104, [0033], First Annotated Fig. 4); and
source/drain structures over the platform 104 (portions of source or drain structures 124, hereinafter source/drain structures 124, that are over platform 104 are outlined in Second Annotated Fig. 4).
Devices like gate-all-around (GAA) transistors have been introduced to reduce off-state current and short-channel effects. Forming platforms with stepped profiles in the substrate further electrically isolates adjacent devices which reduces off-state current and short-channel effects and in turn improves device performance and reliability.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by PARK with the teachings of HASAN by forming a platform in the substrate with a stepped profile to reduce off-state current and short-channel effects and in turn improves device performance and reliability.
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PARK Annotated Figure 13
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HASAN First Annotated Figure 4
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HASAN Second Annotated Figure 4
Claim 2, the combination of PARK and HASAN teaches the semiconductor device of claim 1.
PARK further discloses wherein the first sidewall spacers have an L-shaped cross-section, with a lower portion extending laterally into the gate stack (first spacer layer 302`, hereinafter first sidewall spacers 302`, has an L-shaped cross section, and has a lower portion extending laterally into the gate stack 100, Annotated Fig. 13).
Claim 3, the combination of PARK and HASAN teaches the semiconductor device of claim 1.
The combination of PARK and HASAN does not explicitly teach wherein the channel layer and the source/drain structures have approximately the same width as the width of the top portion of the platform.
However, HASAN teaches the channel layer 108 and the source/drain structures 124 have approximately the same width as the width of the top portion of the platform 104 (First Annotated Fig. 4 shows the width of the channel layer 108, the width of the source/drain structures 124, and the width of the top portion of the platform 104 having approximately the same width).
The width of the channel layer, width of the source/drain structures, and width of the top portion of the platform are result effective variables as one would have chosen them to suppress short channel effects and increase electrostatic control.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention taught by the combination of PARK and HASAN with the claimed limitation disclosed by HASAN as it would merely result in an optimization of a result effective variable.
Claim 4, the combination of PARK and HASAN teaches the semiconductor device of claim 1.
PARK further discloses the semiconductor device of claim 1, further comprising a self-aligned substrate isolation layer between the gate stack 100, and the substrate 102 (bottom dielectric isolation layer 306, hereinafter self-aligned substrate isolation layer 306, is formed, [0038], Annotated Fig. 13; self-aligned substrate isolation layer 306, is between the gate stack 100 and substrate 102, Annotated Fig. 13).
PARK does not explicitly disclose the self-aligned substrate isolation layer between the gate stack and the platform.
However, HASAN discloses a substrate having a platform (platform 104 [0024], First Annotated Fig. 4).
Devices like gate-all-around (GAA) transistors have been introduced to reduce off-state current and short-channel effects. Forming platforms with stepped profiles in the substrate further electrically isolates adjacent devices which reduces off-state current and short-channel effects and in turn improves device performance and reliability.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by the combination of PARK and HASAN with the teachings of HASAN by forming a platform in the substrate with a stepped profile to reduce off-state current and short-channel effects and in turn improves device performance and reliability.
Claim 7, the combination of PARK and HASAN teaches the semiconductor device of claim 1.
PARK further discloses wherein the source/drain structures 702 include a dielectric spacer on sidewalls of an epitaxially grown, doped semiconductor (source/drain structures 702 include a first spacer layer 302, hereinafter dielectric spacer 302, on sidewalls of source/drain structures 702 facing the surface of substrate 102, Annotated Fig. 13; source/drain structures 702 are formed from an epitaxially grown and doped semiconductor, [0045]), wherein the dielectric spacer 302 is between the epitaxially grown, doped semiconductor and the substrate 102 (dielectric spacer 302 is between the source/drain structures 702 - comprising an epitaxially grown, doped semiconductor - and the substrate 102, Annotated Fig. 13).
PARK does not explicitly disclose wherein the dielectric spacer is between the epitaxially grown, doped semiconductor and the platform.
However, HASAN discloses a substrate having a platform (platform 104 [0024], First Annotated Fig. 4).
Devices like gate-all-around (GAA) transistors have been introduced to reduce off-state current and short-channel effects. Forming platforms with stepped profiles in the substrate further electrically isolates adjacent devices which reduces off-state current and short-channel effects and in turn improves device performance and reliability.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by the combination of PARK and HASAN with the teachings of HASAN by forming a platform in the substrate with a stepped profile to reduce off-state current and short-channel effects and in turn improves device performance and reliability.
Claim 8, the combination of PARK and HASAN teaches the semiconductor device of claim 7.
PARK further discloses wherein the dielectric spacer 302 has a flat interface with the sidewalls of the epitaxially grown, doped semiconductor (sidewalls of source/drain structures 702 share a flat interface with dielectric spacer 302, Annotated Fig. 13; source/drain structures 702 are formed from an epitaxially grown and doped semiconductor, [0045]).
Claim 9, the combination of PARK and HASAN teaches the semiconductor device of claim 7.
PARK further discloses wherein the source/drain structures 702 lack channel remnants on the dielectric spacer 302 (source/drain structures 702 are shown to lack channel remnants on the dielectric spacer 302 in Annotated Fig. 13; source/drain structures 702 are not disclosed having channel remnants).
Claim 10, the combination of PARK and HASAN teaches the semiconductor device of claim 1.
The combination of PARK and HASAN does not explicitly teach the semiconductor device of claim 1 further comprising shallow trench isolation (STI) structures on respective sides of the platform, wherein top surfaces of the STI structures have the same height as a top surface of the base portion of the platform.
However, HASAN discloses a semiconductor device (gate-all-around integrated circuit structure, [0006], Second Annotated Fig. 4) comprising shallow trench isolation (STI) structures on respective sides of the platform, wherein top surfaces of the STI structures have the same height as a top surface of the base portion of the platform (isolation structures 106, hereinafter STI structures 106, are on both sides of the platform 104 and have top surfaces that have the same height as the base portion of the platform, Second Annotated Fig. 4).
Devices like gate-all-around (GAA) transistors have been introduced to reduce off-state current and short-channel effects. Forming platforms with stepped profiles in the substrate and forming STI structures in the trenches between them further electrically isolate adjacent devices which reduces off-state current and short-channel effects and in turn improves device performance and reliability.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by the combination of PARK and HASAN with the teachings of HASAN by forming a platform in the substrate with a stepped profile and STI structures in the trenches between them to reduce off-state current and short-channel effects and in turn improves device performance and reliability.
In addition, the height of top surfaces of the STI structures is a result effective variable as one would have chosen the height of top surfaces of the STI structures to make the STI structures high enough to electrically isolate adjacent devices without touching the channel layer.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention disclosed by the combination of PARK and HASAN with the claimed limitation disclosed by HASAN as it would merely result in an optimization of a result effective variable.
Claim 21, PARK discloses a method of forming a semiconductor device (field-effect transistor device, Annotated Fig. 13), comprising:
forming a channel layer over a substrate (active layer 108a, hereinafter channel layer 108a, is formed over substrate 102, [0029], Annotated Fig. 13);
forming first sidewall spacers above the channel layer 108a (first spacer layer 302`, hereinafter first sidewall spacers 302`, is above the channel layer 108a, Annotated Fig. 13; first spacer layer is deposited, [0038]);
forming source/drain structures over the substrate 102 (source/drain regions 702, hereinafter source/drain structures 702, are formed, [0045], Annotated Fig. 13); and
forming a gate stack on and around the channel layer 108a (stack 100, hereinafter gate stack 100, includes a work function metal layer that is formed in the voids that fully surround portions of the channel layer 108a, [0056], Annotated Fig. 13), wherein the first sidewall spacers 302` are on the gate stack 100 (first sidewall spacers 302`, are on the gate stack 100, Annotated Fig. 13).
PARK does not explicitly disclose a method of forming the semiconductor device, comprising:
forming, in the substrate beneath the channel layer, a platform that is raised relative to a remainder of a top surface of the substrate, wherein the platform includes a stepped profile with a top portion having a smaller width than a width of a base portion; and
forming source/drain structures over the platform.
However, HASAN discloses a method of fabricating a semiconductor device (a method of fabricating a semiconductor device, [0023]), comprising:
forming, in a substrate beneath a channel layer, a platform that is raised relative to a remainder of a top surface of the substrate (substrate 102 having a sub-fin 104, hereinafter platform 104, protruding through isolation structures 106, [0024], First Annotated Fig. 4; a method of fabricating a semiconductor device includes a starting structure that further includes platform 104, [0024]), wherein the platform 104 includes a stepped profile (stepped profile in First Annotated Fig. 4) with a top portion having a smaller width than a width of a base portion (top portion is visually shown to have a smaller width than the width of the bottom portion of the stepped profile in First Annotated Fig. 4);
forming source/drain structures over the platform 104 (outer portions of source or drain structures 124, hereinafter source/drain structures 124, including the portions over platform 104 are formed by epitaxial growth, [0027], Second Annotated Fig. 4).
Devices like gate-all-around (GAA) transistors have been introduced to reduce off-state current and short-channel effects. Forming platforms with stepped profiles in the substrate further electrically isolates adjacent devices which reduces off-state current and short-channel effects and in turn improves device performance and reliability.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by PARK with the teachings of HASAN by forming a platform in the substrate with a stepped profile to reduce off-state current and short-channel effects and in turn improves device performance and reliability.
Claim 22, the combination of PARK and HASAN teaches the method of claim 21.
PARK further discloses the method of claim 21, wherein the first sidewall spacers 302` have an L-shaped cross-section, with a lower portion extending laterally into the gate stack 100 (first sidewall spacers 302` have an L-shaped cross section and have a lower portion extending laterally into the gate stack 100, Annotated Fig. 13).
Claim 23, the combination of PARK and HASAN teaches the method of claim 21.
PARK further discloses the method of claim 21, further comprising forming a self-aligned substrate isolation layer between the gate stack 100, and the substrate 102 (bottom dielectric isolation layer 306, hereinafter self-aligned substrate isolation layer 306, is formed, [0038], Annotated Fig. 13; self-aligned substrate isolation layer 306, is between the gate stack 100 and substrate 102, Annotated Fig. 13).
PARK does not explicitly disclose forming the self-aligned substrate isolation layer between the gate stack and the platform.
However, HASAN discloses a substrate having a platform (platform 104 [0024], First Annotated Fig. 4).
Devices like gate-all-around (GAA) transistors have been introduced to reduce off-state current and short-channel effects. Forming platforms with stepped profiles in the substrate further electrically isolates adjacent devices which reduces off-state current and short-channel effects and in turn improves device performance and reliability.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by the combination of PARK and HASAN with the teachings of HASAN by forming a platform in the substrate with a stepped profile to reduce off-state current and short-channel effects and in turn improves device performance and reliability.
Claim 24, the combination of PARK and HASAN teaches the method of claim 21.
PARK further discloses the method of claim 21, further comprising, before forming the source/drain structures 702, forming a dielectric spacer (isolation layer 306 is formed and further comprises first spacer layer 302, hereinafter dielectric spacer 302, therefore dielectric spacer 302 is formed, [0038]), wherein forming the source/drain structures 702 comprises epitaxially growing a doped semiconductor such that the dielectric spacer 302 is on sidewalls of the epitaxially grown, doped semiconductor (source/drain structures 702 are formed from an epitaxially grown and doped semiconductor, [0045]; source/drain structures 702 include dielectric spacer 302, on sidewalls facing the surface of substrate 102, Annotated Fig. 13), wherein the dielectric spacer 302 is between the epitaxially grown, doped semiconductor and the substrate 102 (source/drain structures 702 are formed from an epitaxially grown and doped semiconductor, [0045]; dielectric spacer 302, is between source/drain structures 702 and substrate 102, Annotated Fig. 13).
PARK does not explicitly disclose wherein the dielectric spacer is between the epitaxially grown, doped semiconductor and the platform.
However, HASAN discloses a substrate having a platform (platform 104 [0024], First Annotated Fig. 4).
Devices like gate-all-around (GAA) transistors have been introduced to reduce off-state current and short-channel effects. Forming platforms with stepped profiles in the substrate further electrically isolates adjacent devices which reduces off-state current and short-channel effects and in turn improves device performance and reliability.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by the combination of PARK and HASAN with the teachings of HASAN by forming a platform in the substrate with a stepped profile to reduce off-state current and short-channel effects and in turn improves device performance and reliability.
Claim 25, the combination of PARK and HASAN teaches the method of claim 21.
The combination of PARK and HASAN does not explicitly teach the method of claim 21 further comprising forming shallow trench isolation (STI) structures on respective sides of the platform, wherein top surfaces of the STI structures have the same height as a top surface of the base portion of the platform.
However, HASAN discloses a method of fabricating a semiconductor device (a method of fabricating a semiconductor device, [0023]) comprising shallow trench isolation (STI) structures on respective sides of the platform, wherein top surfaces of the STI structures have the same height as a top surface of the base portion of the platform (isolation structures 106, hereinafter STI structures 106, are on both sides of the platform 104 and have top surfaces that have the same height as the base portion of the platform, Second Annotated Fig. 4; a method of fabricating a semiconductor device includes a starting structure that further includes isolation structures 106, [0024]).
Devices like gate-all-around (GAA) transistors have been introduced to reduce off-state current and short-channel effects. Forming platforms with stepped profiles in the substrate and forming STI structures in the trenches between them further electrically isolate adjacent devices which reduces off-state current and short-channel effects and in turn improves device performance and reliability.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by the combination of PARK and HASAN with the teachings of HASAN by forming a platform in the substrate with a stepped profile and STI structures in the trenches between them to reduce off-state current and short-channel effects and in turn improves device performance and reliability.
In addition, the height of top surfaces of the STI structures is a result effective variable as one would have chosen the height of top surfaces of the STI structures to make the STI structures high enough to electrically isolate adjacent devices without touching the channel layer.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention disclosed by the combination of PARK and HASAN with the claimed limitation disclosed by HASAN as it would merely result in an optimization of a result effective variable.
Claims 5-6, 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over PARK in view of HASAN further in view of Chung (US 20220037497 A1).
Claim 5, the combination of PARK and HASAN teaches the semiconductor device of claim 4.
The combination of PARK and HASAN does not explicitly teach wherein the self-aligned substrate isolation layer has a width that is approximately the same as the width of the base portion of the platform.
However, Chung teaches a self-aligned substrate isolation layer having a width that is approximately the same as the width of the base portion of the platform (Annotated Fig. 3B shows self-aligned substrate isolation layer 210 having a width that is approximately the same as the width of the base portion of the platform).
The width of the self-aligned substrate isolation layer is a result effective variable as one would have chosen the width of the self-aligned substrate isolation layer to electrically isolate the semiconductor device above it from the substrate platform under the self-aligned substrate isolation layer.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention disclosed by the combination of PARK and HASAN with the claimed limitation disclosed by Chung as it would merely result in an optimization of a result effective variable.
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Chung Annotated Fig 3B
Claim 6, the combination of PARK and HASAN teaches the semiconductor device of claim 4.
The combination of PARK and HASAN does not explicitly teach the semiconductor device of claim 4, wherein the self-aligned substrate isolation layer includes a portion that extends vertically along sidewalls of the top portion of the platform.
However, Chung discloses a self-aligned substrate isolation layer including a portion that extends vertically along sidewalls of the top portion of a platform (first liner 210, hereinafter self-aligned substrate isolation layer 210, may include silicon nitride and includes a portion that extends vertically along the sidewalls of a substrate 202 comprising a top portion of a platform, [0030], Annotated Fig. 3B).
When forming a material layer over a substrate, such as a substrate isolation layer, a multi-patterning processes combining photolithography and self-aligned processes, allows patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process (Chung, [0030]). In addition a self-aligned substrate isolation layer isolates the gate and source/drain structures from the substrate and therefore helps prevent current leakage. Therefore, forming a substrate isolation layer with a multi-patterning process results in more precise alignment of the electrically isolated regions resulting from the formation of the substrate isolation layer and further results in smaller transistor sizes.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention taught by the combination of PARK and HASAN with the teachings of Chung by forming a substrate isolation layer with a multi-patterning process resulting in more precise alignment of the electrically isolated regions from the formation of the substrate isolation layer and further resulting in smaller transistor sizes.
Claim 11, PARK discloses a semiconductor device (field-effect transistor device, Annotated Fig. 13), comprising:
a substrate (substrate 102, Annotated Fig. 13);
a channel layer (active layer 108a, hereinafter channel layer 108a, is formed on substrate 102, [0029], Annotated Fig. 13);
a gate stack on and around the channel layer 108a (stack 100, hereinafter gate stack 100, includes a work function metal layer that is formed in the voids that fully surround portions of the channel layer 108a, [0056], Annotated Fig. 13);
first sidewall spacers on the gate stack 100, above the channel layer 108a, that have an L-shaped cross-section, with a lower portion extending laterally into the gate stack 100 (first spacer layer 302`, hereinafter first sidewall spacers 302`, are on the gate stack 100, above the channel layer 108a, has an L-shaped cross section, and has a lower portion extending laterally into the gate stack 100, Annotated Fig. 13);
source/drain structures (source/drain regions 702, hereinafter source/drain structures 702, are formed, [0045], Annotated Fig. 13); and
a self-aligned substrate isolation layer (bottom dielectric isolation layer 306, hereinafter self-aligned substrate isolation layer 306, is formed, [0038], Annotated Fig. 13), below the gate stack 100 (self-aligned substrate isolation layer 306 is below the gate stack 100, Annotated Fig. 13).
PARK does not explicitly disclose the semiconductor device, comprising:
the substrate having a platform that is raised relative to a remainder of a top surface of the substrate, wherein the platform includes a stepped profile with a top portion having a smaller width than a width of a base portion;
the channel layer over the platform;
source/drain structures over the platform; and
the self-aligned substrate isolation layer, between the gate stack and the platform, that includes a portion that extends vertically along sidewalls of the top portion of the platform.
However, HASAN discloses a semiconductor device (gate-all-around integrated circuit structure, [0006], First Annotated Fig. 4), comprising:
a substrate having a platform that is raised relative to a remainder of a top surface of the substrate (substrate 102 having a sub-fin 104, hereinafter platform 104, protruding through isolation structures 106, [0024], First Annotated Fig. 4), wherein the platform 104 includes a stepped profile (stepped profile in First Annotated Fig. 4) with a top portion having a smaller width than a width of a base portion (top portion is visually shown to have a smaller width than the width of the bottom portion of the stepped profile in First Annotated Fig. 4);
a channel layer over the platform 104 (nanowires 108, hereinafter channel layer 108, are silicon nanowires and can be considered a channel layer over platform 104, [0033], First Annotated Fig. 4); and
source/drain structures over the platform 104 (portions of source or drain structures 124, hereinafter source/drain structures 124, that are over platform 104 are outlined in Second Annotated Fig. 4).
Devices like gate-all-around (GAA) transistors have been introduced to reduce off-state current and short-channel effects. Forming platforms with stepped profiles in the substrate further electrically isolates adjacent devices which reduces off-state current and short-channel effects and in turn improves device performance and reliability.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by PARK with the teachings of HASAN by forming a platform in the substrate with a stepped profile to reduce off-state current and short-channel effects and in turn improves device performance and reliability.
The combination of PARK and HASAN does not explicitly disclose the semiconductor device, comprising:
a self-aligned substrate isolation layer, between a gate stack and the platform, that includes a portion that extends vertically along sidewalls of the top portion of the platform.
However, Chung discloses a semiconductor device, comprising:
a self-aligned substrate isolation layer, that includes a portion that extends vertically along sidewalls of the top portion of a platform (first liner 210, hereinafter self-aligned substrate isolation layer 210, may include silicon nitride and includes a portion that extends vertically along the sidewalls of a substrate 202 comprising a top portion of a platform, [0030], Annotated Fig. 3B).
When forming a material layer over a substrate, such as a substrate isolation layer, a multi-patterning processes combining photolithography and self-aligned processes, allows patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process (Chung, [0030]). In addition a self-aligned substrate isolation layer isolates the gate and source/drain structures from the substrate and therefore helps prevent current leakage. Therefore, forming a substrate isolation layer with a multi-patterning process results in more precise alignment of the electrically isolated regions resulting from the formation of the substrate isolation layer and further results in smaller transistor sizes.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention taught by the combination of PARK and HASAN with the teachings of Chung by forming a substrate isolation layer with a multi-patterning process resulting in more precise alignment of the electrically isolated regions from the formation of the substrate isolation layer and further resulting in smaller transistor sizes.
Claim 12, the combination of PARK, HASAN, and Chung teaches the semiconductor device of claim 11.
The combination of PARK, HASAN, and Chung does not explicitly teach wherein the channel layer and the source/drain structures have approximately the same width as the width of the top portion of the platform.
However, HASAN teaches the channel layer 108 and the source/drain structures 124 have approximately the same width as the width of the top portion of the platform 104 (First Annotated Fig. 4 shows the width of the channel layer 108, the width of the source/drain structures 124, and the width of the top portion of the platform 104 having approximately the same width).
The width of the channel layer, width of the source/drain structures, and width of the top portion of the platform are result effective variables as one would have chosen them to suppress short channel effects and increase electrostatic control.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention taught by the combination of PARK, HASAN, and Chung with the claimed limitation disclosed by HASAN as it would merely result in an optimization of a result effective variable.
Claim 13, the combination of PARK, HASAN, and Chung teaches the semiconductor device of claim 11.
The combination of PARK, HASAN, and Chung does not explicitly teach the semiconductor device of claim 11, wherein the self-aligned substrate isolation layer has a width that is approximately the same as the width of the base portion of the platform.
However, Chung teaches a self-aligned substrate isolation layer having a width that is approximately the same as the width of the base portion of the platform (Annotated Fig. 3B shows self-aligned substrate isolation layer 210 having a width that is approximately the same as the width of the base portion of the platform).
The width of the self-aligned substrate isolation layer is a result effective variable as one would have chosen the width of the self-aligned substrate isolation layer to electrically isolate the semiconductor device above it from the substrate platform under the self-aligned substrate isolation layer.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention disclosed by the combination of PARK, HASAN, and Chung with the claimed limitation disclosed by Chung as it would merely result in an optimization of a result effective variable.
Claim 14, the combination of PARK, HASAN, and Chung teaches the semiconductor device of claim 11.
PARK further discloses the semiconductor device of claim 11, wherein the source/drain structures 702 include a dielectric spacer on sidewalls of an epitaxially grown, doped semiconductor (source/drain structures 702 are formed from an epitaxially grown and doped semiconductor, [0045]; source/drain structures 702 include a first spacer layer 302, hereinafter dielectric spacer 302, on sidewalls facing the surface of substrate 102, Annotated Fig. 13), wherein the dielectric spacer 302 is between the epitaxially grown, doped semiconductor and the substrate 102 (source/drain structures 702 are formed from an epitaxially grown and doped semiconductor, [0045]; dielectric spacer 302, is between source/drain structures 702 and substrate 102, Annotated Fig. 13), wherein the dielectric spacer 302 has a flat interface with the sidewalls of the epitaxially grown, doped semiconductor (sidewalls of source/drain structures 702 share a flat interface with dielectric spacer 302, Annotated Fig. 13).
PARK does not explicitly disclose wherein the dielectric spacer is between the epitaxially grown, doped semiconductor and the platform.
However, HASAN discloses a substrate having a platform (platform 104 [0024], First Annotated Fig. 4).
Devices like gate-all-around (GAA) transistors have been introduced to reduce off-state current and short-channel effects. Forming platforms with stepped profiles in the substrate further electrically isolates adjacent devices which reduces off-state current and short-channel effects and in turn improves device performance and reliability.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by the combination of PARK, HASAN, and Chung with the teachings of HASAN by forming a platform in the substrate with a stepped profile to reduce off-state current and short-channel effects and in turn improves device performance and reliability.
Claim 15, the combination of PARK, HASAN, and Chung teaches the semiconductor device of claim 11.
The combination of PARK, HASAN, and Chung does not explicitly teach the semiconductor device of claim 11 further comprising shallow trench isolation (STI) structures on respective sides of the platform, wherein top surfaces of the STI structures have the same height as a top surface of the base portion of the platform.
However, HASAN discloses a semiconductor device (gate-all-around integrated circuit structure, [0006], Second Annotated Fig. 4) comprising shallow trench isolation (STI) structures on respective sides of the platform, wherein top surfaces of the STI structures have the same height as a top surface of the base portion of the platform (isolation structures 106, hereinafter STI structures 106, are on both sides of the platform 104 and have top surfaces that have the same height as the base portion of the platform, Second Annotated Fig. 4).
Devices like gate-all-around (GAA) transistors have been introduced to reduce off-state current and short-channel effects. Forming platforms with stepped profiles in the substrate and forming STI structures in the trenches between them further electrically isolate adjacent devices which reduces off-state current and short-channel effects and in turn improves device performance and reliability.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by the combination of PARK, HASAN, and Chung with the teachings of HASAN by forming a platform in the substrate with a stepped profile and STI structures in the trenches between them to reduce off-state current and short-channel effects and in turn improves device performance and reliability.
In addition, the height of top surfaces of the STI structures is a result effective variable as one would have chosen the height of top surfaces of the STI structures to make the STI structures high enough to electrically isolate adjacent devices without touching the channel layer.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention disclosed by the combination of PARK, HASAN, and Chung with the claimed limitation disclosed by HASAN as it would merely result in an optimization of a result effective variable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhang (US 20250309116 A1) discloses a semiconductor device including a plurality of FETs that each have similar device features (see Figs. 4A and 4B) to the claimed invention.
Sarkar (US 20250311320 A1) discloses a FET semiconductor device having similar device features (see Fig. 1) to the claimed invention.
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/MICHAEL M VANYO/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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