DETAILED ACTION
This Office Action, based on application 18/625,941 filed 3 April 2024, is entered responsive to applicant’s amendment and remarks filed 10 April 2026. Claims 1-20, 24, and 25 are currently pending and have been fully considered below.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s remarks, filed 10 April 2026 in response to the Office Action entered 16 January 2026, have been fully considered below.
Claim Objections
The list of claim objections has been updated in response to applicant’s amendment and remarks. New objections have been presented in response to newly discovered issues.
Claim Rejections under 35 U.S.C. § 103
The applicant traverses the prior art rejection alleging cited prior art fails to disclose the selection of an output page based on three concurrent factors including (1) the level of the one or more destination data pages, (2) the content of the input page, and (3) a memory reliability optimization goal further based on the level of the one or more destination pages.
The applicant alleges STROPE does not teach “selecting a page based on its content to satisfy a reliability goal associated with the page’s level” since “STROPE’s core logic is Priority => Performance”. In response, the Office asserts the STROPE reference is not solely relied upon to teach “selecting a page based on its content to satisfy a reliability goal associated with the page’s level”. The Office asserts one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). As noted in the grounds of rejection, STROPE is relied upon for teaching “assigning input pages to output pages” to which ¶[0017] of STROPE teaches page selection based on a priority of the write request. STROPE at ¶[0025] further discloses a priority level may be assigned to each page based on programming time {meeting factor (1)}, and ¶[0029] discloses priority levels of a write request may be based on the type of data (or ‘content’) {meeting factor (2)}.
The applicant acknowledges the teachings of BURGER that include teachings that a level of reliability may be achieved by using different encoding schemes for different page level and thus links page levels and reliability goals. BURGER further teaches at ¶[0057] that different encoding rates may be associated with each page including a different encoding rate may be applied based on whether the page being programmed is a lower, middle, or upper page. As such, the Office respectfully disagrees with applicant’s assertion that BURGER’s teachings do not apply to the initial selection and mapping of data since BURGER clearly acknowledges whether the page is a lower, middle, or upper page impacts how the page is programmed.
The applicant presents further arguments regarding an alleged gap in the combination of references. While the applicant alleges the combination of STROPE and BURGER manage pages by looking at metadata opposed to Claim 1 analyzing ‘actual content’ (e.g. sensitivity to corruption or its specific data pattern), the Office notes that the features upon which applicant relies (such as analyzing ‘actual content’) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Claim Objections
The following claims are objected to due to informalities:
Claim 7: Claim 1 establishes that memory reliability optimization goals are defined as a function of “the one or more destination data pages” associated with an output page. As such, a particular memory reliability optimization goal is not associated with “a given destination page”, but “the one or more destination data pages”.
Claim 7: “optimizing a balance … to be stored to destination data page.” should be “optimizing a balance … to be stored to the destination data page.”.
Claim 14: “at least a subset of the one or more data representations” should be “the at least a subset of the one or more data representations”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-5, 8, 9, 19, 20, 24, and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over STROPE (US PGPub 2013/0151764) in further view of BURGER et al (US PGPub 2014/0126288).
With respect to Claim 1, STROPE discloses a method of restructuring input data to be stored in a multi-level flash memory having a plurality of multi-level flash memory cells being arranged in multiple physical pages each having a defined number N > 1 of data pages corresponding to different levels of the multi-level flash memory (Claim 1 – “a multi-level cell memory having a same physical page configured to be programmed at different programming rates by selecting different levels of a voltage provided to cells within the same physical page”; Claim 2 – “wherein the multi-level cell memory comprises multi-level cell (MLC) NAND Flash memory”), the method comprising:
based on a defined page structure according to which the input data is segmented into multiple logical input pages, restructuring the segmented input data to obtain corresponding output data being segmented into logical output pages, wherein each output page has one or more associated destination data pages for storing content of the output page therein (¶[0013] – “host interface 105 receives access requests from the host (e.g. read and write operations”; ¶[0017] – “During operation, the write prioritizer 114 may receive a write request for data to be stored in the memory array 118. … select a page to store the data when the priority level indicates a high priority level, select a second page to store the data when the priority level indicates a low priority level”); and
outputting the segmented output data for storage to the multi-level flash memory in accordance with the associations between the output pages and their respective destination data pages (¶[0017] – “The write prioritizer 114 may … store the data associated with the write request in the selected page”); wherein the restructuring comprises:
assigning a respective corresponding input page to each respective output page (¶[0017] – “During operation, the write prioritizer 114 may receive a write request for data to be stored in the memory array 118. The write prioritizer 114 may determine a priority level of a received write request, select a page to store the data when the priority level indicates a high priority level, select a second page to store the data when the priority level indicates a low priority level, and the store the data associated with the write request in the selected page. When the priority level is indicated as high, a page having a faster programming time may be selected and when the priority level is indicated as low, a page having a slower programming time may be selected”), and wherein selecting the respective corresponding input page for assignment to the respective output page is based on:
a level of the one or more destination data pages being associated with the output page (¶[0025] – “The method 400 then determines an amount of time that each page used to be programmed, at 406. This may be accomplished by monitoring a busy status signal of the memory device to determine when a write is complete. For example, a ready signal may be received when a device has completed a write operation. Then, a priority level is assigned to each page based on its programming time, at 408. The method 400 then creates a data map, or list, indicating the priority level for each page, at 410. In a particular embodiment, the data map may indicate either a first priority level associated with a faster programming time or a second priority level associated with a slower programming time. Which programming times are considered faster or slower can be a design choice of each system. In addition, there may be more than two priority levels where each of the priority levels are associated with a range of programming times. The data map, or list, may be stored in a buffer memory and, in a particular embodiment, may include a single bit to indicate whether a page has a first priority level assigned to indicate a faster programming time or a second priority level assigned to indicate a slower programming time, where a first state of the single bit represents the first priority level and a second state of the single bit represents the second priority level”),
and a content of the input page (¶[0029] – “The method 500 then determines a priority level of the write request, at 504. The priority level of the write request may be determined based on a type of data”)
wherein the input page is selected so that the content of the output page is defined accordingly as that of the input page or the reversibly transformed version thereof (¶[0030] – “Once a page is selected based on the associated priority level, the write request is performed on the selected page, at 512”).
STROPE may not explicitly disclose wherein selecting the respective corresponding input page for assignment to the respective output page is based on a memory reliability optimization goal defined as a function of the level of the one or more destination data pages being associated with the output page, wherein the input page is selected so that the input page or a reversibly transformed version thereof satisfies the memory reliability optimization goal associated with the output page's associated one or more destination data pages.
However, BURGER discloses wherein selecting the respective corresponding input page for assignment to the respective output page is based on a memory reliability optimization goal defined as a function of the level of the one or more destination data pages being associated with the output page, wherein the input page is selected so that the input page or a reversibly transformed version thereof satisfies the memory reliability optimization goal associated with the output page's associated one or more destination data pages (¶[0057] – “the write process 800 employs a page level access scheme and novel techniques for partitioning the user data based on the page type (i.e., page level) that is being encoded. In addition, the write process 800 also employs the appropriate code rate associated with the identified page type. For example, in one exemplary implementation, the lower and middle pages of a wordline can comprise eight sectors of user data, while the upper page can comprise seven sectors of user data. Thus, if the lower or middle pages are being programmed, eight sectors of user data should be accumulated, while if the upper page is being programmed, then seven sectors of user data should be accumulated”).
STROPE and BURGER are analogous art because they are from the same field of endeavor of management of storage in multi-level cell memory devices. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of STROPE and BURGER before him or her, to modify the write prioritizer of STROPE to include page reliability considerations when assigning priority levels to each page as taught by BURGER. A motivation for doing so would have been to recognize that different page types may have different reliability issues and hence different encoding rates may be applied to the different page types which may then increase access times for the page due to encoding/decoding (¶[0039]; ¶[0075]). Therefore, it would have been obvious to combine STROPE and BURGER to obtain the invention as specified in the instant claims.
With respect to Claim 24, STROPE discloses a data processing apparatus comprising:
multi-level flash memory having a plurality of multi-level flash memory cells being arranged in multiple physical pages each having a defined number N > 1 of data pages corresponding to different levels of the multi-level flash memory (Claim 1 – “a multi-level cell memory having a same physical page configured to be programmed at different programming rates by selecting different levels of a voltage provided to cells within the same physical page”; Claim 2 – “wherein the multi-level cell memory comprises multi-level cell (MLC) NAND Flash memory”); and
one or more processors coupled to the flash memory (Fig 1, Flash Memory Controller), wherein the one or more processors having access to a program memory in which one or more programs are stored, which when executed on the one or more processors cause the data processing apparatus to perform a method of restructuring input data to be stored in the flash memory comprising:
based on a defined page structure according to which the input data is segmented into multiple logical input pages, restructuring the segmented input data to obtain corresponding output data being segmented into logical output pages, wherein each output page has one or more associated destination data pages for storing content of the output page therein (¶[0013] – “host interface 105 receives access requests from the host (e.g. read and write operations”; ¶[0017] – “During operation, the write prioritizer 114 may receive a write request for data to be stored in the memory array 118. … select a page to store the data when the priority level indicates a high priority level, select a second page to store the data when the priority level indicates a low priority level”); and
outputting the segmented output data for storage to the flash memory in accordance with the associations between the output pages and their respective destination data pages (¶[0017] – “The write prioritizer 114 may … store the data associated with the write request in the selected page”); wherein the restructuring comprises:
assigning a respective corresponding input page to each respective output page (¶[0017] – “During operation, the write prioritizer 114 may receive a write request for data to be stored in the memory array 118. The write prioritizer 114 may determine a priority level of a received write request, select a page to store the data when the priority level indicates a high priority level, select a second page to store the data when the priority level indicates a low priority level, and the store the data associated with the write request in the selected page. When the priority level is indicated as high, a page having a faster programming time may be selected and when the priority level is indicated as low, a page having a slower programming time may be selected”), and wherein selecting the respective corresponding input page for assignment to the respective output page is based on:
a level of the one or more destination data pages being associated with the output page (¶[0025] – “The method 400 then determines an amount of time that each page used to be programmed, at 406. This may be accomplished by monitoring a busy status signal of the memory device to determine when a write is complete. For example, a ready signal may be received when a device has completed a write operation. Then, a priority level is assigned to each page based on its programming time, at 408. The method 400 then creates a data map, or list, indicating the priority level for each page, at 410. In a particular embodiment, the data map may indicate either a first priority level associated with a faster programming time or a second priority level associated with a slower programming time. Which programming times are considered faster or slower can be a design choice of each system. In addition, there may be more than two priority levels where each of the priority levels are associated with a range of programming times. The data map, or list, may be stored in a buffer memory and, in a particular embodiment, may include a single bit to indicate whether a page has a first priority level assigned to indicate a faster programming time or a second priority level assigned to indicate a slower programming time, where a first state of the single bit represents the first priority level and a second state of the single bit represents the second priority level”),
and a content of the input page (¶[0029] – “The method 500 then determines a priority level of the write request, at 504. The priority level of the write request may be determined based on a type of data”);
wherein the input page is selected so that content of the output page is defined accordingly as that of the input page or its reversibly transformed version thereof (¶[0030] – “Once a page is selected based on the associated priority level, the write request is performed on the selected page, at 512”).
STROPE may not explicitly disclose wherein selecting the respective corresponding input page for assignment to the respective output page is based on a memory reliability optimization goal defined as a function of the level of the one or more destination data pages being associated with the output page, wherein the input page is selected so that the input page or a reversibly transformed version thereof satisfies the memory reliability optimization goal associated with the output page's associated one or more destination data pages.
However, BURGER discloses wherein selecting the respective corresponding input page for assignment to the respective output page is based on a memory reliability optimization goal defined as a function of the level of the one or more destination data pages being associated with the output page, wherein the input page is selected so that the input page or a reversibly transformed version thereof satisfies the memory reliability optimization goal associated with the output page's associated one or more destination data pages (¶[0057] – “the write process 800 employs a page level access scheme and novel techniques for partitioning the user data based on the page type (i.e., page level) that is being encoded. In addition, the write process 800 also employs the appropriate code rate associated with the identified page type. For example, in one exemplary implementation, the lower and middle pages of a wordline can comprise eight sectors of user data, while the upper page can comprise seven sectors of user data. Thus, if the lower or middle pages are being programmed, eight sectors of user data should be accumulated, while if the upper page is being programmed, then seven sectors of user data should be accumulated”).
STROPE and BURGER are analogous art because they are from the same field of endeavor of management of storage in multi-level cell memory devices. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of STROPE and BURGER before him or her, to modify the write prioritizer of STROPE to include page reliability considerations when assigning priority levels to each page as taught by BURGER. A motivation for doing so would have been to recognize that different page types may have different reliability issues and hence different encoding rates may be applied to the different page types which may then increase access times for the page due to encoding/decoding (¶[0039]; ¶[0075]). Therefore, it would have been obvious to combine STROPE and BURGER to obtain the invention as specified in the instant claims.
With respect to Claim 2, the combination of STROPE and BURGER disclose the method of claim 1.
STROPE further discloses wherein for each output page, selecting the respective corresponding input page comprises determining for each of the input pages a respective associated indicator that characterizes the input page; and selecting the input page for assignment to the output page comprises: comparing of the associated respective indicators of multiple input pages with the priority related to the level of the one or more destination data pages being associated with the output page, and determining one input page among the multiple input pages, which the one input page or the reversibly transformed version thereof satisfies the priority, as the selected input page (¶[0018] – “The write prioritizer 114 may determine the priority level by checking a data map, or list, of pages that indicates whether a selected page has a fast programming time or a slow programming time. The data map may be stored in a memory, such as the buffer memory 116 or the memory 106, and may include a list of pages and an indicator of a priority level associated with each page, where the indicator of the priority level is based on a programming time associated with the associated page”; ¶[0020] – “The priority level of a write request may be determined based on a type of data, an indicator from the host, an amount of the volatile memory 106 filled, an amount of the buffer memory 116 filled, a fill rate of either buffer, or any combination thereof. Further, the flash memory controller 102 may be configured to receive, via the host interface 105, an indicator of a user selectable setting to initially store all data to pages associated with a fast programming time”).
BURGER further discloses wherein the priority is based on the memory reliability optimization goal (¶[0039 – “more powerful codes or lower code rates can be employed for the pages that need improved reliability”; ¶[0047] – “a lower page level can be encoded at a higher code rate than the middle and upper page levels (or vice versa). In one variation, some page levels with sufficient reliability may not be encoded at all”).
With respect to Claim 3, the combination of STROPE and BURGER disclose the method of claim 2.
STROPE further discloses wherein the associated indicator of an input page is a function of a number of bits within the input page with a same predetermined bit value (¶[0020] – “The priority level of a write request may be determined based on a type of data, an indicator from the host”; ¶[0019] – “the indicator may indicate more priority levels than just two, with each priority level being associated with a different programming speed.”).
With respect to Claim 4, the combination of STROPE and BURGER disclose the method of claim 1.
STROPE further discloses wherein: the input data is randomized, and before the restructuring, the input pages are defined based on the randomized input data (¶[0013] – “host interface 105 receives access requests from the host (e.g. read and write operations”; ¶[0017] – “During operation, the write prioritizer 114 may receive a write request for data to be stored in the memory array 118).
With respect to Claim 5, the combination of STROPE and BURGER disclose the method of claim 1.
BURGER further discloses wherein the respective memory reliability optimization goal associated with the one or more destination data pages is selected as a function of the level of the one or more destination data pages as one of the following: maximizing a number of "0" bit values to be stored to the destination data page; maximizing a number of "1" bit values to be stored to the destination data page; optimizing a balance between "0" bit values and "1" bit values to be stored to the destination data page (¶[0039 – “more powerful codes or lower code rates can be employed for the pages that need improved reliability”; ¶[0047] – “a lower page level can be encoded at a higher code rate than the middle and upper page levels (or vice versa). In one variation, some page levels with sufficient reliability may not be encoded at all”; ¶[0003] – “In addition, using QLC memory cells may involve complicated encoding schemes for the four levels of data stored per memory cell. For example, 1-2-6-6, 1-2-4-8, 2-3-5-5, and other encoding schemes may be used, where each number refers to the number of state changes that occur within a memory level, i.e., how many points along that level may see a change from either a “0” to “1” or “1” to “0” memory state. Memory levels where fewer points along the level may be read to ascertain a cell's memory state, may incur a lower bit error rate (BER) than levels on which more points along the level are read to properly sense and read the data for a particular level. Conversely, memory levels where more points along the level (i.e., more memory states) may be read to ascertain a cell's memory state may incur a higher BER than levels on which fewer points along the level are read to properly sense and read the data for a particular level”).
With respect to Claim 8, the combination of STROPE and BURGER disclose the method of claim 5.
BURGER further discloses wherein: maximizing a number of "0" bit values is defined as satisfying the condition that the number of bits in an input page or a reversibly transformed version thereof which have a bit value of one is less than a defined upper threshold; maximizing a number of "1" bit values is defined as satisfying the condition that the number of bits in an input page or a reversibly transformed version thereof which have a bit value of one is greater than a defined lower threshold; or optimizing a balance between "0" bit values and "1" bit values is defined as satisfying a condition that the number of bits in an input page or a reversibly transformed version thereof which have a bit value of one is greater than a defined lower threshold and less than a defined upper threshold (¶[0039 – “more powerful codes or lower code rates can be employed for the pages that need improved reliability”; ¶[0047] – “a lower page level can be encoded at a higher code rate than the middle and upper page levels (or vice versa). In one variation, some page levels with sufficient reliability may not be encoded at all”; ¶[0003] – “In addition, using QLC memory cells may involve complicated encoding schemes for the four levels of data stored per memory cell. For example, 1-2-6-6, 1-2-4-8, 2-3-5-5, and other encoding schemes may be used, where each number refers to the number of state changes that occur within a memory level, i.e., how many points along that level may see a change from either a “0” to “1” or “1” to “0” memory state. Memory levels where fewer points along the level may be read to ascertain a cell's memory state, may incur a lower bit error rate (BER) than levels on which more points along the level are read to properly sense and read the data for a particular level. Conversely, memory levels where more points along the level (i.e., more memory states) may be read to ascertain a cell's memory state may incur a higher BER than levels on which fewer points along the level are read to properly sense and read the data for a particular level”).
With respect to Claim 9, the combination of STROPE and BURGER disclose the method of claim 1.
STROPE further discloses wherein when multiple input pages or their reversibly transformed versions, respectively, satisfy a priority associated with the one or more destination data pages being associated with a given output page, an input page among these multiple input pages is selected for assignment to the given output page for which a degree that quantifies a satisfaction of the priority is maximized among the multiple input pages (¶[0030] – “A priority level decision may be made, at 506. When the priority level of the write request is a first priority level, such as a priority level associated with a faster write, a first page may be selected to store the data when the first page is associated with the first priority level via the data map, at 508. When the priority level of the write request is a second priority level, such as a priority level associated with a slower write, a second page may be selected to store the data when the second page is associated with the second priority level via the data map, at 510. Once a page is selected based on the associated priority level, the write request is performed on the selected page, at 512”.).
BURGER further discloses wherein the priority is based on the memory reliability optimization goal (¶[0039 – “more powerful codes or lower code rates can be employed for the pages that need improved reliability”; ¶[0047] – “a lower page level can be encoded at a higher code rate than the middle and upper page levels (or vice versa). In one variation, some page levels with sufficient reliability may not be encoded at all”).
With respect to Claim 19, the combination of STROPE and BURGER disclose the method of claim 1.
BURGER further discloses wherein the input data is provided or stored in a cache memory other than the multi-level flash memory and the restructuring of the input data is performed in relation to the input data stored in the cache memory to obtain the output data (¶[0050] – “It is noted that during step 510 one or more pages may require buffering, for example, using memory circuits in the data management block 110, until three full pages of data are available (for the exemplary 3-bit-per-cell embodiment of FIG. 3). Thereafter, the wordline level write process 500 encodes j pages of data into an encoded block during step 520”).
With respect to Claim 20, the combination of STROPE and BURGER disclose the method of claim 1.
BURGER further discloses wherein respective memory reliability optimization goals associated with the one or more destination data pages are each defined as a function of a calibration parameter which defines a common reliability margin of the respective memory reliability optimization goals (¶[0039] – “each page in a wordline can optionally be encoded with different code rates or different types of codes (or both). For example, Low Density Parity Check Codes (LDPC), Bose-Chaudhuri-Hocquenghem (BCH) and Reed Solomon (RS) codes may be employed. In one embodiment, more powerful codes or lower code rates can be employed for the pages that need improved reliability. For example, higher page numbers may have a higher likelihood of error. Thus, these pages may be encoded with a code or code rate (or both) that improve the performance of these pages. More powerful error correcting codes (such as lower rate codes and LDPC codes) can be used for the higher pages associated with a higher error rate, and less powerful error correcting codes (such as higher rate codes and algebraic codes) can be used for the lower pages associated with a lower error rate”).
With respect to Claim 25, the combination of STROPE and BURGER disclose the data processing apparatus of claim 24.
STROPE further discloses wherein for each output page, selecting the respective corresponding input page comprises determining for each of the input pages a respective associated indicator that characterizes the input page; and selecting the input page for assignment to the output page comprises: comparing of the associated respective indicators of multiple input pages with the priority related to the level of the one or more destination data pages being associated with the output page, and determining one input page among the multiple input pages, which the one input page or the reversibly transformed version thereof satisfies the priority, as the selected input page (¶[0018] – “The write prioritizer 114 may determine the priority level by checking a data map, or list, of pages that indicates whether a selected page has a fast programming time or a slow programming time. The data map may be stored in a memory, such as the buffer memory 116 or the memory 106, and may include a list of pages and an indicator of a priority level associated with each page, where the indicator of the priority level is based on a programming time associated with the associated page”; ¶[0020] – “The priority level of a write request may be determined based on a type of data, an indicator from the host, an amount of the volatile memory 106 filled, an amount of the buffer memory 116 filled, a fill rate of either buffer, or any combination thereof. Further, the flash memory controller 102 may be configured to receive, via the host interface 105, an indicator of a user selectable setting to initially store all data to pages associated with a fast programming time”).
BURGER further discloses wherein the priority is based on the memory reliability optimization goal (¶[0039 – “more powerful codes or lower code rates can be employed for the pages that need improved reliability”; ¶[0047] – “a lower page level can be encoded at a higher code rate than the middle and upper page levels (or vice versa). In one variation, some page levels with sufficient reliability may not be encoded at all”).
Claim(s) 6 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over STROPE in further view of BURGER and JAIN (US PGPub 2022/0075687).
With respect to Claim 6, the combination of STROPE and BURGER disclose the method of claim 1,.
BURGER further discloses the memory reliability optimization goal applied to a destination data page is defined as a function of both a level of the destination data page and a layer to which the physical page having the destination data page pertains (¶[0039 – “more powerful codes or lower code rates can be employed for the pages that need improved reliability”; ¶[0047] – “a lower page level can be encoded at a higher code rate than the middle and upper page levels (or vice versa). In one variation, some page levels with sufficient reliability may not be encoded at all”).
STROPE and BURGER may not explicitly disclose wherein: the multi-level flash memory is a 3D NAND flash memory in which the physical pages are distributed over a plurality of stacked layers of the multi-level flash memory.
However, JAIN discloses wherein: the multi-level flash memory is a 3D NAND flash memory in which the physical pages are distributed over a plurality of stacked layers of the multi-level flash memory (¶[0106] – “The non-volatile memory array 212 can be two-dimensional (2D—laid out in a single fabrication plane) or three-dimensional (3D—laid out in multiple fabrication planes), The non-volatile memory array 212 may comprise one or more arrays of memory cells including a 3D array. In one embodiment, the non-volatile memory array 212 may comprise a monolithic three-dimensional memory structure (3D array) in which multiple memory levels are formed above (and not in) a single substrate, such as a wafer, with no intervening substrates.”)
STROPE, BURGER, and JAIN are analogous art because they are from the same field of endeavor of management of storage in multi-level cell memory devices. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of STROPE, BURGER, and JAIN before him or her, to modify the flash memory array of the combination of STROPE and BURGER to include multiple fabrication planes as taught by BURGER. A motivation for doing so would have been to recognize that 3D flash memories also exhibit different integrity characteristics based on the page level (¶[0007]) and the benefits of a 3D flash memory vs 2D flash memory may be more memory capacity per die size. Therefore, it would have been obvious to combine STROPE, BURGER, and JAIN to obtain the invention as specified in the instant claims.
With respect to Claim 7, the combination of STROPE, BURGER, and JAIN disclose the method of claim 6.
BURGER further discloses wherein the respective memory reliability optimization goal associated with a given destination data page is selected as a function of both the level of the destination data page and the layer to which the physical page having the destination data page pertains as one of the following: maximizing a number of "0" bit values to be stored to the destination data page; maximizing a number of "1" bit values to be stored to the destination data page; optimizing a balance between "0" bit values and "1" bit values to be stored to destination data page (¶[0039 – “more powerful codes or lower code rates can be employed for the pages that need improved reliability”; ¶[0047] – “a lower page level can be encoded at a higher code rate than the middle and upper page levels (or vice versa). In one variation, some page levels with sufficient reliability may not be encoded at all”; ¶[0003] – “In addition, using QLC memory cells may involve complicated encoding schemes for the four levels of data stored per memory cell. For example, 1-2-6-6, 1-2-4-8, 2-3-5-5, and other encoding schemes may be used, where each number refers to the number of state changes that occur within a memory level, i.e., how many points along that level may see a change from either a “0” to “1” or “1” to “0” memory state. Memory levels where fewer points along the level may be read to ascertain a cell's memory state, may incur a lower bit error rate (BER) than levels on which more points along the level are read to properly sense and read the data for a particular level. Conversely, memory levels where more points along the level (i.e., more memory states) may be read to ascertain a cell's memory state may incur a higher BER than levels on which fewer points along the level are read to properly sense and read the data for a particular level”).
Allowable Subject Matter
Claims 10-18 are allowed over prior art.
Exemplary Claim 10 further limits the allocation of data to particular pages of a multi-level flash memory based on characteristics of the data and characteristics of memory levels and associated pages. Claim 10 is limited to transforming incoming data prior to writing the data to flash memory “wherein the transformation scheme is defined based on the yet-untransformed input page and the memory reliability optimization goal associated with the output page's associated one or more destination data pages to reversibly replace, in the input page, one or more data representations being associated with respective first threshold voltages of the memory flash by a respective number of data representations being associated with respective second threshold voltages of the memory flash being lower than the corresponding first threshold voltages to obtain the transformed version of the input page”. While cited prior art including BURGER disclose encoding schemes to encode incoming data based on the level to which the data is to be written to in flash memory, prior art has not been found to anticipate or render obvious the transformation scheme as limited in the claim.
The Office would like to emphasize that while one or more reasons are offered as to why the claims are allowable over the prior art, it is each claim, taken as a whole, including interrelationships and interconnections between various claimed elements which are allowable over the prior art of record and not any individual limitation of a claim.
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
Claims 10-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC T LOONAN whose telephone number is (571)272-6994. The examiner can normally be reached M-F 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached at 571-272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIC T LOONAN/Examiner, Art Unit 2137
Prosecution Insights