DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendments filed 6/24/2026 have been accepted. Claims 1, 2, 7-10, 12, 14, 16, and 17 are still pending. Claims 1, 2, 7-10, 12, 16, and 17 are amended. Claim 6 has been canceled. Applicant’s amendments to the claims have overcome each and every 112 previously set forth in the Non-Final Office Action mailed 3/26/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 2, 7, 8, 12, 16, and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Independent claims 1 and 16 and claim 12 contain the limitations “wherein the first logical output is configured as a normal cache for non-speculative execution by the processor, and wherein the second logical output is configured as a shadow cache for speculative execution by the processor” which render the claims indefinite as the outputs do not constitute caches themselves, even according the applicant’s own specification (Paragraph [0306]). The logical outputs are part of the different caches mentioned, but they are not the caches themselves, which is what the claims state. This makes it unclear as to what is being said with the particular limitations. For examination purposes, the limitations will be construed to be that the logical outputs are mapped and associated with their respective logical caches.
Since the independent claims have been rendered indefinite, so too have the claims dependent upon them.
Claim Rejections - 35 USC § 103
Claims 1, 2, 7-10, 12, 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Favor et al. (US Patent 8370609, hereafter referred to as Favor) in view of Jacobi et al. (US PGPub 2019/0018780, hereafter referred to as Jacobi) in view of So et al. (US PGPub 2007/0094664, hereafter referred to as So).
Regarding claim 1, Favor teaches a system, comprising: a first cache set, a second cache set (Col. 15, lines 30-37, states that the L1 cache can be a 2-way set associative cache), wherein when the processor identifies that an execution type of instructions executed by the processor changes from speculative execution to non-speculative execution, the logic circuit is configured to: change a state of a first cache set and second cache set in response to a status of speculative execution indicating that a result of speculative execution is to be accepted (Col. 16, lines 1-52, describes the process of completing speculative operations that either involve committing the speculative operation when it is accepted (thereby becoming non-speculative as well as changing the states of the sets of the cache that the data is stored in) or rolling back the operation using the checkpoint in the VCC that would maintain the states of the cache before the speculative operation), wherein the first logical output is configured as a normal cache for non-speculative execution by the processor, and wherein the second logical output is configured as a shadow cache for speculative execution by the processor (Fig. 1 shows that each core contains L1, L2, and L3 caches to be used. Col. 3, lines 29-47, shows that processors can perform speculative execution. Col. 9, lines 42-58, discusses a versioning cache circuit used to allow for speculative requests and rollbacks if needed. Col. 15, lines 47-59, the inclusion of the versioning circuit allows for rollback to previous states upon an aborted speculation and as such contains the effects of the speculative execution to the L1 cache meaning operations to the L2 and L3 would remain non-speculative). Favor does not explicitly teach a first cache set having a first physical output; a second cache set having a second physical output, where in the first cache set and the second cache set are configured as interchangeable in the system, a first register associated with the first cache set, a second register associated with the second cache set, and a logic circuit coupled to a processor to control the first register and the second register, wherein the logic circuit includes a mapping circuit coupled to a control register to map configured to map, using the mapping circuit, the first physical output and the second physical output as a first logical output and a second logical output according to a state of the control register, according to a state of the control register, and wherein when an execution type identified by the processor changes, the logic circuit is configured to: change a state of the first register and the second register.
Jacobi teaches a first cache set having a first physical output; a second cache set having a second physical output, where in the first cache set and the second cache set are configured as interchangeable in the system (Fig. 2 and Paragraphs [0071] and [0082], show the set-associative cache setup which includes two cache sets with two physical outputs that are interchangeable depending on which set is accessed. It should be noted this is standard for set-associative caches), a first register associated with the first cache set, a second register associated with the second cache set (Paragraph [0073], states that the cache can be a two way set-associative. Fig. 5 and Paragraph [0119]-[0120], show the set registers that are used to ensure that the correct output is given by matching the incoming set ID with the content of the set register), and a logic circuit coupled to a processor to control the first register and the second register (Paragraph [0080], discusses logic circuits used to compare tags (address) to determine whether there is a hit or not), wherein when an execution type identified by the processor changes, the logic circuit is configured to: change a state of the first register and the second register (Paragraphs [0125]-[0129], states the registers may be updated if no hit occurs). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Favor to use the registers as taught in Jacobi so a cache entry may be retrieved more rapid than if searched for directly in the cache (Jacobi, Paragraph [0030]). Favor and Jacobi do not teach wherein the logic circuit includes a mapping circuit coupled to a control register configured to map, using the mapping circuit, the first physical output and the second physical output as a first logical output and a second logical output according to a state of the control register.
So teaches wherein the logic circuit includes a mapping circuit coupled to a control register configured to map, using the mapping circuit, the first physical output and the second physical output as a first logical output and a second logical output to a second logical cache according to a state of the control register (Fig. 4 and Paragraphs [0051]-[0055], discusses the partitioning of the set-associative cache between two different threads, thus creating two logical caches, one for each thread. While there is no explicit recitation of a mapping circuitry, the use of a set associative cache means that a mapping for the cache has to exist and the partitioning means that the ways are designated to one or more threads based on the priority set in the control registers. Fig. 3 and Paragraph [0038], helps confirm this with the mention of virtual-to-physical address translation and the existence of a TLB. Paragraph [0042]-[0043] and [0051]-[0053], show how control registers are used to determine the state of particular cache sets. One of ordinary skill in the art would be able to recognize that when combined with Jacobi to include the logic circuit the mapping circuit would be connected to the logic circuit as they are both part of the same system and are used in the addressing of the cache). Since both Favor/Jacobi and So teach the use of caches it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the prior art elements according to known methods to modify the teachings of Favor and Jacobi to have a mapping circuit as taught in So to obtain the predictable result of wherein the logic circuit includes a mapping circuit coupled to a control register configured to map, using the mapping circuit, the first physical output and the second physical output as a first logical output and a second logical output according to a state of the control register.
Regarding claim 2, Favor, Jacobi, and So teach all the limitations of claim 1. Jacobi further teaches wherein when a memory address is received from the processor, the logic circuit is configured to: generate a set index from at least the memory address, and determine whether the set index matches with a content stored in the first register or with a content stored in the second register, wherein the logic circuit is configured to implement a command via the first cache set in response to the set index matching with the content stored in the first register and via the second cache set in response to the set index matching with the content stored in the second register (Paragraphs [0119]-[0126], describe the use of the set registers where the set ID stored in the register is matched to a part of the received address sent down the address line so that the correct command is performed on the correct set in the cache). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 7, Favor, Jacobi, and So teach all the limitations 2. Favor further teaches a connection to a speculation-status signal line from the processor identifying the status of the speculative execution of instructions by the processor, wherein the connection to the speculation-status signal line is configured to receive the status of the speculative execution of the instructions (Col. 18, lines 10-58, describe the versioning cache circuit (VCC) which is used to roll back the L1 cache. The process involves keeping track of the status of speculative/out-of-order commands to see if they are committed or aborted. Fig. 20 and Col. 64, line 57-Col. 65 line 10 show the use of a status line into the VCC). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 8, Favor, Jacobi, and So teach all the limitations 7. Favor further teaches wherein when an execution type changes from speculative execution to non-speculative execution, the logic circuit is configured to: maintain the state of the first cache set and the second cache set without changes, if the status of speculative execution of the instructions indicates that the result of speculative execution of the instructions is to be rejected (Col. 16, lines 1-52, describes the process of completing speculative operations that either involve committing the speculative operation when it is accepted (thereby becoming non-speculative as well as changing the states of the sets of the cache that the data is stored in) or rolling back the operation using the checkpoint in the VCC that would maintain the states of the cache before the speculative operation). So further teaches the use of control registers (Paragraphs [0042]-[0043] and [0051]-[0053], as stated in the rejection to claim 3) The combination of and reason for combining are the same as those given in claim 1.
Regarding claims 9, 10, and 12, claims 9, 10, and 12 are the system claims associated with claims 1 and 2. Since Favor, Jacobi, and So teach all the limitations to claims 1 and 2 and Favor further teaches a connection to a speculation-status signal line from the processor identifying a status of a speculative execution of instructions by the processor (Col. 18, lines 10-58, describe the versioning cache circuit (VCC) which is used to roll back the L1 cache. The process involves keeping track of the status of speculative/out-of-order commands to see if they are committed or aborted. Fig. 20 and Col. 64, line 57-Col. 65 line 10 show the use of a status line into the VCC), they also teach all the limitations to claims 9, 10, and 12; therefore the rejection to claims 1 and 2 also apply to claims 9, 10, and 12.
Regarding claims 16 and 17, claims 16 and 17 are the system claims associated with claims 1 and 2. Since Favor, Jacobi, and So teach all the limitations to claims 1 and 2, they also teach all the limitations to claims 16 and 17; therefore the rejection to claims 1 and 2 also apply to claims 16 and 17.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Favor, Jacobi, and So as applied to claim 10 above, and further in view of McCarthy (US PGPub 2017/0091096).
Regarding claim 14, Favor, Jacobi, and So teach all the limitations to claim 10. Favor, Jacobi, and So do not teach wherein the state of the control register controls the state of the first cache set or the second cache set by changing a valid bit for each block of a respective cache set.
McCarthy teaches wherein the state of the control register controls the state of the first cache set or the second cache set by changing a valid bit for each block of a respective cache set (Paragraph [0017], states that control registers can be used for various things such as partitioning the cache as well as clearing either the entire cache or a particular entry. The clearing of the cache would require invalidation and eviction of all entries (also called flushing). Paragraph [0022] also shows upon a cache invalidation that the temporal information bits for each set can be initialized to a predetermined valid state). Since both Favor/Jacobi/So and McCarthy teach the use of control registers it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the prior art elements according to known methods by modifying the teachings of Favor, Jacobi, and So to also use control registers to clear the cache as taught in McCarthy to obtain the predictable result of wherein the state of the control register can control the state of a cache set of the plurality of cache sets by changing a valid bit for each block of the cache set.
Response to Arguments
Applicant's arguments filed 6/24/2026 have been fully considered but they are not persuasive. The applicant argues that the references do not teach the amended limitations of the independent claims. The examiner respectfully disagrees. First, all the references are stated as being able to use set-associative caches and Jacobi explicitly shows (Fig. 2) and describes a 2-way set-associative cache with the two interchangeable physical outputs. So explicitly teaches the mapping circuit and conversion of physical outputs to logical ones by mapping them appropriately. In combination the references do teach the limitations of the independent claims.
Regarding the argument against Favor, Favor is relied upon to teach the speculative vs. non-speculative execution and caches. So is relied upon to teach the mapping limitations. And in combination the references do teach the cited limitations.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS A PAPERNO whose telephone number is (571)272-8337. The examiner can normally be reached Mon-Fri 9:30-5 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at 571-272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NICHOLAS A. PAPERNO/Examiner, Art Unit 2132
Prosecution Insights