DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 10th, 2026 has been entered.
Response to Amendment
Applicant’s Remarks/Arguments filed on April 10th, 2026, have been carefully considered.
No claims have been amended, added or canceled.
Claims 1-20 are currently pending in the instant application.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 12-15, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hahn et al. [US2019/0138220] hereinafter Hahn2. Hahn2 teaches adaptive device quality of service by a host memory buffer range.
Regarding claims 1, 12, and 20, Hahn2 teaches an apparatus [Hahn2 abstract “…host memory buffer (HMB) for use by a storage device…”], comprising:
a memory system comprising a volatile memory device [Hahn2 figure 2A, feature 116 “RAM”] and a non-volatile memory device [Hahn2 figure 2A, feature 104 “non-volatile memory”]; and
a kernel associated with the memory system [Hahn2 figure 2A, feature 214 “Host Processor”], wherein the kernel is configured to cause the apparatus to:
receive [Hahn2 paragraph 0046, first lines “…the controller 102 will first fetch the command from the queue…”], from an application [Hahn2 paragraph 0051, middle lines “…transactions for common applications…”], a first command indicating a first file to be accessed by an access operation [Hahn2 paragraph 0046, middle lines “…The controller 102 will then decode and parse the command (at 604). If the command includes a physical region page (PRP) list, then the controller 102 will fetch the PRP list from the queue/PRP region 230 in host RAM 216…”(Where the examiner has determined the decoded command to include the first command as seen in figure 5, feature 508.)]; and
identify one or more logical block addresses associated with the first file based at least in part on receiving the first command [Hahn2 paragraph 0046, last lines “…If no PRP list is included, then the controller 102 determines the location of the current logical-to-physical mapping information for logical addresses provided in the READ command (at 608). If the mapping information is already in NVM system RAM 116 it is retrieved from there (at 612), if it needs to be retrieved from non-volatile memory 104 it is retrieved from there (at 614), and if the NVM system 100 used the HMB 218 on the host 212 to store the mapping, then a PCIe access is used to retrieve the mapping information from the HMB 218 (at 616)…”];
the memory system configured to cause the apparatus to:
transfer, by the memory system, a portion of a logical-to-physical mapping associated with the first file from a non-volatile memory device to a volatile memory device based at least in part on the one or more logical block addresses associated with the first file and the first command [Hahn2 paragraph 0047, most lines “…Depending on the amount of mapping table information maintained in the FTL mappings region 222 in the HMB 218 and the need to swap in a different portion of the mapping table information into the HMB 218, for example if the NVM system 100 uses the HMB 218 for mapping information storage and the mapping being searched for is not currently in the HMB 218, the mapping information may need to be swapped into the HMB 218 (at 618). When this swapping in of mapping information is needed, the controller 102 will need to make a PCIe access to update the mapping information (e.g. the FTL mappings region 222 of the HMB 218) (at 622)…”];
the kernel configured to cause the apparatus to:
receive a second command to perform the access operation and access the first file after transferring the portion from the non-volatile memory device to the volatile memory device [Hahn2 paragraph 0044, middle lines “…a PRP look up, a HMB access, a NAND memory access and a completion step…” and paragraph 0047, last lines “…Once the mapping information for the READ command has been obtained, the controller 102 will retrieve (fetch) from the non-volatile memory 104 the data at the retrieved physical address associated with the READ command (at 620)…”(The examiner has determined the NAND memory access to read on the second command.)]; and
the memory system configured to cause the apparatus to:
perform, by the memory system, the access operation to retrieve information associated with the first file from the non-volatile memory device based at least in part on receiving the second command, such that the second command to perform the access operation is received subsequent to the transfer [Hahn2 paragraph 0044, middle lines “…a PRP look up, a HMB access, a NAND memory access and a completion step…” and paragraph 0047, last lines “…Once the mapping information for the READ command has been obtained, the controller 102 will retrieve (fetch) from the non-volatile memory 104 the data at the retrieved physical address associated with the READ command (at 620)…”(The examiner has determined the NAND memory access to read on the second command. And as can be seen from paragraph 0047, the transfer happens before the access operation.)].
Regarding claim 2, as per claim 1, Hahn2 teaches the first command indicates a file name, an offset, a length, or a combination thereof, associated with the first file [Hahn2 paragraph 0043, middle lines “…Alongside each read or write command is listed a start address (in physical host memory) and a data length, indicating a start and stop address, that is provided with the command. From the NVM system perspective, knowledge of the particular application (browser or email, for example) that relates to the transaction…”(The examiner is interoperating the “or” to mean that not all are required.)].
Regarding claims 3 and 13, as per claim 1, Hahn2 teaches the kernel is further configured to cause the apparatus to:
retrieve the one or more logical block addresses associated with the first file based on the file name, offset, length, or combination thereof, associated with the first file, wherein identifying the one or more logical block addresses associated with the first file is based at least in part on the retrieving [Hahn2 paragraph 0047, last lines “…Once the mapping information for the READ command has been obtained, the controller 102 will retrieve (fetch) from the non-volatile memory 104 the data at the retrieved physical address associated with the READ command (at 620)…”(.
Regarding claims 4 and 13, as per claim 1, Hahn2 teaches the kernel is further configured to cause the apparatus to:
transfer, to the memory system, a first information unit [Hahn2 paragraph 0046, middle lines “…If the command includes a physical region page (PRP) list, then the controller 102 will fetch the PRP list from the queue/PRP region 230 in host RAM 216 (at 606, 610)…”] associated with the first command based at least in part on identifying the one or more logical block addresses, wherein transferring the portion of the logical-to-physical mapping associated with the first file is based at least in part on transferring the first information unit associated with the first command [Hahn2 paragraph 0047, most lines “…Depending on the amount of mapping table information maintained in the FTL mappings region 222 in the HMB 218 and the need to swap in a different portion of the mapping table information into the HMB 218, for example if the NVM system 100 uses the HMB 218 for mapping information storage and the mapping being searched for is not currently in the HMB 218, the mapping information may need to be swapped into the HMB 218 (at 618). When this swapping in of mapping information is needed, the controller 102 will need to make a PCIe access to update the mapping information (e.g. the FTL mappings region 222 of the HMB 218) (at 622)…”].
Regarding claims 5 and 14, as per claim 1, Hahn2 teaches the first information unit comprises an operation code associated with a pre-read command, an indication of the one or more logical block addresses associated with the first file, and a length value associated with the first command [Hahn2 paragraph 0046, last lines “…If the mapping information is already in NVM system RAM 116 it is retrieved from there (at 612), if it needs to be retrieved from non-volatile memory 104 it is retrieved from there (at 614), and if the NVM system 100 used the HMB 218 on the host 212 to store the mapping, then a PCIe access is used to retrieve the mapping information from the HMB 218 (at 616)…” and figure 5, feature “Length”].
Regarding claims 6, and 15, as per claim 1, Hahn2 teaches the first information unit comprises an operation code associated with a pre-read command [Hahn2 paragraph 0046, middle lines “…If the command includes a physical region page (PRP) list, then the controller 102 will fetch the PRP list from the queue/PRP region 230 in host RAM 216 (at 606, 610)…”] and a first value associated with a length of a list [Hahn2 figure 5, feature “Length”], and the kernel is further configured to cause the apparatus to:
transfer, to the memory system, a second information unit associated with the first command, the second information unit comprising a portion of the list that indicates the one or more logical block addresses associated with the first file [Hahn2 paragraph 0047, most lines “…Depending on the amount of mapping table information maintained in the FTL mappings region 222 in the HMB 218 and the need to swap in a different portion of the mapping table information into the HMB 218, for example if the NVM system 100 uses the HMB 218 for mapping information storage and the mapping being searched for is not currently in the HMB 218, the mapping information may need to be swapped into the HMB 218 (at 618). When this swapping in of mapping information is needed, the controller 102 will need to make a PCIe access to update the mapping information (e.g. the FTL mappings region 222 of the HMB 218) (at 622)…”].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 8-11 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Hahn et al. [US2019/0138220] hereinafter Hahn2, in view of Hahn [US2016/0246726]. Hahn2 teaches adaptive device quality of service by a host memory buffer range. Hahn teaches adaptive host memory buffer (HMB) caching using unassisted hinting.
Regarding claim 8, as per claim 1, Hahn2 fails to explicitly teach the kernel is further configured to cause the apparatus to: receive, from the application, a third command indicating a second file that is ceasing to be accessed by the application during a time period; and identify one or more logical block addresses associated with the second file based at least in part on receiving the third command.
However, Hahn does teach receive, from the application, a third command indicating a second file that is ceasing to be accessed by the application during a time period; and identify one or more logical block addresses associated with the second file based at least in part on receiving the third command [Hahn paragraph 0028, middle lines “…is determined whether the address translation requires eviction of a page from one of the FTL caches to allow caching of the FTL data needed for the current I/O command. Determining whether eviction of a page is necessary includes determining whether the hint derived from the command requires the addition of FTL data to one or more of the caches…”(The examiner has determined the eviction to read on the third command since it indicates a file that is ceasing to be accessed.)].
Hahn2 and Hahn are analogous arts in that they both deal with using memory mapping in host memory buffers.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Hahn2’s swapping of portions of addresses from HMB to RAM with Hahn’s teachings that portions of addresses come from the memory system and go to the HMB and vice versa for the benefit of reducing latency by storing address translation information on faster HMB cache [Hahn paragraph 0015, last lines “…The adaptive HMB caching module utilizes the hints to determine how to cache FTL data in the HMB and on the storage device to reduce latency in future accesses…”].
Regarding claims 9 and 17, as per claim 1, Hahn teaches the memory system is further configured to cause the apparatus to:
transfer, by the memory system, a portion of a logical-to-physical mapping associated with the second file from the volatile memory device to the non-volatile memory device based at least in part on the one or more logical block addresses associated with the second file and the third command [Hahn paragraph 0027, most lines “…A hint table 302 stores LBA ranges and corresponding hints that indicate how the corresponding LBA range will likely be accessed by the host system in the future. In one example, the hints may be file types, which provide an indication of how the files and their associated FTL table entries will subsequently be accessed by the host system. Access frequency map 304 stores LBA ranges and frequencies of access for the ranges. Access frequency map 304 may be in the form of statistics, counters, logs, or any other direct or derived mechanism for recording access frequencies for different LBAs…” and paragraph 0031, first lines “…Continuing operation of the storage device may include gradually replacing the data in the primary and secondary FTL caches with FTL data expected to be accessed next using the hints derived from subsequent memory accesses…”].
Regarding claims 10 and 18, as per claim 1, Hahn teaches the kernel is further configured to cause the apparatus to:
transfer, to the memory system, a first information unit associated with the third command, wherein transferring the portion of the logical-to-physical mapping associated with the second file is based at least in part on transferring the first information unit associated with the third command [Hahn paragraph 0031, first lines “…Continuing operation of the storage device may include gradually replacing the data in the primary and secondary FTL caches with FTL data expected to be accessed next using the hints derived from subsequent memory accesses…”].
Regarding claim 11, as per claim 1, Hahn2 fails to teach the kernel is further configured to cause the apparatus to: store an indication of the one or more logical block addresses associated with the first file [Hahn paragraph 0027, first lines “…A hint table 302 stores LBA ranges and corresponding hints that indicate how the corresponding LBA range will likely be accessed by the host system in the future…”];
However Hahn does teach the kernel [Hahn paragraph 0051, middle line “…In a Windows-based operating system…”] is further configured to cause the apparatus to: store an indication of the one or more logical block addresses associated with the first file [Hahn paragraph 0027, first lines “…A hint table 302 stores LBA ranges and corresponding hints that indicate how the corresponding LBA range will likely be accessed by the host system in the future…”];
Hahn2 and Hahn are analogous arts in that they both deal with using memory mapping in host memory buffers.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Hahn2’s swapping of portions of addresses from HMB to RAM with Hahn’s teachings that portions of addresses come from the memory system and go to the HMB and vice versa for the benefit of reducing latency by storing address translation information on faster HMB cache [Hahn paragraph 0015, last lines “…The adaptive HMB caching module utilizes the hints to determine how to cache FTL data in the HMB and on the storage device to reduce latency in future accesses…”].
retrieve the indication of the one or more logical block addresses associated with the first file, wherein, to perform the access operation [Hahn paragraph 0028, middle lines “…The hint may be derived by hint derivation module 301 using data stored in hint table 302 and/or access frequency map 304. Detailed examples of hint derivation will be described below. In step 404, an address translation is performed for the I/O command. For example, address translation module 207 may translate the logical addresses in the memory access to physical addresses using FTL data…”], the memory system is further configured to cause the apparatus to:
retrieve the information associated with the first file from the non-volatile memory device based at least in part on retrieving the indication of the one or more logical block addresses associated with the first file [Hahn paragraph 0039, last lines “…Continuing the processing may include completing the I/O command and updating the access frequency for the LBA range…”].
Regarding claim 19, as per claim 12, Hahn teaches the first information unit comprises an operation code associated with a pre-read command and a first value associated with a length of a list that indicates one or more logical block addresses associated with the second file [Hahn paragraph 0034, last lines “…it is determined whether or not a hint already exists for the LBA range in the I/O command. In order to determine whether a hint exists for the range specified in the I/O command, hint derivation module 301 may extract the LBA range from the I/O command sequence and perform a lookup in hint table 302 to determine whether an entry for the LBA range is present in hint table 302. Table 1 shown below illustrates exemplary entries that may be present in hint table 302…”], and the one or more controllers [Hahn paragraph 0021, middle lines “…a storage controller that controls access by host device 201 to nonvolatile memory…”] are further configured to cause the apparatus to:
receive a second information unit comprising the list that indicates the one or more logical block addresses associated with the second file [Hahn paragraph 0031, first lines “…Continuing operation of the storage device may include gradually replacing the data in the primary and secondary FTL caches with FTL data expected to be accessed next using the hints derived from subsequent memory accesses…”].
Allowable Subject Matter
Claims 7 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claims 1, 12, and 20 have been considered but are moot in view of new grounds of rejection.
Applicant argues that two different commands aren’t used in Hahn. The examiner has thus applied Hahn2 to show that two different commands are used in the read or write transactions as can be seen from figure 5.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC CARDWELL whose telephone number is (571)270-1379. The examiner can normally be reached on Monday - Friday 10-6pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached on (571) 272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC CARDWELL/Primary Examiner, Art Unit 2139
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