CTNF 18/626,260 CTNF 87591 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made 07-21-aia AIA Claim s 1-3, 5-6, 8-10, 12, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Schluessler et al. (US 2023/0076468, hereinafter Schluessler) in view of Thiruchengode Vajravel et al. (US 11,288,216, hereinafter Thiruchengode Vajravel) . Regarding claim 1, Schluessler discloses A computer-implemented method comprising (fig. 1-4): queueing, by an integrated circuit, a message in a message queue (paragraph [0048]: The FBLCU alternatively can determine a type of GPU draw in the request and determine the quantity of data for the transfer is equal to a quantity of data used by the GPU when the GPU previously rendered a frame for the same type of GPU draw ; paragraph [0049]: the FBLCU identifies, within a queue , a first group of operations that transfer known quantities of data, as well as a second group of operations that transfer unknown quantities of data. That is, the first group of operations transfer a determinate quantity of data) … ; transitioning, by the integrated circuit, a data transfer link to an active state based on a presence of the message in the message queue and the latency tolerance level (paragraph [0049]: the FBLCU identifies, within a queue , a first group of operations that transfer known quantities of data, as well as a second group of operations that transfer unknown quantities of data. That is, the first group of operations transfer a determinate quantity of data … The FBLCU then determines the active lane count based on the sum ; paragraph [0050]: the FBLCU optionally determines (e.g., calculates) a period of time for the transfer , at least in part based on the request. In particular, the FBLCU determines the period, based on the quantity of data for the transfer or the use of the request ; paragraph [0064]: the FBLCU can calculate the bus lane wake or sleep initiation time, based on the current latency on the communication bus 160 and the bandwidth requirement for the transfer ) for the message (paragraph [0048]: The FBLCU alternatively can determine a type of GPU draw in the request and determine the quantity of data for the transfer is equal to a quantity of data used by the GPU when the GPU previously rendered a frame for the same type of GPU draw ; paragraph [0049]: the FBLCU identifies, within a queue , a first group of operations that transfer known quantities of data, as well as a second group of operations that transfer unknown quantities of data. That is, the first group of operations transfer a determinate quantity of data) ; and transferring, by the integrated circuit, the message over the data transfer link while the data transfer link is in the active state (paragraph [0066]: after the wake cycle time (or sleep cycle time) has elapsed, the host 110 or peripheral device 170 can perform the transfer using one or more lanes of the communication bus 160 in the direction of the request. For example, lanes that were awoken at the initiation time in S275 can perform the transfer ) . Schluessler does not disclose queueing, by an integrated circuit, a message in a message queue based on a latency tolerance level for the message . Thiruchengode Vajravel discloses queueing, by an integrated circuit, a message in a message queue based on a latency tolerance level for the message (fig. 1-3, col. 7, lines 18-32: Information handling system 202 can identify latency-sensitive traffic data that is marked for the first communication channel 230 and re-classify the latency-sensitive traffic data for placing in a queue associated with the second communication channel 232 (e.g., moving the latency-sensitive traffic data to a higher-priority queue ). That is, the information handling system 202 can adjust (increase) the priority of the latency-sensitive traffic data such that the latency-sensitive traffic data is placed in a higher-priority queue that is associated with the second communication channel 232 that is an isochronous communication channel ( as compared to a lower-priority queue that is associated with the first communication channel 230 that is a non-isochronous communication channel). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Schluessler’s bus lane power management system to incorporate Thiruchengode Vajravel’s latency-based queueing and classification, in order to ensure that highly latency-sensitive traffic (such as urgent GPU rendering commands) is properly prioritized in the queueing stage, thereby allowing the power management unit to accurately calculate wake initiation times and guarantee that the bus lanes are active exactly when time-critical data needs to be transferred, ultimately improving system responsiveness while maintaining power efficiency. Regarding claim 8 referring to claim 1 , Schluessler discloses A system comprising: at least one physical processor; and physical memory comprising computer-executable instructions that, when executed by the at least one physical processor, cause the at least one physical processor to: … (Fig. 4). Regarding claims 2 and 9, Schluessler does not disclose wherein queueing the message includes determining the latency tolerance level for the message by: determining a message type of the message; and identifying a predefined latency tolerance level associated with the message type . Thiruchengode Vajravel discloses wherein queueing the message includes determining the latency tolerance level for the message by: determining a message type of the message; and identifying a predefined latency tolerance level associated with the message type (col. 7, lines 18-32: Information handling system 202 can identify latency-sensitive traffic data that is marked for the first communication channel 230 and re-classify the latency-sensitive traffic data for placing in a queue associated with the second communication channel 232 (e.g., moving the latency-sensitive traffic data to a higher-priority queue ). That is, the information handling system 202 can adjust (increase) the priority of the latency-sensitive traffic data such that the latency-sensitive traffic data is placed in a higher-priority queue that is associated with the second communication channel 232 that is an isochronous communication channel ( as compared to a lower-priority queue that is associated with the first communication channel 230 that is a non-isochronous communication channel). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Schluessler’s bus lane power management system to incorporate Thiruchengode Vajravel’s latency-based queueing and classification, in order to ensure that highly latency-sensitive traffic (such as urgent GPU rendering commands) is properly prioritized in the queueing stage, thereby allowing the power management unit to accurately calculate wake initiation times and guarantee that the bus lanes are active exactly when time-critical data needs to be transferred, ultimately improving system responsiveness while maintaining power efficiency. Regarding claims 3 and 10, Schluessler does not disclose wherein queueing the message includes: queueing a first message having a first latency tolerance level in a first message queue dedicated to messages having the first latency tolerance level; and queueing a second message having a second latency tolerance level in a second message queue that is dedicated to messages having the second latency tolerance level . Thiruchengode Vajravel discloses wherein queueing the message includes: queueing a first message having a first latency tolerance level in a first message queue dedicated to messages having the first latency tolerance level; and queueing a second message having a second latency tolerance level in a second message queue that is dedicated to messages having the second latency tolerance level (col. 7, lines 18-32: Information handling system 202 can identify latency-sensitive traffic data that is marked for the first communication channel 230 and re-classify the latency-sensitive traffic data for placing in a queue associated with the second communication channel 232 (e.g., moving the latency-sensitive traffic data to a higher-priority queue ). That is, the information handling system 202 can adjust (increase) the priority of the latency-sensitive traffic data such that the latency-sensitive traffic data is placed in a higher-priority queue that is associated with the second communication channel 232 that is an isochronous communication channel ( as compared to a lower-priority queue that is associated with the first communication channel 230 that is a non-isochronous communication channel). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Schluessler’s bus lane power management system to incorporate Thiruchengode Vajravel’s latency-based queueing and classification, in order to ensure that highly latency-sensitive traffic (such as urgent GPU rendering commands) is properly prioritized in the queueing stage, thereby allowing the power management unit to accurately calculate wake initiation times and guarantee that the bus lanes are active exactly when time-critical data needs to be transferred, ultimately improving system responsiveness while maintaining power efficiency. Regarding claims 5 and 12, Schluessler discloses wherein transferring the message over the data transfer link includes: transferring a plurality of messages … over the data transfer link (paragraph [0045]: The FBLCU also determines (e.g., calculates) in S225 a quantity of data for the transfer at least in part based on the request. In some instances, the request identifies a determinate quantity of data for a memory transfer ; paragraph [0048]: The FBLCU alternatively can determine a type of GPU draw in the request and determine the quantity of data for the transfer is equal to a quantity of data used by the GPU when the GPU previously rendered a frame for the same type of GPU draw ; paragraph [0049]: the FBLCU identifies, within a queue , a first group of operations that transfer known quantities of data, as well as a second group of operations that transfer unknown quantities of data. That is, the first group of operations transfer a determinate quantity of data; paragraph [0066]: after the wake cycle time (or sleep cycle time) has elapsed, the host 110 or peripheral device 170 can perform the transfer using one or more lanes of the communication bus 160 in the direction of the request. For example, lanes that were awoken at the initiation time in S275 can perform the transfer ) . Schluessler does not disclose a plurality of messages having different latency tolerance levels . Thiruchengode Vajravel discloses a plurality of messages having different latency tolerance levels (col. 7, lines 18-32: Information handling system 202 can identify latency-sensitive traffic data that is marked for the first communication channel 230 and re-classify the latency-sensitive traffic data for placing in a queue associated with the second communication channel 232 (e.g., moving the latency-sensitive traffic data to a higher-priority queue ). That is, the information handling system 202 can adjust (increase) the priority of the latency-sensitive traffic data such that the latency-sensitive traffic data is placed in a higher-priority queue that is associated with the second communication channel 232 that is an isochronous communication channel ( as compared to a lower-priority queue that is associated with the first communication channel 230 that is a non-isochronous communication channel). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Schluessler’s bus lane power management system to incorporate Thiruchengode Vajravel’s latency-based queueing and classification, in order to ensure that highly latency-sensitive traffic (such as urgent GPU rendering commands) is properly prioritized in the queueing stage, thereby allowing the power management unit to accurately calculate wake initiation times and guarantee that the bus lanes are active exactly when time-critical data needs to be transferred, ultimately improving system responsiveness while maintaining power efficiency. Regarding claims 6 and 13, Schluessler discloses wherein the message is generated by a first system on a chip (SoC) and is transferred to a second SoC (paragraph [0020]: The device driver 130 is a driver for the one or more CPUs 110 to interact with the peripheral device 170; paragraph [0066]: after the wake cycle time (or sleep cycle time) has elapsed, the host 110 or peripheral device 170 can perform the transfer using one or more lanes of the communication bus 160 in the direction of the request. For example, lanes that were awoken at the initiation time in S275 can perform the transfer ; paragraph [0120]: Implementations of the present disclosure can be readily included in a system-on-chip (SOC) package ) . 07-21-aia AIA Claim s 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Schluessler et al. (US 2023/0076468, hereinafter Schluessler) in view of Thiruchengode Vajravel et al. (US 11,288,216, hereinafter Thiruchengode Vajravel) as applied to claims 1 and 8, and further in view of Natarajan (US 2021/0208668, hereinafter Natarajan) . Regarding claims 7 and 14, Schluessler in view of Thiruchengode Vajravel does not disclose further comprising: utilizing a virtual wire comprising a physical wire to virtual wire message interface to perform two-way transfer of messages between a first system on a chip (SoC) and a second SoC . Natarajan discloses further comprising: utilizing a virtual wire comprising a physical wire to virtual wire message interface to perform two-way transfer of messages between a first system on a chip (SoC) and a second SoC (paragraph [0060]: For Type-C Host, initiated wake only requirement inference which has no stringent latency tolerance requirements, Host Port Power Save Scheme preempts power cutoff via I2C interface to PD controller. In some embodiments, SoC GPIO pins and SLP_S0, Sx pins, eSPI virtual wires signaling can be also utilized to trigger PD controller to shutoff power to BPD or HUB devices while the SoC system can also shut its wake power planes. On a wake notification from SOC SLP_S0, SX pins, eSPI virtual wires to the PD can be triggered to again power the BPD or HUB devices.). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined system of Schluessler and Thiruchengode Vajravel to incorporate the eSPI virtual wire signaling of Natarajan, in order to reduce physical pin counts on the integrated circuits by replacing dedicated physical signaling lines with in-band virtual wire messages, thereby saving board space and reducing manufacturing costs while reliably transmitting power and wake state messages between the chips . 07-21-aia AIA Claim s 15, 17, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Schluessler et al. (US 2023/0076468, hereinafter Schluessler) in view of Dalmia (US 2020/0083974, hereinafter Dalmia) . Regarding claim 15, Schluessler discloses A method comprising: identifying, by an integrated circuit … , a latency tolerance level (paragraph [0014]: The present disclosure identifies specific resources to be transferred, their size, and latency sensitivity (e.g., whether the resource should be provided immediately (latency sensitive, or it can be transferred slowly using fewer lanes ; paragraph [0015] Particular implementations of this disclosure use the aforementioned details to determine a lane configuration based on an upcoming operation including the amount of data to be transferred and the latency /bandwidth sensitivity of the computing system to that transfer ) ; and duty cycling, by the integrated circuit, … (paragraph [0049]: the FBLCU identifies, within a queue , a first group of operations that transfer known quantities of data, as well as a second group of operations that transfer unknown quantities of data. That is, the first group of operations transfer a determinate quantity of data … The FBLCU then determines the active lane count based on the sum ; paragraph [0050]: the FBLCU optionally determines (e.g., calculates) a period of time for the transfer , at least in part based on the request. In particular, the FBLCU determines the period, based on the quantity of data for the transfer or the use of the request ; paragraph [0064]: the FBLCU can calculate the bus lane wake or sleep initiation time, based on the current latency on the communication bus 160 and the bandwidth requirement for the transfer ) with a frequency that satisfies the latency tolerance level (paragraph [0014]: The present disclosure identifies specific resources to be transferred, their size, and latency sensitivity (e.g., whether the resource should be provided immediately (latency sensitive, or it can be transferred slowly using fewer lanes ; paragraph [0015] Particular implementations of this disclosure use the aforementioned details to determine a lane configuration based on an upcoming operation including the amount of data to be transferred and the latency /bandwidth sensitivity of the computing system to that transfer ) . Schluessler does not disclose identifying, by an integrated circuit and at an application layer of a communication protocol, a latency tolerance level … duty cycling, by the integrated circuit, a link layer of the communication protocol . Dalmia discloses identifying, by an integrated circuit and at an application layer of a communication protocol, a latency tolerance level (paragraph [0009]: Even in the sleep mode, however, the transmitter of a PHY device generally sends periodic refresh signals (as shown in FIG. 1), for example, to ensure that the link is functioning and that the higher level systems, such as the network management system (NMS) are aware of the availability of the link, and known that the link can be re-awakened , as needed, at any time. This is especially important in the case of unpredictable/ latency sensitive traffic ; paragraph [0040]: With reference to FIG. 3, in an Ethernet-based communication system 300 according to one embodiment, when a source device or application (e.g., a video source , smart phone, tablet, etc.) intends to send data to a sink device or application (e.g., a video display, speaker, web browser, etc.), the topmost layer in the communication system (referred to as the Application layer in the Open Systems Interconnection (OSI) model) generates the data to be transmitted … the application layers of the source and sink devices/applications are referred to as data source and data sink , respectively.) … duty cycling, by the integrated circuit, a link layer of the communication protocol (paragraph [0041]: The PHY 302 exchanges data and control signals with the layer directly above, e.g., the data link layer , which includes the Media Access Control (MAC) 304 and Logical Link Control (LLC) sublayers; paragraph [0056]: The link partner devices may also adjust the duty cycle of the transmission and silent modes , e.g., the durations Ta and Tq on the fly, e.g., between two sessions . Such adjustment of duty cycle can be 50% allowing for a symmetrical bandwidth in both directions). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Schluessler’s bus lane power management system to incorporate Dalmia’s protocol-layered architecture, specifically generating latency-sensitive traffic parameters from the application layer and adjusting the duty cycle via the data link layer. A person of ordinary skill in the art would have been motivated to do so in order to provide a standardized, protocol-compliant framework (such as the OSI model) for power management, ensuring that high-level application latency requirements systematically dictate the hardware link’s active/silent duty cycle, thereby optimizing system power consumption without violating the application’s critical timing constraints. Schluessler does not disclose identifying, by an integrated circuit and at an application layer of a communication protocol, a latency tolerance level … duty cycling, by the integrated circuit, a link layer of the communication protocol . Dalmia discloses identifying, by an integrated circuit and at an application layer of a communication protocol, a latency tolerance level (paragraph [0009]: Even in the sleep mode, however, the transmitter of a PHY device generally sends periodic refresh signals (as shown in FIG. 1), for example, to ensure that the link is functioning and that the higher level systems, such as the network management system (NMS) are aware of the availability of the link, and known that the link can be re-awakened , as needed, at any time. This is especially important in the case of unpredictable/ latency sensitive traffic ; paragraph [0040]: With reference to FIG. 3, in an Ethernet-based communication system 300 according to one embodiment, when a source device or application (e.g., a video source , smart phone, tablet, etc.) intends to send data to a sink device or application (e.g., a video display, speaker, web browser, etc.), the topmost layer in the communication system (referred to as the Application layer in the Open Systems Interconnection (OSI) model) generates the data to be transmitted … the application layers of the source and sink devices/applications are referred to as data source and data sink , respectively.) … duty cycling, by the integrated circuit, a link layer of the communication protocol (paragraph [0041]: The PHY 302 exchanges data and control signals with the layer directly above, e.g., the data link layer , which includes the Media Access Control (MAC) 304 and Logical Link Control (LLC) sublayers; paragraph [0056]: The link partner devices may also adjust the duty cycle of the transmission and silent modes , e.g., the durations Ta and Tq on the fly, e.g., between two sessions . Such adjustment of duty cycle can be 50% allowing for a symmetrical bandwidth in both directions). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Schluessler’s bus lane power management system to incorporate Dalmia’s protocol-layered architecture, specifically generating latency-sensitive traffic parameters from the application layer and adjusting the duty cycle via the data link layer. A person of ordinary skill in the art would have been motivated to do so in order to provide a standardized, protocol-compliant framework (such as the OSI model) for power management, ensuring that high-level application latency requirements systematically dictate the hardware link’s active/silent duty cycle, thereby optimizing system power consumption without violating the application’s critical timing constraints. Regarding claim 17, Schluessler discloses transitioning a data transfer link to an active state based at least in part on the latency tolerance level (paragraph [0049]: the FBLCU identifies, within a queue , a first group of operations that transfer known quantities of data, as well as a second group of operations that transfer unknown quantities of data. That is, the first group of operations transfer a determinate quantity of data … The FBLCU then determines the active lane count based on the sum ; paragraph [0050]: the FBLCU optionally determines (e.g., calculates) a period of time for the transfer , at least in part based on the request. In particular, the FBLCU determines the period, based on the quantity of data for the transfer or the use of the request ; paragraph [0064]: the FBLCU can calculate the bus lane wake or sleep initiation time, based on the current latency on the communication bus 160 and the bandwidth requirement for the transfer ) . Schluessler does not disclose wherein duty cycling the link layer includes … . Dalmia discloses wherein duty cycling the link layer includes … (paragraph [0041]: The PHY 302 exchanges data and control signals with the layer directly above, e.g., the data link layer , which includes the Media Access Control (MAC) 304 and Logical Link Control (LLC) sublayers; paragraph [0056]: The link partner devices may also adjust the duty cycle of the transmission and silent modes , e.g., the durations Ta and Tq on the fly, e.g., between two sessions . Such adjustment of duty cycle can be 50% allowing for a symmetrical bandwidth in both directions). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Schluessler’s bus lane power management system to incorporate Dalmia’s protocol-layered architecture, specifically generating latency-sensitive traffic parameters from the application layer and adjusting the duty cycle via the data link layer. A person of ordinary skill in the art would have been motivated to do so in order to provide a standardized, protocol-compliant framework (such as the OSI model) for power management, ensuring that high-level application latency requirements systematically dictate the hardware link’s active/silent duty cycle, thereby optimizing system power consumption without violating the application’s critical timing constraints. Regarding claim 18, Schluessler does not disclose transitioning a data transfer link to a low-power state following transfer of messages by the link layer (paragraph [0041]: The PHY 302 exchanges data and control signals with the layer directly above, e.g., the data link layer , which includes the Media Access Control (MAC) 304 and Logical Link Control (LLC) sublayers; paragraph [0056]: The link partner devices may also adjust the duty cycle of the transmission and silent modes , e.g., the durations Ta and Tq on the fly, e.g., between two sessions . Such adjustment of duty cycle can be 50% allowing for a symmetrical bandwidth in both directions). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Schluessler’s bus lane power management system to incorporate Dalmia’s protocol-layered architecture, specifically generating latency-sensitive traffic parameters from the application layer and adjusting the duty cycle via the data link layer. A person of ordinary skill in the art would have been motivated to do so in order to provide a standardized, protocol-compliant framework (such as the OSI model) for power management, ensuring that high-level application latency requirements systematically dictate the hardware link’s active/silent duty cycle, thereby optimizing system power consumption without violating the application’s critical timing constraints. Regarding claim 20, Schluessler discloses transfers all enqueued messages while in an active state regardless of latency tolerance levels of the enqueued messages (paragraph [0049]: the FBLCU identifies, within a queue, a first group of operations that transfer known quantities of data, as well as a second group of operations that transfer unknown quantities of data. That is, the first group of operations transfer a determinate quantity of data. On the other hand, the FBLCU uses historical averages or such to determine an approximation of the unknown quantity of data. The FBLCU adds the determinate quantity of data to the approximation of the unknown quantity of data to determine a sum. The FBLCU then determines the active lane count based on the sum; paragraph [0066]: after the wake cycle time (or sleep cycle time) has elapsed, the host 110 or peripheral device 170 can perform the transfer using one or more lanes of the communication bus 160 in the direction of the request. For example, lanes that were awoken at the initiation time in S275 can perform the transfer. Lanes that were slept in S275 are not used in the transfer. Similarly, lanes that were maintained in an awake state at S275 can be used for the transfer, and lanes that were maintained in a sleeping state at S275 are not used for the transfer. The algorithm 200 then advances to S295; paragraph [0090]: the device driver 130 can determine a queue for the communication bus 160 includes a first command list, followed by other work, then followed by a second command list. The device driver 130 then can reorder the queue so the first command list and the second command list are performed consecutively. Thus, the BLPM can keep the communication bus 160 in a higher power state for a longer consecutive period of time. Thus, overall power can be saved; Note: Schluessler teaches batching operations in a queue, summing the total quantity of data required for the operations, and performing the transfer of the batched data while the bus lanes are in the active state ). Schluessler does not disclose wherein the link layer all enqueued message (paragraph [0041]: The PHY 302 exchanges data and control signals with the layer directly above, e.g., the data link layer , which includes the Media Access Control (MAC) 304 and Logical Link Control (LLC) sublayers; paragraph [0056]: The link partner devices may also adjust the duty cycle of the transmission and silent modes , e.g., the durations Ta and Tq on the fly, e.g., between two sessions . Such adjustment of duty cycle can be 50% allowing for a symmetrical bandwidth in both directions; paragraph [0071]: The size of the rate matching FIFOs 704, 706 is based on the instantaneous bit rate the PHY can support multiplied by the largest active period value it can support, which is the most number of bits the PHY will need to buffer while the PHY is in the silent mode . In the TX direction, bits are enqueued into the Rate Match FIFO 704 at the TX constant bit rate, and during the active phase, the data bits are dequeued at the instantaneous bit rate ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Schluessler’s batching operations in a queue, summing the total quantity of data required for the operations, and performing the transfer of the batched data while the bus lanes are in the active state to incorporate Dalmia’s enqueuing data bits into a buffer during the silent phase, and dequeuing and transferring the enqueued data bits and transferred during the active phase via data link, thus, the combined teachings of Schluessler and Dalmia disclose transferring all enqueued messages (the batched operations / FIFO data) while the link is in the active state, regardless of the individual latency tolerance levels of the specific messages within that batch. A person of ordinary skill in the art would have recognized that once the link layer transitions to the active state to satisfy a latency-sensitive request, it is highly efficient to transfer all pending data in the queue (flushing the queue/FIFO) before returning to a sleep state, in order to maximize bandwidth utilization and preventing the need to wake the link again shortly thereafter for lower-priority data . 07-21-aia AIA Claim s 16 are rejected under 35 U.S.C. 103 as being unpatentable over Schluessler et al. (US 2023/0076468, hereinafter Schluessler) in view of Dalmia (US 2020/0083974, hereinafter Dalmia) as applied to claim 15, and further in view of Thiruchengode Vajravel et al. (US 11,288,216, hereinafter Thiruchengode Vajravel) . Regarding claim 16, Schluessler in view of Dalmia does not disclose wherein determining the latency tolerance level includes: determining a message type of a message; and identifying a predefined latency tolerance level associated with the message type . Thiruchengode Vajravel discloses wherein determining the latency tolerance level includes: determining a message type of a message; and identifying a predefined latency tolerance level associated with the message type (col. 7, lines 18-32: Information handling system 202 can identify latency-sensitive traffic data that is marked for the first communication channel 230 and re-classify the latency-sensitive traffic data for placing in a queue associated with the second communication channel 232 (e.g., moving the latency-sensitive traffic data to a higher-priority queue ). That is, the information handling system 202 can adjust (increase) the priority of the latency-sensitive traffic data such that the latency-sensitive traffic data is placed in a higher-priority queue that is associated with the second communication channel 232 that is an isochronous communication channel ( as compared to a lower-priority queue that is associated with the first communication channel 230 that is a non-isochronous communication channel). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Schluessler Dalmia’s bus lane power management system to incorporate Thiruchengode Vajravel’s latency-based queueing and classification, in order to ensure that highly latency-sensitive traffic (such as urgent GPU rendering commands) is properly prioritized in the queueing stage, thereby allowing the power management unit to accurately calculate wake initiation times and guarantee that the bus lanes are active exactly when time-critical data needs to be transferred, ultimately improving system responsiveness while maintaining power efficiency . 07-21-aia AIA Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Schluessler et al. (US 2023/0076468, hereinafter Schluessler) in view of Dalmia (US 2020/0083974, hereinafter Dalmia) as applied to claim 15, and further in view of Natarajan (US 2021/0208668, hereinafter Natarajan) . Regarding claim 19, Schluessler does not disclose wherein the link layer … (paragraph [0041]: The PHY 302 exchanges data and control signals with the layer directly above, e.g., the data link layer , which includes the Media Access Control (MAC) 304 and Logical Link Control (LLC) sublayers; paragraph [0056]: The link partner devices may also adjust the duty cycle of the transmission and silent modes , e.g., the durations Ta and Tq on the fly, e.g., between two sessions . Such adjustment of duty cycle can be 50% allowing for a symmetrical bandwidth in both directions). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Schluessler’s bus lane power management system to incorporate Dalmia’s protocol-layered architecture, specifically generating latency-sensitive traffic parameters from the application layer and adjusting the duty cycle via the data link layer. A person of ordinary skill in the art would have been motivated to do so in order to provide a standardized, protocol-compliant framework (such as the OSI model) for power management, ensuring that high-level application latency requirements systematically dictate the hardware link’s active/silent duty cycle, thereby optimizing system power consumption without violating the application’s critical timing constraints. Schluessler in view of Dalmia does not disclose utilizes a virtual wire comprising a physical wire to virtual wire message interface to perform two-way transfer of messages between a first system on a chip (SoC) and a second SoC . Natarajan discloses utilizes a virtual wire comprising a physical wire to virtual wire message interface to perform two-way transfer of messages between a first system on a chip (SoC) and a second SoC (paragraph [0060]: For Type-C Host, initiated wake only requirement inference which has no stringent latency tolerance requirements, Host Port Power Save Scheme preempts power cutoff via I2C interface to PD controller. In some embodiments, SoC GPIO pins and SLP_S0, Sx pins, eSPI virtual wires signaling can be also utilized to trigger PD controller to shutoff power to BPD or HUB devices while the SoC system can also shut its wake power planes. On a wake notification from SOC SLP_S0, SX pins, eSPI virtual wires to the PD can be triggered to again power the BPD or HUB devices.). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined system of Schluessler and Dalmia to incorporate the eSPI virtual wire signaling of Natarajan, in order to reduce physical pin counts on the integrated circuits by replacing dedicated physical signaling lines with in-band virtual wire messages, thereby saving board space and reducing manufacturing costs while reliably transmitting power and wake state messages between the chips . Conclusion 12-151-08 AIA 07-43 12-51-08 Claim s 4 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. Lee et al. (US 2025/0272233) discloses “The priority queue may add elements (e.g., commands) with an associated priority” (paragraph [0058]) and “the host 1100 may change or adjust the priority such that the execution results of the latency sensitive command written to the completion queue CQ may comply with the latency limitation” (paragraph [0060]). Kim et al. (US 2023/0146174) discloses “The application layer AL, the presentation layer PL, the session layer SL, the transport layer TL, the network layer NL, the data link layer DL, and the physical layer PHY of the first SoC 4100 may communicate with the application layer AL, the presentation layer PL, the session layer SL, the transport layer TL, the network layer NL, the data link layer DL, and the physical layer PHY of the second SoC 4200, respectively” (paragraph [0115]). Jeon (US 2022/0327073) discloses “When the amount of the commands stored in the command queue is less than or equal to the reference value, the power controller 131 may set the operation mode to the second power mode. The power controller 131 may set the operation mode to the third power mode when the command queue is empty during a first time period that is equal to or more than a first reference time and a latency allowed by the host 2000 is less than or equal to a reference latency” (paragraph [0095]). Any inquiry concerning this communication or earlier communications from the examiner should be directed to SISLEY N. KIM whose telephone number is (571)270-7832. The examiner can normally be reached M-F 11:30AM -7:30PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice . If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, April Y. Blair can be reached on (571)270-1014. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov . Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SISLEY N KIM/Primary Examiner, Art Unit 2196 6/11/2026 Application/Control Number: 18/626,260 Page 2 Art Unit: 2196 Application/Control Number: 18/626,260 Page 3 Art Unit: 2196 Application/Control Number: 18/626,260 Page 4 Art Unit: 2196 Application/Control Number: 18/626,260 Page 5 Art Unit: 2196 Application/Control Number: 18/626,260 Page 6 Art Unit: 2196 Application/Control Number: 18/626,260 Page 7 Art Unit: 2196 Application/Control Number: 18/626,260 Page 8 Art Unit: 2196 Application/Control Number: 18/626,260 Page 9 Art Unit: 2196 Application/Control Number: 18/626,260 Page 10 Art Unit: 2196 Application/Control Number: 18/626,260 Page 11 Art Unit: 2196 Application/Control Number: 18/626,260 Page 12 Art Unit: 2196 Application/Control Number: 18/626,260 Page 13 Art Unit: 2196 Application/Control Number: 18/626,260 Page 14 Art Unit: 2196 Application/Control Number: 18/626,260 Page 15 Art Unit: 2196 Application/Control Number: 18/626,260 Page 16 Art Unit: 2196 Application/Control Number: 18/626,260 Page 17 Art Unit: 2196 Application/Control Number: 18/626,260 Page 18 Art Unit: 2196 Application/Control Number: 18/626,260 Page 19 Art Unit: 2196 Application/Control Number: 18/626,260 Page 20 Art Unit: 2196 Application/Control Number: 18/626,260 Page 21 Art Unit: 2196
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