DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I of the device in claims 1-3, while amending the method of claims 4-8 to depend on claim 1, in the reply filed on August 24, 2026 is acknowledged.
Claim Objections
Claim 4 objected to because of the following informalities: typo in the amended claim 4, “forming [[a]] gate electrode” is likely meant to read “forming [[a]] the gate electrode” to connect the gate electrode in claim 4 to the previously claimed electrode in claim 1. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8 are rejected under 35 U.S.C. 103 as being anticipated by Kinoshita et al. US 2018/0197983 A1, hereinafter “Kino”.
Regarding independent claim 1, Kino discloses, A superjunction silicon carbide semiconductor device (Kino Fig 1A and 12 [0050]), comprising: a silicon carbide semiconductor substrate of a first conductivity type (FIG 12 element 1, n+ conductivity type), the silicon carbide semiconductor substrate having a main surface (let the main surface be the top surface traveling into and across the plane of the page as seen in Fig 12); a first semiconductor layer of the first conductivity type (FIG 12 element 2, [0054] "the n-type silicon carbide epitaxial layer 2" is described to have a side "facing the n+ type silicon carbide substrate 1” and a side opposite that), provided at the main surface of the silicon carbide semiconductor substrate (on top of layer 1), the first semiconductor layer having a first surface and a second surface opposite to each other (first surface = top and second surface = bottom, which faces the silicon carbide substrate, layer 1), the second surface of first semiconductor layer facing the silicon carbide semiconductor substrate (bottom of layer 2 faces layer 1);
a parallel pn region provided at the first surface of the first semiconductor layer (third p-type region 3c disposed on the first surface of the first semiconductor layer, 2, creates the parallel pn region), the parallel pn region having a first surface (first surface of the parallel pn region consists of the first surface of layer 2 and the top surfaces of p-type regions 3c) and a second surface opposite to each other (bottom surface of the elements 3c), the second surface of the parallel pn region facing the silicon carbide semiconductor substrate (bottom of 3c faces layer 1), the parallel pn region having therein a plurality of first column regions of the first conductivity type (columns of full device containing n-type conductivity between columns 3c inside of layer 2) and a plurality of second column regions of a second conductivity type (columns of whole device containing 3c of p-type conductivity) disposed repeatedly alternating with one another in a direction parallel to the main surface (Kino [0088] “"the third p-type region 3c may be provided … along a direction parallel to the surface of the n+ type silicon carbide substrate 1", and Fig 12 shows the columns 3c repeating with columns of n-type layer 2 in between);
a second semiconductor layer of the first conductivity type (Fig 12 layer 5), provided at the first surface of the parallel pn region (on top of the parallel pn upper surface of n-type layer 2 in Fig 12), the second semiconductor layer having a first surface and a second surface opposite to each other (the top of layer 5 is the first surface and the bottom is the second surface), the second surface of the second semiconductor layer facing the silicon carbide semiconductor substrate (bottom of layer 5 faces layer 1);
a third semiconductor layer of the second conductivity type (Fig 12 layer 6), provided at the first surface of the second semiconductor layer (layer 6 is on the top surface of layer 5); a first semiconductor region of the first conductivity type, selectively provided in the third semiconductor layer (Fig 12 element 7 [0057] “n+ source region”) and having a doping concentration higher than a doping concentration of the first semiconductor layer (n+ doping concentration is higher than the concentration of n layer [0051]); a trench penetrating through the first semiconductor region and the third semiconductor layer and reaching the second semiconductor layer (Fig 12 element 16 [0071] which reaches through the second semiconductor layer 5); a second semiconductor region of the second conductivity type (second semiconductor region 4 of the p+-type, where p-type conductivity is the second conductivity type), provided in the second semiconductor layer (in layer 5, n-type conductivity) and in contact with a bottom of the trench (Kino [0071] “The bottoms of the trenches 16 may reach the second p+-type base regions 4, or may be positioned in the n-type high-concentration regions 5 between the p-type base layers 6 and the second p+-type base regions 4.”); a third semiconductor region of the second conductivity type (third regions 3 of the p-type conductivity), provided in the second semiconductor layer (also in layer 5), at the first surface of the second semiconductor layer (at the top surface of layer 5), apart from the trench (Fig 12 elements 3 are not in contact with the trench 16); a gate insulating film provided in the trench (gate insulating film 9 [0072]); a gate electrode (gate electrode 10) provided on the gate insulating film, in the trench (10 is on 9 inside of 16 in Fig 12); and another electrode (Fig 12 discloses two electrode elements, 10, let the leftmost electrode be the gate electrode and the rightmost electrode is the “another electrode”) in contact with the first semiconductor region (first semiconductor region, element 7, is in contact with the another electrode through the insulating film) and the third semiconductor layer (third semiconductor layer 6 is in contact with the other electrode through the insulating film);
Kino does not explicitly disclose the final limitation: wherein the plurality of first column regions and the plurality of second column regions contain phosphorus as a dopant thereof.
However, it is commonly known in the art that both phosphorus and nitrogen ions can be implanted as n-type impurities. With the substitution of phosphorus for nitrogen ions, Kino does disclose wherein the plurality of first column regions (let the first column regions be defined from the top to the bottom of the first semiconductor layer 2, in Fig 12, first columns containing elements 3c) and the plurality of second column regions (let the second column regions be defined from the top to the bottom of the layer 2, in Fig 12, in the areas where element 3c is not present, refer to annotated Fig 12 below) contain phosphorus as a dopant thereof (Kino as modified by the obvious substitution of n-type doping with phosphorus, would contain phosphorus at the bottom surface of each column region).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify the nitrogen ion doping of the epitaxial film as disclosed in Kino to be phosphorus ion doping to obtain the predictable result of n-type doping of the epitaxial film.
PNG
media_image1.png
653
827
media_image1.png
Greyscale
Fig A: Kino prior art, Fig 12, annotated by examiner to show defined first and second column regions
Regarding claim 3, Kino with the obvious substitution discussed above discloses, The superjunction silicon carbide semiconductor device according to claim 1 (Kino Fig 12), wherein the first semiconductor layer (layer 2, n-type doped with nitrogen) contains phosphorus (substitute the n-type dopant of nitrogen for phosphorus) as a dopant thereof.
Regarding independent claim 4, Kino with obvious substitution as discussed above discloses, A method of manufacturing the superjunction silicon carbide semiconductor device of claim 1 (Kino Fig 1A and Fig 12 [0050]), the method comprising: preparing the silicon carbide semiconductor substrate (Fig 12 element 1 [0021]); forming the first semiconductor layer (Fig 12 element 2), at the main surface of the silicon carbide semiconductor substrate, so that the second surface thereof faces the silicon carbide semiconductor substrate (first surface of layer 2 = top surface facing up, and second surface = bottom surface facing down);
forming the parallel pn region (p-type regions 3c in parallel alternating columns with n-type layer 2) at the first surface (top) of the first semiconductor layer, so that the second surface thereof faces the silicon carbide semiconductor substrate (bottom of regions 3c also face the silicon carbide semiconductor substrate, 1);
forming the second semiconductor layer (Fig 12 layer 5), at the first surface (top) of the parallel pn region, so that the second surface faces the silicon carbide semiconductor substrate (bottom of layer 5 faces layer 1);
forming the third semiconductor layer (Fig 12 layer 6), at the first surface (top) of the second semiconductor layer;
selectively forming the first semiconductor region (Fig 12 element 7 in layer 6), in the third semiconductor layer, the first semiconductor region having a doping concentration higher than a doping concentration of the first semiconductor layer (n+ doping concentration is higher than n-doping [0051]);
forming the second semiconductor region (layer 4, p+ doping type), in the second semiconductor layer (in layer 5);
forming the third semiconductor region (later 3 of p+ doping type), in the second semiconductor layer at the first surface thereof (at the top of layer 5);
forming the trench (trenches 16 [0071]) so as to penetrate through the first semiconductor region and the third semiconductor layer, and reach the second semiconductor layer (reaches layer 5), so that the bottom of the trench is in contact with the second semiconductor region (see Fig 12, bottom of trench 16 touches layer 4, the second semiconductor region);
forming the gate insulating film (9) in the trench (Fig 12);
forming (the word “a” was deleted, and the examiner will assume that the word “the” was meant to be added to the amended claims here) the gate electrode (gate electrode 10) on the gate insulating film, in the trench;
and forming another electrode (rightmost electrode 10, in Fig 12) in contact with the first semiconductor region and the third semiconductor layer (in contact with first semiconductor region 7 through the insulating film), wherein forming the parallel pn region includes a process of:
forming, at the first surface of the first semiconductor layer (Kino’s first semiconductor layer, 2), an epitaxial film containing silicon carbide (“the first n-type silicon carbide epitaxial layer 2a” [0061] is shown to make up the first layer of the first semiconductor type in Fig 4 and Fig 5),
and implanting phosphorus ions therein (doping nitrogen atoms into epitaxial film 2a, [0061], with the obvious substation of nitrogen dopants for phosphorus dopants), from an entire surface of the epitaxial film (implanted while no use of a mask is mentioned [0061]) thereby forming a semiconductor region of the first conductivity type (Fig 12 layer 2), and in the semiconductor region,
implanting dopant ions of the second conductivity type ([0062] “a p-type impurity, e.g., aluminum atoms, is ion-implanted” into the first n-type silicon carbide epitaxial layer 2a) so as to selectively form (selectively implanted through a mask [0062]) a semiconductor region of the second conductivity type (this creates p-type regions in Fig 12, 3c, as described by [0090-0092]),
the process being performed multiple times (the epitaxial growth and ion implantation are repeated multiple times as shown by the formation of layers 3a, and 5a, followed by layers 3b, and 5b in Fig 5 and [0065-0066]).
Regarding claim 6, Kino and the obvious substitution of phosphorus ions for nitrogen ions discloses, The method according to claim 4, wherein forming the first semiconductor layer includes forming the epitaxial film (Kino Fig 4 and 5, silicon carbide epitaxy layer 2) at the main surface of the silicon carbide semiconductor substrate (Fig 12 element 1) and implanting only the phosphorus ions (nitrogen ions are implanted on layer 2 to form n-type epitaxial film 2a in Fig 3; it is obvious to substitute phosphorus ions) therein from the entire surface of the epitaxial film (nitrogen is doped on the entire surface, no mask is used [0061]).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being anticipated by Kino in view of Takenaka et al. JP 2019-121690 A, hereinafter “Takenaka”.
Regarding claim 7, Kino and the obvious substitution of phosphorus ions for doping discloses The method according to claim 4, however, Kino fails to disclose wherein the epitaxial film is a non-doped epitaxial film of the silicon carbide, or an epitaxial film of silicon carbide with an ultralow concentration of nitrogen atoms in a range of 1×1013 to 1015/cm3.
However, in the same field of endeavor, Takenaka discloses a silicon carbide device that utilizes the method of forming a n-type epitaxial layer (layer 3 Takenaka Fig 1); wherein the epitaxial film is a non-doped epitaxial film of the silicon carbide, or an epitaxial film of silicon carbide (method of forming silicon carbide substrate) with an ultralow concentration of nitrogen atoms (nitrogen used for doping n-type layer) in a range of 1×1013 to 1015/cm3 (“the n—type epitaxial layer 3 having a carrier concentration of 1×1014 to 1015/cm3 is formed on the n-type buffer layer 2 by epitaxial growth”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of forming the epitaxial layer as disclosed by Kino to maintain an ultra-low concentration of nitrogen atoms, “in order to realize an ultra-high breakdown voltage and low loss device of over 10 kV grade” [Takenaka 001-004].
Claim(s) 2, 5, and 8 are rejected under 35 U.S.C. 103 as being anticipated by Kino in view of Takenaka, further in view of Laube et al. (2002). Codoping of 4H-SiC with N- and P-Donors by Ion Implantation. Materials Science Form Vols 389-393 pp 791-794. Doi:10.4028/www.scientific.net/MSF.389-393.791, hereinafter “Laube”.
Regarding claim 2, Kino discloses The superjunction silicon carbide semiconductor device according to claim 1, wherein the plurality of first column regions includes: a plurality of lower first column regions facing silicon carbide semiconductor substrate (let the lower first column regions be the lower half of the first columns regions as annotated above in Kino’s Fig 12, annotated Fig A., the bottom surfaces face the substrate Fig 12 element 1), and a plurality of upper first column regions facing the second semiconductor layer (let the upper first column regions be the top half of the first column regions, wherein the top surface faces the second semiconductor layer, Kino Fig 12 layer 5); the plurality of lower first column regions contain nitrogen as a dopant thereof (the first semiconductor layer Kino’s Fig 12, layer 2 is doped with nitrogen, and it would be obvious to substitute phosphorus for this singular dopant; however, Kino does not clearly disclose having phosphorus as a second dopant).
Kino does not disclose the plurality of upper first column regions and the plurality of second column regions contain phosphorus as the dopant thereof.
However, in the same field of endeavor, Laube discloses the benefits of doping a silicon carbide epilayers with both phosphorus and nitrogen; therefore, disclosing the plurality of upper first column regions and the plurality of second column regions contain phosphorus as the dopant thereof (P1(X) samples P1(N+P) dopants in Laube Table 1 page 793).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device and method of formation of the device of Kino to have an epitaxial layer with an ultra-low nitrogen atom concentration such as the one disclosed in Tanenaka, as applied to claim 7, and also to further dope the upper first column regions and second column regions with phosphorous as disclosed in Laube to reach a high ion concentration of n-type dopants without relying on only nitrogen ion dopants. This co-doping is effective for maintaining a high carrier concentration while avoiding a saturation of nitrogen atoms in the device as, “higher N concentrations form preferentially complexes, which do not act as shallow donors” while “P-atoms can be incorporated into the 4H-SiC lattice at electrically active lattice sites at concentrations greater than 2×1020 /cm3 “[Laube pp 794 lines 4-5].
Regarding claim 5, Kino in view of Taneaka and Laube discloses, The method according to claim 4 (disclosed by Kino), wherein the process further includes, before implanting the phosphorus ions, implanting, in a lower region of the epitaxial film (Taneaka’s epitaxial layer 3 in Fig 1), nitrogen ions from the entire surface of the epitaxial film (nitrogen ions are doped through a nitrogen-containing dopant gas [Taneaka 0028]), the lower region facing the silicon carbide semiconductor substrate (bottom of layer 3 in Fig 1 faces the silicon carbide semiconductor substrate 1).
Regarding claim 8, Kino in view of Taneaka and Laube discloses, The method according to claim 4, wherein the first semiconductor layer (Kino Fig 12 element 2) contains phosphorus and nitrogen as the dopant (modify Kino with the ultra-low concentration epitaxial film n-type doped layer as disclosed in Taneaka, and further modify the n-type doped layer to be co-doped with phosphorus to achieve a higher carrier concentration as disclosed in Laube).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Ishikawa et al. WO 2012108165 A1 discloses a silicon carbide semiconductor device with parallel pn junction region in the upper portion of the drift layer region, Fig 14.
Shiomi et al. WO 2016002766 A1 disclosing a silicon carbide device with a nitrogen doped drift region further doped with phosphorus to create source regions in Fig 1
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA MICKEY whose telephone number is (571)270-3109. The examiner can normally be reached M-F, 8am to 5pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD DICKE can be reached at 571 270 7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TERESA N MICKEY/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights