DETAILED ACTION
The response filed on or after May 12,2026 is being examined.
Information Disclosure Statement
Applicants must continue to submit prior art references throughout the patent application process. A supplemental IDS must be submitted if prior art is discovered through a foreign patent application or an International Patent Search, or a related application before a prosecution closes.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Rejection of claim 6, the term “ the PCB” lacks antecedent basis in line 5 of claim 6, because there are two PCB mentioned in the claims. the PCB should be clarify as the first PCB.
Additionally, “at least one of the edges of the PCB” appears to be “ at least one of edges of the first PCB”;
The term “respective connection edges” refers to what connection edges of M orifices, the first PCB; or the spacers or something else.
Additionally, see figure 1 herein, the pads and spacer are part of the first PCB; they are provided on a top surface of the substrate of the first board; and they are making a top surface of the PCB; they are not on the top surface of the PCB; they are on a top surface of substrate of the first PCB.
Note that the bottom surface of the second PCB comprises a series of N conductive pads in land grid array form that are respectively coupled with the top surface of the first PCB comprises a series of N conductive pads.
Therefore, claim 6 is unclear or indefinite and lacks essential structure.
Rejection of claims 7-8, claims 7-8 are rejected by the same reason applied to rejection of claim 6 above.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AlA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Note: The rejection under USC 102 and USC 103 below with modified language are given to advance prosecution; however, proper clarification is required under rejection of USC 112 above to consider the rejection under USC 102 and USC 103.
Claim Rejections - 35 USC § 102
The following is a quotation of 35 U.S.C. 102 which forms the basis for all rejections set forth in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 6-7 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) (whichever apply) as being anticipated by Junichi et al. (JPH11330661, herein referred to as Junichi).
Rejection of claim 6, Junichi discloses an electronic module (figs. 1-9 of Junichi) comprising;
a first printed circuit board (a top circuit board (board 30) in figure 3 as first circuit board) comprising:
a top surface, a bottom surface (see top and bottom surfaces of the first circuit board in figures 1-9 wherein connection side surface to substrate 1 is top surface or consider upside down figure of figure 3 ),
a series of M castellated orifices on at least one of first PCB (see castellated orifices on at least one edge of first circuit board )
a series of N conductive pads on a upper surface of a substrate of the first PCB connecting to the M orifices at respective connection edges of M orifices or the spacers or the first PCB , M and N being integers greater than 1 (see pads on first circuit board) , wherein each of the pads on the upper surface of a substrate of the first PCB is partially covered by a respective spacer such that an area between the connection edge and a border of a remaining pad area is completely covered by the spacer (see spacer covering connection edge portion and a boarder of remaining portion of pad covered by resist 10), and the connection edge and the border of the remaining pad area have a minimum distance of D, D being a positive number (see figure 3), and
a second PCB (substrate 13 as second PCB), wherein the second PCB is overlaid on top of the first PCB (see figure 3), a bottom surface of the second PCB faces a top surface of the first PCB ( see upside down figure 3), the bottom surface of the second PCB comprises a series of N conductive pads in land grid array form that are respectively coupled with the N pads on the top surface of the first PCB, and the coupled pads are soldered together (see pads of the first PCB and the second PCB are connected by solder 14).
Rejection of claim 7, Junichi discloses the electronic module according to claim 6, wherein the coupled pads are soldered together via a solder paste being applied on the remaining pad area of each pad on the top surface of the first PCB or on the N pads of the second PCB (see solder 14 in figure 3(a) of Junichi) .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Junichi.
Rejection of claim 8, Junichi discloses the electronic module according to claim 6,but fails to disclose wherein at least one electronic component is disposed on the bottom surface of the second PCB.
Examiner makes official notice that at least one electronic component is disposed on the bottom surface of the second PCB so that the at least one electronic component is between and covered by two printed circuit boards which further increase protection of the electronic components.
It would have been obvious to ordinary skill in the art before the effective filing date of the claimed invention to modify the electronic module of Junichi to have at least one electronic component is disposed on the bottom surface of the second PCB for the reason mentioned above in the official notice.
Pertinent Prior Arts
The prior arts made of record and not relied upon is considered pertinent to applicant's disclosure. Please refer to the enclosed PTO-892 form for the citation of pertinent arts in the present case, all of which disclose various board to board interconnects assemblies.
Response to Arguments
Applicant argument would not be considered for multiple regions.
One of the main reason is that claim has main issue under 112 which is not properly defined. See rejection of claim 1 under USC 112. Additionally, applicants failed to solve all the issue mentioned in prior action, thefore, would not overcome the rejection.
Furthermore It appears that applicant arguments based on figures and disclosure, not based on claim which raise further issue under USC 112; specification is narrow then the claim; claim do not clearly defines what is connection edges referred to. the claimed structure is broader than the structure in specification; and the structure in specification is narrower than the claimed invention.
Also see claim sates Each of the pads on the top surface of the board is partially covered by a respective spacer such that an area between the connection edge and a border of a remaining pad area is completely covered by the spacer. This limitation is very board and can be has multiple definitions.
Claim do not say that wherein each top surface of the pads on a top surface of the substrate is partially covered by a respective spacer wherein an area of the pad is completely covered by the spacer in one side of the pad toward a first side surface of the pad connecting the orifice and a remaining pad portion provides entirely second side surface of the pad opposite to the first side surface of the pad and completely unexposed by the spacer.
Current claim very broad then specification wherein connection edges can be edges of spacers or first PCB or else whichever reads; while any area or region or part of pad covered by spacer can be just side edge or surface of the pad or any region or boarder that contacts pads and spacers. Note that claims do not clearly mentions that how pads are structures on top layer of substrate, instead claims mentioned that pads are top surface of the first pcb such as they are surface mounted devices (capacitor, chip.. etc.) on a top surface of PCB. Should ordinary skill person consider pads/spacers as surface mounted devices or parts of the first PCB. Clarification is required.
Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993); also, the rejection is based on the claimed structure, not the narrow structure as mentioned in specification; thefore, claim lacks the structure as well as clarification.
Claim has major issue under 112 which required further clarification.
Therefore, applicants arguments are not persuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Communication
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/PARESH PAGHADAL/ Primary Examiner, Art Unit 2847
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