Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 23 is objected to under 37 CFR 1.75 as being a substantial duplicate of claim 18. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-8, 11-26 are rejected under 35 U.S.C. 103 as being unpatentable over Gendler (United States Patent Application Publication US 2016/0231798), hereinafter Gendler in view of Whatmough et al. (United States Patent Application Publication US 2023/0297432), hereinafter Whatmough.
Regarding claim 1, Gendler teaches a power management system in an integrated circuit (IC) chip ([0075] “Referring now to FIG. 10, shown is a block diagram of a representative SoC.”), configured to: sample processing activity of an assigned processing device of a plurality of processing devices in a processor-based system to generate a plurality of activity samples; determine a current flow rate of the assigned processing device based on the plurality of activity samples; determine whether the current flow rate of the assigned processing device exceeds a threshold current flow rate ([0110] “A processor, such as a multi-core processor, may have a power management unit (PMU) that can monitor telemetry data associated with power consumption of portions of the processor, e.g., the cores, one or more caches, interconnect, uncore, etc.” [0112] “Events may include…detection of a current spike, e.g., via comparison of current slop (dI/dt) to a threshold value” Telemetry data associated with power consumption includes various events. Events include detection of a current spike, e.g., via comparison of current slope (dI/dt) to a threshold value. Thus, a PMU for a processor monitors events, such as current spikes by determining that the current slope to the threshold, which suggests that the current slope exceeds the threshold.);
in response to determining the current flow rate of the assigned processing device exceeds the threshold current flow rate ([0129] “a count of high dI/dt events may exceed a corresponding threshold value and can trigger a push of the corresponding telemetry data from a dI/dt event accumulator to the PMU, independent of any pull commands that might otherwise be generated by the PMU. A push of the dI/dt data may enable the PMU to quickly react to, e.g., an imminent rise of temperature of the core due a series of current spikes.”):
throttle processing activity of the assigned processing device to throttle its power consumption ([0110] “The PMU may adjust power supplied to each of the components based on the telemetry data received.” [0142] “The PMA 1720 may also include power adjustment logic 1728 that can adjust one or more operation parameters, e.g., clock frequency of the core 171 based upon input, received from the PMU 1730.” In response to the determination that the high dI/dt events, power supplied to the processor is adjusted or throttled.);
However, Gendler does not explicitly teach to estimate the power consumption of the assigned processing device based on the plurality of activity samples; generate an activity power event based on the estimated power consumption of the assigned processing device; and generate a power limiting management response to cause power consumption to be throttled in the IC based on a plurality of activity power events based on the generated activity power event for each assigned processing device of the plurality of processing devices.
Whatmough teaches to estimate the power consumption of the assigned processing device based on the plurality of activity samples ([0041] “predicate generation circuitry 424 may be provided to convert the sparsity metadata into predicates that are supplied to CPU 408 to control predication of vector operations, which may allow for further power savings at the CPU based on the sparsity metadata.” [0046] “The monitoring circuitry 530 may detect power hungry events based on signals received from the processing circuitry 520 indicating the occurrence of these power hungry events.” [0047] “The power management circuitry 522 may have MPMM setting control circuitry 538 that uses metadata related to the input data and/or instructions to be processed by the processing circuitry 520 so as to control the MPMM settings.” [0061] “At block 710, method 700 may predict current consumption using proxies.” Whatmough suggests that the power consumption is predicted, which is interpreted as estimate the power consumption of the assigned processing device. The prediction or estimation of the power consumption is based on proxies, which Whatmough suggests various monitored data of sparsity metadata, occurrence of power hungry events, input data and/or instructions to be processed.);
generate an activity power event based on the estimated power consumption of the assigned processing device ([0062] “At block 714, method 700 may determine di/dt events, such as, e.g., whether the actual current (Icurr) is greater than the previous current (Iprev). At decision block 718, method 700 may determine whether a di/dt event (e.g., rapid change in current or voltage) is likely.” Based on the prediction or estimation, di/dt events, which is an activity power event, is determined.); and
generate a power limiting management response to cause power consumption to be throttled in the IC based on a plurality of activity power events based on the generated activity power event for each assigned processing device of the plurality of processing devices ([0062] “If yes, then method may proceed to block 724 so as to modify scheduling of the graph through NOPs/clock-gating cycles as supported by the target hardware (HW).” [0063] “At block 728, method 700 may modify the graph schedule and/or deploy an optimized graph to mitigate various di/dt events, such as, e.g., rapid voltage droops and/or current spikes.” [0072] “If yes, then method 800 may proceed to block 838 to update local DVFS setting (Dynamic Voltage Frequency Scaling settings) for the neural network (NN) engine.” [0044] “the power management feature may be configured to count a number of high energy events over an evaluation period so as to keep a rolling average across time. If the rolling average exceeds a pre-defined threshold, then the MPMM policy may throttle the throughput of the processing circuitry 222A, 222B, 222C, e.g., by throttling dispatch of processing operations or instructions or dispatch of input data to be processed, or by reducing clock frequency.” Based on the determination that the di/dt events likely to occur, throttling operation is performed to reduce power consumption.).
determine whether a throughput in a processing device of the plurality of processing devices should be throttled based on the received plurality of activity power events ([0046] “the power management circuitry 522 may implement the MPMM policy with monitoring circuitry 530 for monitoring occurrence of certain power-hungry events occurring on the SoC, such as, e.g., certain types of processing operations and/or instructions that are expected to drain power or cause interrupts/exceptions.” FIG. 5 “throughput threshold” In order to compare the throughput to a throughput threshold, Whatmough suggests that the throughput is monitored. Based on the monitored throughput and the throughput threshold, the policy for the throughput is determined.); and
in response to determining the throughput in the processing device of the plurality of processing devices should be throttled ([0046] “comparison logic 534 may compare the event rate metric with a certain threshold, and the comparison may be used to determine whether to apply a restriction in the throughput of instructions or data processed by the processing circuitry 520 (e.g., CPU 222A, GPU 222B or NPU 222C, as described herein).”):
generate the power limiting management response by being configured to generate a throughput throttling power limiting management response to be received by the processing device to be throughput throttled; and receive the throughput throttling power limiting management response in response to generating the throughput throttling power limiting management response for its assigned processing device; and throttle the processing activity of its assigned processing device to throttle its power consumption based on the received throughput throttling power limiting management response ([0044] “If the rolling average exceeds a pre-defined threshold, then the MPMM policy may throttle the throughput of the processing circuitry 222A, 222B, 222C, e.g., by throttling dispatch of processing operations or instructions or dispatch of input data to be processed, or by reducing clock frequency.” [0047] “throughput control logic 86 may be provided in association with the processing circuitry 520 to monitor the rate of data and/or instructions that have been dispatched to the processing circuitry 520 within a given period so that a flow of the data and/or instructions may be halted or reduced if a restriction needs to be applied to limit energy consumption based on monitoring of the power-hungry events by the monitoring circuitry 530.” Based on the determination the throughput exceeding the threshold, the restriction to limit power consumption or the throttling is performed.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Gendler by incorporating the teaching of Whatmough of throttling power consumption to reduce power consumption based on the activity power events, which is based on the estimated power consumption of the assigned processing device and throttling the processing activity of its assigned processing device to throttle its power consumption based on received throughput throttling power limiting management response determined based on the received plurality of activity power events. They are all directed toward power management in the SoC. As recognized by Whatmough, neural network workloads are typically compute bound and when processed on digital circuitry, NN workloads easily generate large current spikes, which results in catastrophic voltage droops on-chip and logical errors ([0003]). Thus, by predicting the workload, which potentially cause the large current spikes, the power consumption can be reduced, which avoids the damages and errors from the large current spikes. Therefore, it would be advantageous to incorporate the teaching of Whatmough of throttling power consumption to reduce power consumption based on the activity power events, which is based on the estimated power consumption of the assigned processing device in order to improve the stability of the system.
Regarding claim 2, Gendler in view of Whatmough teaches all the limitations of the power management system of claim 1, as discussed above.
Gendler, as modified above, further teaches wherein the plurality of processing devices comprises a plurality of network nodes in the IC, and the assigned processing device of the plurality of processing devices comprises an assigned network node (FIG. 16, FIG. 17 As defined in Oxford Languages, a node is a point at which lines or pathways intersect or branch; a central or connecting point. A communication node is interpreted as a point of communication path. As the core region and uncore region are communicating through a communication interconnect, a on-chip system fabric, and a sideband path.)
Regarding claim 3, Gendler in view of Whatmough teaches all the limitations of the power management system of claim 1, as discussed above.
Gendler, as modified above, further teaches wherein the plurality of processing devices comprises a plurality of processing units in the IC, and the assigned processing device of the plurality of processing devices comprises an assigned processing unit (FIG. 16, FIG. 17 As shown in FIG. 16 and 17, the processor further includes a plurality of cores and a plurality of uncore region.).
Regarding claim 4, Gendler in view of Whatmough teaches all the limitations of the power management system of claim 1, as discussed above.
Whatmough further teaches to sample the processing activity of the assigned processing device by being configured to sample the processing activity of a single assigned processing device of the plurality of processing devices to generate the plurality of activity samples ([0113] “Each measurement may be determined by a local counter. A cumulative count (also tally herein) for a time period between requests from the PMU may be stored in a corresponding accumulator (also accumulator logic herein).” [0134] “each local counter 1616, may generate an indication (e.g., a count) in response to a particular core event type (e.g. dI/dt spike, memory load, memory store, etc.)...”).
Regarding claim 5, Gendler in view of Whatmough teaches all the limitations of the power management system of claim 2, as discussed above.
Gendler, as modified above, further teaches to throttle the processing activity by being configured to throttle the processing activity of the assigned network node to throttle its power consumption by being configured to selectively enable and disable communication flow of the assigned network node ([00155] “the PMU may determine to reduce activity level of the core, e.g., via reduction of instruction throughput (e.g., throttling), reduction of clock speed, reduction of operating voltage, etc. or a combination thereof.” As the instruction throughput is reduced or throttled, the flow of instruction or workload to be executed on the processor or the core is disabled.).
Regarding claim 6, Gendler in view of Whatmough teaches all the limitations of the power management system of claim 5, as discussed above.
Gendler, as modified above, further teaches to selectively enable and disable the communication flow in the assigned network node by being configured to selectively generate enable and disable throttle signals that cause the assigned network node to selectively enable and disable, respectively, the communication flow in the assigned network node ([0155] “the PMU may determine to reduce activity level of the core, e.g., via reduction of instruction throughput (e.g., throttling), reduction of clock speed, reduction of operating voltage, etc. or a combination thereof.” As the PMU controls the activity level of the core or the power related parameters, the command or signals to throttle the activity or the parameters must be generated and transmitted.).
Regarding claim 7, Gendler in view of Whatmough teaches all the limitations of the power management system of claim 1, as discussed above.
Whatough, as modified above, further teaches for each assigned processing device: an accumulate circuit configured to, for each activity sample of the plurality of activity samples: correlate the received activity sample into a next estimated incoming current demand; and accumulate the next estimated incoming current demand into a next estimated current demand ([0041] “sparsity metadata may be supplied to the power management circuitry 422 so that the sparsity of the input data sets are taken into account for controlling power management policy.” [0046] “The monitoring circuitry 530 may detect power hungry events based on signals received from the processing circuitry 520 indicating the occurrence of these power hungry events.” [0047] “The power management circuitry 522 may have MPMM setting control circuitry 538 that uses metadata related to the input data and/or instructions to be processed by the processing circuitry 520 so as to control the MPMM settings.” [0053] “At block 614, method 600 may simulate the scheduled graph execution to identify potential changes in load current.” [0061] “At block 710, method 700 may predict current consumption using proxies.” [0069] “At block 810, method 800 may predict current consumption using proxies.” The prediction of power consumption is based on the prediction of power consumption for the data to be processed, which is the processing activity for the next time window. The power consumption of the data be processed is related to a current power consumption which is compared to the previous current to a predicted or current current.); and
a di/dt circuit configured to: compare the next estimated current demand to a previous estimated current demand to generate a next current flow rate of the assigned processing device ([0062] “At block 714, method 700 may determine di/dt events, such as, e.g., whether the actual current (Icurr) is greater than the previous current (Iprev).”);
wherein the power management system is configured to: determine whether the next current flow rate of the assigned processing device exceeds the threshold current flow rate; and in response to determining the next current flow rate of the assigned processing device exceeds the threshold current flow rate: throttle the processing activity of the assigned processing device to throttle its power consumption ([0044] “the power management feature may be configured to count a number of high energy events over an evaluation period so as to keep a rolling average across time. If the rolling average exceeds a pre-defined threshold, then the MPMM policy may throttle the throughput of the processing circuitry 222A, 222B, 222C, e.g., by throttling dispatch of processing operations or instructions or dispatch of input data to be processed, or by reducing clock frequency.” [0048] “Other types of management policy may also be controlled based on metadata, such as dynamic voltage or frequency scaling, requests to a voltage regulator for supply of more or less voltage, as well as a scheme for limiting the rate of change of power requirements by monitoring differences over time of expected power requirements and taking action to smooth changes in power demand when required, e.g., by either throttling the dispatch of data or instructions to the processing circuitry 520.” Thus, based on the determination that di/dt events likely occurs, various throttling to reduce power consumption is performed.).
Regarding claim 8, Gendler in view of Whatmough teaches all the limitations of the power management system of claim 7, as discussed above.
Whatmough, as modified above, further teaches for each assigned processing device, to: receive the plurality of activity samples for a current local time window; and
wherein the di/dt circuit is configured to: compare the next estimated current demand for the current local time window to the previous estimated current demand for a previous local time window prior to the current local time window, to generate a next current flow rate of the assigned processing device ([0041] “sparsity metadata may be supplied to the power management circuitry 422 so that the sparsity of the input data sets are taken into account for controlling power management policy.” [0046] “The monitoring circuitry 530 may detect power hungry events based on signals received from the processing circuitry 520 indicating the occurrence of these power hungry events.” [0047] “The power management circuitry 522 may have MPMM setting control circuitry 538 that uses metadata related to the input data and/or instructions to be processed by the processing circuitry 520 so as to control the MPMM settings.” [0053] “At block 614, method 600 may simulate the scheduled graph execution to identify potential changes in load current.” [0061] “At block 710, method 700 may predict current consumption using proxies.” [0069] “At block 810, method 800 may predict current consumption using proxies.” [0062] “At block 714, method 700 may determine di/dt events, such as, e.g., whether the actual current (Icurr) is greater than the previous current (Iprev).” When the actual current and the previous current are measured, the time window for previous current is measured prior to the time window for the actual current. Then, in order to determine dI/dt, which is to generate the current flow rate, the previous current and the actual current are compared.).
Regarding claim 11, Gendler in view of Whatmough teaches all the limitations of the power management system of claim 1, as discussed above.
Whatmough further teaches to determine a throughput throttling for at least one processing device of the plurality of processing devices based on the received plurality of activity power events ([0046] “the power management circuitry 522 may implement the MPMM policy with monitoring circuitry 530 for monitoring occurrence of certain power-hungry events occurring on the SoC, such as, e.g., certain types of processing operations and/or instructions that are expected to drain power or cause interrupts/exceptions.”; and
in response to determining the throughput throttling for the at least one processing device: generate the power limiting management response by being configured to generate a throughput throttling power limiting management response to throttle the throughput of the at least one processing device ([0047] “throughput control logic 86 may be provided in association with the processing circuitry 520 to monitor the rate of data and/or instructions that have been dispatched to the processing circuitry 520 within a given period so that a flow of the data and/or instructions may be halted or reduced if a restriction needs to be applied to limit energy consumption based on monitoring of the power-hungry events by the monitoring circuitry 530.”).
Regarding claim 12, Gendler in view of Whatmough teaches all the limitations of the power management system of claim 1, as discussed above.
Gendler, as modified above, further teaches determine a clock throttling of at least one clock circuit of one or more clock circuits, to clock throttle the power consumption of at least one processing device of the plurality of processing devices based on the received plurality of activity power events; and in response to determining the clock throttling for the at least one processing device: generate the power limiting management response by being configured to generate a clock throttling power limiting management response to throttle a clock signal ([0116] “the PMA is to operate in its own power domain that is distinct from the core, e.g., according to a different clock (e.g., the PMA may operate at a lower clock frequency than the core.” [0142] “The PMA 1720 may also include power adjustment logic 1728 that can adjust one or more operation parameters, e.g., clock frequency of the core 17120 based upon input received from the PMU 1730.” As each domain or different cores are operating at different clock frequencies, different clock signals are generated for different domains. Furthermore, each domain are monitored to detect dI/dt current spikes and other events, which further controls the power related parameters, as discussed above.).
Regarding claim 13, Gendler in view of Whatmough teaches all the limitations of the power management system of claim 1, as discussed above.
Gendler, as modified above, further teaches to determine a clock throttling of a clock circuit, to clock throttle power consumption of a plurality of processing units based on the received plurality of activity power events; and in response to determining the clock throttling for the clock circuit: generate the power limiting management response by being configured to generate a clock throttling power limiting management response to throttle a clock signal ([0116] “the PMA is to operate in its own power domain that is distinct from the core, e.g., according to a different clock (e.g., the PMA may operate at a lower clock frequency than the core.” [0142] “The PMA 1720 may also include power adjustment logic 1728 that can adjust one or more operation parameters, e.g., clock frequency of the core 17120 based upon input received from the PMU 1730.” As each domain or different cores are operating at different clock frequencies, different clock signals are generated for different domains. Furthermore, each domain are monitored to detect dI/dt current spikes and other events, which further controls the power related parameters, as discussed above. The telemetry data is associated with power consumption of portions of the processors.).
Regarding claim 14, Gendler in view of Whatmough teaches all the limitations of the power management system of claim 1, as discussed above.
Gendler, as modified above, further teaches to determine a performance throttling of at least one processing device of the plurality of processing devices based on the received plurality of activity power events ([0111] “the telemetry data may include, for each core of a multi-core processor for a particular time period, an indication (also measurement herein) of an event occurrence or of multiple occurrences of the event.”); and
in response to determining the performance throttling for the at least one processing device: generate the power limiting management response by being configured to generate a performance throttling power limiting management response to throttle performance of the at least one processing device ([0136] “Based upon the received telemetry data the PMU 1632 may determine whether to cause adjustment of one or more power parameters associated with the core region 1602, e.g., core voltage, clock frequency, etc. associated with the core 16120.” [1055] “the PMU may determine to reduce activity level of the core, e.g., via reduction of instruction throughput (e.g., throttling), reduction of clock speed, reduction of operating voltage, etc. or a combination thereof.”).
Regarding claim 15, Gendler in view of Whatmough teaches all the limitations of the power management system of claim 1, as discussed above.
Gendler, as modified above, further teaches receive at least one non-activity power event not based on the plurality of activity power events ([0112] “Events may include, but are not limited to streaming single instruction multiple data instruction multiple data (SIMD) extension instructions (SSE 128,256,512 bit), fused multiply/add (FMA) instructions, mid-level cache lookup, data cache load/store dispatch, memory load/store, instruction decode, micro-operation allocation, branch predictor thread identification replace, out-of-order (000) thread select, power meter measurement, instances that the core is in an active state (e.g., CO power state), instances of the core in a Cl power state, instances of the core in a C6 power state, detection of a current spike, e.g., via comparison of current slope (dl/dt) to a threshold value, energy efficiency count (e.g., a count of instances that misses occur that result in accesses to a dynamic random access memory (DRAM) due to a backlog at the 000), and other events that may be measured on a periodic basis or on a continual basis”); and
generate the power limiting management response to cause power consumption to be throttled in the IC based on the received plurality of activity power events and the at least one non-activity power event ([0136] “Based upon the received telemetry data the PMU 1632 may determine whether to cause adjustment of one or more power parameters associated with the core region 1602, e.g., core voltage, clock frequency, etc. associated with the core 16120.”).
Regarding claim 16, Gendler in view of Whatmough teaches all the limitations of the power management system of claim 1, as discussed above.
Gendler, as modified above, further teaches wherein the at least one non-activity power event is comprised from the group consisting of a temperature power event indicating a temperature in the IC ([0155] “an indication that the accumulator value exceeds the corresponding threshold may indicate that a thermal condition is imminent”).
Whatmough further teaches a voltage droop event indicating a voltage droop in at least one power rail of a plurality of power rails ([0003] “these current spikes may result in catastrophic voltage droops on-chip” [0055] “At block 628, method 600 may deploy an optimized graph to mitigate various di/dt events, such as, e.g., rapid voltage droops and/or current spikes.” The current spike resulting voltage droop is an event to cause the voltage droop.).
Regarding claim 17, Gendler in view of Whatmough teaches all the limitations of the power management system of claim 1, as discussed above.
Whatmough further teaches the power management system of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter ([0074] “Examples of computing systems, environments, and/or configurations that may be suitable for use with the various technologies described herein include, but are not limited to, personal computers, server computers, hand-held or laptop devices, multiprocessor systems, microprocessor based systems, set top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, smart phones, tablets, wearable computers, cloud computing systems, virtual computers, marine electronics devices, and the like.”).
Regarding claim(s) 18-26, the claim(s) 18-26 are the method claims of the apparatus claim(s) 1, 4-7, 11-12, and 14. The claim(s) 18-26 do not further teach or define the limitation over the limitations recited in the rejected claims above. Therefore, Gendler in view of Whatmough teaches all the limitations of the claim(s) 18-26.
Allowable Subject Matter
Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Gendler teaches a power management unit to receive telemetry data including current spikes and change operating parameters of each core based on the received telemetry data including operating voltage, clock frequency, duty cycle, throttling, etc. and combinations thereof. However, Gendler does not teach “a multiplexing circuit comprising a plurality of first inputs and a first output; a plurality of summing circuits each comprising a second output coupled to a first input of the plurality of first inputs, and a second input; and a plurality of latch circuits comprising an incoming latch circuit and a plurality of shift latch circuits, each of the plurality of latch circuits comprising a third input and a third output, wherein: the third output of each latch circuit of the plurality of latch circuits is coupled to an input of a next shift latch circuit of the plurality of shift latch circuits; and the third output of each latch circuit of the plurality of latch circuits is also coupled to the second input of a summing circuit of the plurality of summing circuits; wherein: the incoming latch circuit is configured to, for each local time window: receive the next estimated incoming current demand; and shift the next estimated incoming current demand to its third output; the plurality of shift latch circuits are configured to: shift in an estimated current demand from its third input; and shift the estimated current demand to its third output; and each summing circuit of the plurality of summing circuits is configured to: receive an estimated current demand on its second input; and subtract the received estimated current demand from the next estimated incoming current demand to generate the next current flow rate on its third output; and the multiplexing circuit configured to pass the next current flow rate on the first input of the plurality of first inputs, to the first output.”
Whatmough teaches monitoring workloads for current spikes and modifying load scheduling, throttling a throughput and dispatch of processing operations or instructions. However, Whatmough does not teach “a multiplexing circuit comprising a plurality of first inputs and a first output; a plurality of summing circuits each comprising a second output coupled to a first input of the plurality of first inputs, and a second input; and a plurality of latch circuits comprising an incoming latch circuit and a plurality of shift latch circuits, each of the plurality of latch circuits comprising a third input and a third output, wherein: the third output of each latch circuit of the plurality of latch circuits is coupled to an input of a next shift latch circuit of the plurality of shift latch circuits; and the third output of each latch circuit of the plurality of latch circuits is also coupled to the second input of a summing circuit of the plurality of summing circuits; wherein: the incoming latch circuit is configured to, for each local time window: receive the next estimated incoming current demand; and shift the next estimated incoming current demand to its third output; the plurality of shift latch circuits are configured to: shift in an estimated current demand from its third input; and shift the estimated current demand to its third output; and each summing circuit of the plurality of summing circuits is configured to: receive an estimated current demand on its second input; and subtract the received estimated current demand from the next estimated incoming current demand to generate the next current flow rate on its third output; and the multiplexing circuit configured to pass the next current flow rate on the first input of the plurality of first inputs, to the first output.”
CALUGARU et al. (United States Patent Application Publication US 2021/0294403) teaches to dynamically altering power settings in anticipation of the predicted future load transients. However, CALUGARU does not teach “a multiplexing circuit comprising a plurality of first inputs and a first output; a plurality of summing circuits each comprising a second output coupled to a first input of the plurality of first inputs, and a second input; and a plurality of latch circuits comprising an incoming latch circuit and a plurality of shift latch circuits, each of the plurality of latch circuits comprising a third input and a third output, wherein: the third output of each latch circuit of the plurality of latch circuits is coupled to an input of a next shift latch circuit of the plurality of shift latch circuits; and the third output of each latch circuit of the plurality of latch circuits is also coupled to the second input of a summing circuit of the plurality of summing circuits; wherein: the incoming latch circuit is configured to, for each local time window: receive the next estimated incoming current demand; and shift the next estimated incoming current demand to its third output; the plurality of shift latch circuits are configured to: shift in an estimated current demand from its third input; and shift the estimated current demand to its third output; and each summing circuit of the plurality of summing circuits is configured to: receive an estimated current demand on its second input; and subtract the received estimated current demand from the next estimated incoming current demand to generate the next current flow rate on its third output; and the multiplexing circuit configured to pass the next current flow rate on the first input of the plurality of first inputs, to the first output.”
de la Cropte de Chanterac et al. (United States Patent Application Publication US 2016/0091954) teaches monitoring operational parameter of a corresponding functional unit to adjust one or more performance settings of the computing system. However, de la Cropte de Chanterac does not teach “a multiplexing circuit comprising a plurality of first inputs and a first output; a plurality of summing circuits each comprising a second output coupled to a first input of the plurality of first inputs, and a second input; and a plurality of latch circuits comprising an incoming latch circuit and a plurality of shift latch circuits, each of the plurality of latch circuits comprising a third input and a third output, wherein: the third output of each latch circuit of the plurality of latch circuits is coupled to an input of a next shift latch circuit of the plurality of shift latch circuits; and the third output of each latch circuit of the plurality of latch circuits is also coupled to the second input of a summing circuit of the plurality of summing circuits; wherein: the incoming latch circuit is configured to, for each local time window: receive the next estimated incoming current demand; and shift the next estimated incoming current demand to its third output; the plurality of shift latch circuits are configured to: shift in an estimated current demand from its third input; and shift the estimated current demand to its third output; and each summing circuit of the plurality of summing circuits is configured to: receive an estimated current demand on its second input; and subtract the received estimated current demand from the next estimated incoming current demand to generate the next current flow rate on its third output; and the multiplexing circuit configured to pass the next current flow rate on the first input of the plurality of first inputs, to the first output.”
Hovis et al. (United States Patent Application Publication US 2021/0081016) teaches monitoring indications of pending operations for a processing core of an integrated circuit and predicting change in workload for the processing core based on the indication of the pending operations, which alters a clock frequency provided to the processing core. However, Hovis does not teach “a multiplexing circuit comprising a plurality of first inputs and a first output; a plurality of summing circuits each comprising a second output coupled to a first input of the plurality of first inputs, and a second input; and a plurality of latch circuits comprising an incoming latch circuit and a plurality of shift latch circuits, each of the plurality of latch circuits comprising a third input and a third output, wherein: the third output of each latch circuit of the plurality of latch circuits is coupled to an input of a next shift latch circuit of the plurality of shift latch circuits; and the third output of each latch circuit of the plurality of latch circuits is also coupled to the second input of a summing circuit of the plurality of summing circuits; wherein: the incoming latch circuit is configured to, for each local time window: receive the next estimated incoming current demand; and shift the next estimated incoming current demand to its third output; the plurality of shift latch circuits are configured to: shift in an estimated current demand from its third input; and shift the estimated current demand to its third output; and each summing circuit of the plurality of summing circuits is configured to: receive an estimated current demand on its second input; and subtract the received estimated current demand from the next estimated incoming current demand to generate the next current flow rate on its third output; and the multiplexing circuit configured to pass the next current flow rate on the first input of the plurality of first inputs, to the first output.”
Laird et al. (United States Patent US 9304560) teaches a data storage device that detects a current transient exceeding a current threshold, which causes to reduce power drawn from a host. However, Laird does not teach “a multiplexing circuit comprising a plurality of first inputs and a first output; a plurality of summing circuits each comprising a second output coupled to a first input of the plurality of first inputs, and a second input; and a plurality of latch circuits comprising an incoming latch circuit and a plurality of shift latch circuits, each of the plurality of latch circuits comprising a third input and a third output, wherein: the third output of each latch circuit of the plurality of latch circuits is coupled to an input of a next shift latch circuit of the plurality of shift latch circuits; and the third output of each latch circuit of the plurality of latch circuits is also coupled to the second input of a summing circuit of the plurality of summing circuits; wherein: the incoming latch circuit is configured to, for each local time window: receive the next estimated incoming current demand; and shift the next estimated incoming current demand to its third output; the plurality of shift latch circuits are configured to: shift in an estimated current demand from its third input; and shift the estimated current demand to its third output; and each summing circuit of the plurality of summing circuits is configured to: receive an estimated current demand on its second input; and subtract the received estimated current demand from the next estimated incoming current demand to generate the next current flow rate on its third output; and the multiplexing circuit configured to pass the next current flow rate on the first input of the plurality of first inputs, to the first output.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
LIU et al. (United States Patent Application Publication US 2017/0103031) teaches handle I/O operations to and from a storage device based on an application running on a host computer.
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