Office Action Predictor
Last updated: April 16, 2026
Application No. 18/626,649

MULTIPLE SUPPLY LEVEL AREA REDUCTION USING ELECTROSTATIC DISCHARGE SHARING

Non-Final OA §102§112
Filed
Apr 04, 2024
Examiner
SREEVATSA, SREEYA
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Skyworks Solutions, INC.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
87%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allow Rate
219 granted / 255 resolved
+17.9% vs TC avg
Minimal +1% lift
Without
With
+1.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
39 currently pending
Career history
294
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
47.6%
+7.6% vs TC avg
§102
35.3%
-4.7% vs TC avg
§112
14.5%
-25.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 255 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-20 are pending in this application. Specification The disclosure is objected to because of the following informalities: Specification paragraph [0093], “720’” should be –720C--. Appropriate correction is required. Claim Objections Claims 1, 4, 6-7, 11, 14 and 16 are objected to because of the following informalities: Claim 1 line 7, “the input node” should be – the first input node--. Similar corrections are required in multiple instances of claims 11, 14. Claim 4 line 3, “the input node of first voltage supply” should be -- the input node of the first voltage supply--. Claim 6 line 4, “an in input node” should be -- an input node--. Similar correction is required in claim 16. Claim 7 line 2, “a voltage reference node” should be –the voltage reference node--. Claim 16 line 3, “a voltage clamp” should be –the voltage clamp--. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 6-8 and 11-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 6 line 4 recites “an input node of one of the plurality of voltage clamps”. It is unclear if “an input node” is different from “a second input node of the voltage clamp” of lines 2-3 of claim 6. As seen in fig.7C, it appears that the above two limitations are referring to the node between 721C and 722C. For the purposes of examination, the above limitation is interpreted as -- the second input node of the voltage clamp--. Claims 7-8 are rejected for the same reasons as stated above for claim 6. Claim 11 line 3 recites “an integrated circuit implemented on the semiconductor substrate”. In fig.4 PMIC 218 is indicated as integrated circuit. It is not clear how PMIC 218 can be on semiconductor substrate 302 of fig.8. For the purpose of examination, the above limitation is interpreted as –a power amplifier implemented on the semiconductor substrate--. Claim 11 line 11 recites “at least some of the integrated circuit”. In fig.4 PMIC 218 is indicated as integrated circuit. It is not clear how PMIC 218 can be on semiconductor substrate 302 of fig.8. For the purpose of examination, the above limitation is interpreted as –at least some of the semiconductor die--. Claims 12-18 are rejected for the same reasons as stated above for claim 11. Claim 16 lines 3-4 recites “an in input node”. It is unclear if this input node is different from “an input node” of lines 2-3. Based on fig.7C, for the purposes of examination, the above limitation is interpreted as –the input node--. Claims 17-18 are rejected for the same reasons as stated above for claim 16. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-5 and 11-15 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Krabbenborg (US 20100220419 A1). Regarding claim 1, Krabbenborg teaches a supply circuit ([0001], a circuit comprising a first supply line, a second supply line) for a radio frequency system ([0055], in class-d audio power amplifier ICs), the supply circuit comprising: a first coupling diode (e.g. diode D1, fig.1 below) coupled between an input node (e.g. node NA, fig.1 below) of a first voltage supply (e.g. voltage at pin VA, fig.4) and a first input node (e.g. node N1, fig.1 below) of a voltage clamp of the supply circuit ([0043], active clamp circuit of FIG. 4) (e.g. circuit comprising transistors MD and MP, fig.4), an output of the first coupling diode being coupled to the first input node of the voltage clamp (e.g. cathode of D1 is connected to node N1, fig.1 below); and a second coupling diode (e.g. diode D3, fig.1 below) coupled between an input node (e.g. node NB, fig.1 below) of a second voltage supply (e.g. voltage at pin VB, fig.4) and the first input node of the voltage clamp (e.g. diode D3 is connected between nodes NB and N1, fig.1 below), an output of the second coupling diode being coupled to the first input node of the voltage clamp (e.g. cathode of D3 is connected to node N1, fig.1 below). PNG media_image1.png 404 522 media_image1.png Greyscale Fig.1: Annotated Fig.4 of prior art Krabbenborg (US 20100220419 A1). Regarding claim 2, Krabbenborg teaches the supply circuit of claim 1 wherein the voltage clamp comprises a plurality of voltage clamps (e.g. plurality of zener diodes and transistors MD and MP, fig.4) coupled in a series connection ([0043], clamp voltage is now determined by the sum of the zener voltages of the zener diodes Z1 to Z3 and the two threshold voltages of transistors M.sub.D and M.sub.P) (it is necessarily true that zener diodes and transistors are connected in series). Regarding claim 3, Krabbenborg teaches the supply circuit of claim 2 wherein the voltage clamp is coupled between the first input node and a voltage reference node (e.g. node NREF, fig.1 above) of the supply circuit (e.g. zener diodes, MD and MP are between N1 and NREF, fig.1 above). Regarding claim 4, Krabbenborg teaches the supply circuit of claim 3 further comprising a first diode (e.g. diode D2, fig.1 above) coupled between the input node of the first voltage supply and the voltage reference node (e.g. D2 is between NA and NREF, fig.1 above), an output of the first diode being coupled to the input node of the first voltage supply (e.g. cathode of D2 is connected to node NA, fig.1 above). Regarding claim 5, Krabbenborg teaches the supply circuit of claim 4 further comprising a second diode (e.g. diode D4, fig.1 above) coupled between the input node of the second voltage supply and the voltage reference node (e.g. D4 is between NB and NREF, fig.1 above), an output of the second diode being coupled to the input node of the second voltage supply (e.g. cathode of D4 is connected to node NB, fig.1 above). Regarding claim 11, Krabbenborg substantially teaches the claim limitations as stated above in claim 1. Krabbenborg further teaches a semiconductor die comprising: a semiconductor substrate ([0055], The invention may be used in all integrated circuits) (it is necessarily true that integrated circuits have a semiconductor substrate); a power amplifier implemented on the semiconductor substrate ([0055], ESD protection voltages are required, e.g. in class-d audio power amplifier ICs); the supply circuit configured to provide electrostatic discharge protection for at least some of the semiconductor die ([0055], ESD protection voltages are required). Regarding claim 12, it is rejected for the same reasons as stated above for claim 2. Regarding claim 13, it is rejected for the same reasons as stated above for claim 3. Regarding claim 14, it is rejected for the same reasons as stated above for claim 4. Regarding claim 15, it is rejected for the same reasons as stated above for claim 5. Allowable Subject Matter Claims 6-10 and 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 6, Krabbenborg (US 20100220419 A1) teaches the supply circuit of claim 5. Krabbenborg does not teach further comprising a third coupling diode, the third coupling diode being coupled between an input node of a third voltage supply and a second input node of the voltage clamp, an output of the third coupling diode being coupled to the second input node of the voltage clamp. Prior art Srivastava (US 9042064 B2), Lien (US 6069782 A), Sithanandam (US 20190319453 A1) and Chen (US 20140029142 A1) have been found to be the closest prior art. However, none of the prior art, taken singly or in combination, teach “a third coupling diode, the third coupling diode being coupled between an input node of a third voltage supply and a second input node of the voltage clamp, an output of the third coupling diode being coupled to the second input node of the voltage clamp.” Claims 7-8 are indicated as allowable, as they depend on allowable claim 6. Regarding claim 9, Krabbenborg (US 20100220419 A1) teaches the supply circuit of claim 2. Krabbenborg does not teach, wherein each voltage clamp of the plurality of voltage clamps has the same clamping voltage. Prior art Srivastava (US 9042064 B2), Lien (US 6069782 A), Sithanandam (US 20190319453 A1) and Chen (US 20140029142 A1) have been found to be the closest prior art. However, none of the prior art, taken singly or in combination, teach “each voltage clamp of the plurality of voltage clamps has the same clamping voltage.” Claim 10 is indicated as allowable, as it depends on allowable claim 9. Regarding claim 16, it is indicated as allowable for the same reasons as stated above for claim 6. Claims 17-18 are indicated as allowable, as they depend on allowable claim 16. Regarding claim 19, it is indicated as allowable for the same reasons as stated above for claim 9. Claim 20 is indicated as allowable, as it depends on allowable claim 19. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SREEYA SREEVATSA whose telephone number is (571)272-8304. The examiner can normally be reached M-F 8am-5pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V Tran can be reached at (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SREEYA SREEVATSA/Primary Examiner, Art Unit 2838 11/22/2025
Read full office action

Prosecution Timeline

Apr 04, 2024
Application Filed
Nov 24, 2025
Non-Final Rejection — §102, §112
Apr 02, 2026
Response Filed

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
87%
With Interview (+1.3%)
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 255 resolved cases by this examiner. Grant probability derived from career allow rate.

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