DETAILED ACTION
This action is responsive to 04/04/2024.
Claims 1-18 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Objections
Claims 3, 5, 7-8, 12, 14, and 16-17 are objected to because of the following informalities:
For claims 3, 5, 12, and 14, change “comprising” to “further comprising” in line 1.
For claims 7 and 16, insert “further comprising” before “defining” in line 1.
For claims 8 and 17, change “the plurality of gate lines are” to “the plurality of gate lines is”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 9-15, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US Pub. 2023/0043192, PCT/CN2021/112692), hereinafter Chen, in view of Zhao et al. (US Pub. 2022/0190074), hereinafter Zhao.
Regarding claim 1, Chen discloses a display panel (see figs. 3-10), comprising a display region (display region 3-see fig. 4 and [0045]), a fan-out region (fan-out wire 13-see fig. 1 and [0045]), and a binding region (bonding electrode 5-see fig. 3 and [0045]), the fan-out region and the binding region being stacked on the display region (see fig. 4), wherein the display region comprises a substrate (a display substrate includes a base 17-see fig. 3 and [0045]), a functional structure layer (signal lines 11-see, for example, fig. 10 with description in [0045] and [0068]), and a first insulation layer stacked sequentially (first insulating layer, which may include a plurality of insulating sublayers-see [0067], [0089], and [0099]), wherein the fan-out region (i.e., region with fan-out wires 13, e.g., fan-out region 130-see fig. 4) and the binding region (i.e., region with bonding electrodes 5-seefig. 4) are stacked on the first insulation layer (see fig. 10); the functional structure layer comprises a plurality of functional lines (signal lines 11-see fig. 10), the fan-out region comprises a plurality of electrical connection lines (i.e., fan-out wires 13), and the binding region comprises a plurality of pin terminals (bonding electrodes 5-see fig. 4); and the plurality of electrical connection lines electrically connect the plurality of functional lines to the plurality of pin terminals in one-to-one correspondence (see fig. 2-each bonding electrode 5 is connected to a corresponding signal line 11 by fan-out line 13 in a one-to-one correspondence).
Chen does not appear to expressly disclose and the binding region being co-planar with the fan-out region.
Zhao is relied upon to teach and the binding region being co-planar with the fan-out region (see, for example, fig. 4 with description in [0065], which teaches that first fan-out traces 81 and second fan-out traces 82 may be mounted on the same layer as binding layer 80).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Zhao with the invention of Chen such that the fan-out region and the binding region are coplanar, as taught by Zhao, in order to prevent the first fan-out traces 81 and the second fan-out traces 82 from being short-circuited with each signal line the first driving layer (see [0065]).
Regarding claim 10, Chen discloses a display panel (see figs. 3-10), comprising a display region (display region 3-see fig. 4 and [0045]), a fan-out region (fan-out wire 13-see fig. 1 and [0045]), and a binding region (bonding electrode 5-see fig. 3 and [0045]), the fan-out region and the binding region being stacked on the display region (see fig. 4), wherein the display region comprises a substrate (a display substrate includes a base 17-see fig. 3 and [0045]), a functional structure layer (signal lines 11-see, for example, fig. 10 with description in [0045] and [0068]), and a first insulation layer stacked sequentially (first insulating layer, which may include a plurality of insulating sublayers-see [0067], [0089], and [0099]), wherein the fan-out region (i.e., region with fan-out wires 13, e.g., fan-out region 130-see fig. 4) and the binding region (i.e., region with bonding electrodes 5-seefig. 4) are stacked on the first insulation layer (see fig. 10); the functional structure layer comprises a plurality of functional lines (signal lines 11-see fig. 10), the fan-out region comprises a plurality of electrical connection lines (i.e., fan-out wires 13), and the binding region comprises a plurality of pin terminals (bonding electrodes 5-see fig. 4); and the plurality of electrical connection lines electrically connect the plurality of functional lines to the plurality of pin terminals in one-to-one correspondence (see fig. 2-each bonding electrode 5 is connected to a corresponding signal line 11 by fan-out line 13 in a one-to-one correspondence).
Chen does not appear to expressly disclose and the binding region being co-planar with the fan-out region.
Zhao is relied upon to teach and the binding region being co-planar with the fan-out region (see, for example, fig. 4 with description in [0065], which teaches that first fan-out traces 81 and second fan-out traces 82 may be mounted on the same layer as binding layer 80).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Zhao with the invention of Chen such that the fan-out region and the binding region are coplanar, as taught by Zhao, in order to prevent the first fan-out traces 81 and the second fan-out traces 82 from being short-circuited with each signal line the first driving layer (see [0065]).
Regarding claims 2 and 11, Chen discloses wherein the plurality of functional lines comprise a plurality of gate lines, a plurality of data lines, a plurality of first power lines, and a plurality of second power lines; the plurality of electrical connection lines comprise first electrical connection lines, second electrical connection lines, third electrical connection lines, and fourth electrical connection lines; the plurality of pin terminals comprise first pin terminals, second pin terminals, third pin terminals, and fourth pin terminals; and each of the first electrical connection lines electrically connects one of the plurality of gate lines to one of the first pin terminals; each of the second electrical connection lines electrically connects one of the plurality of data lines to one of the second pin terminals; each of the third electrical connection lines electrically connects one of the plurality of first power lines to one of the third pin terminals; and each of the fourth electrical connection lines electrically connects one of the plurality of second power lines to one of the fourth pin terminals (see, for example, [0044] and particularly [0070], which discloses that the signal lines 11 include a plurality of signals, such gate lines, data lines, touch signal lines, clock signal lines, a high power voltage line, a low power voltage line, a common signal line, and a floating line, and the bonding electrodes 5 (pins) are electrically coupled to a driving chip (IC) or other signal sources through a flexible printed circuit or a chip film, thereby transmitting electrical signal from a peripheral circuit signal source, such as the driving chip or power supply, to electrical devices in the display substrate (see [0045])).
Regarding claims 3 and 12, Chen discloses further comprising a first side edge, a third side edge opposite the first side edge, a second side edge, and a fourth side edge opposite the second side edge, the first side edge and the third side edge being connected between the second side edge and the fourth side edge (see figs. 1-2).
Chen does not appear to expressly disclose wherein the first pin terminals and the first electrical connection lines are closer to the first side edge than the third side edge; and the second pin terminals, the third pin terminals, the fourth pin terminals, the second electrical connection lines, the third electrical connection lines, and the fourth electrical connection lines are closer to the second side edge than the fourth side edge.
Zhao is further relied upon to teach (as shown in fig. 4, the display has a side 702 (first side) and side 704 (third side) opposite the side 702, and sides 701 and 703 (equated second and fourth side edges) that are opposite each other. As shown in fig. 4, there are pins (in the binding area 80 that are closer to the side 701, and other pins in the binding area 80 that are closer to the side 703).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Zhao with the invention of Chen such that some of the pins are arranged closer to one side of the display and others are arranged closer to another side of the display opposite the one side of the display, as taught by Zhao, which constitutes combining prior art elements according to known methods to yield predictable results (i.e., arranging pins to supply signals to the display).
Regarding claims 4 and 13, Zhao is further relied upon to teach wherein the first pin terminals are connected to the first side edge, and the second pin terminals, the third pin terminals, and the fourth pin terminals are connected to the second side edge (having pins on different sides of the display can be gleaned from fig. 4).
Regarding claims 5 and 14, Chen discloses further comprising a first side edge, a third side edge opposite the first side edge, a second side edge, and a fourth side edge opposite the second side edge, the first side edge and the third side edge being connected between the second side edge and the fourth side edge (see figs. 1-2).
Chen does not appear to expressly disclose wherein the first pin terminals, the second pin terminals, the third pin terminals, the fourth pin terminals, the first electrical connection lines, the second electrical connection lines, the third electrical connection lines, and the fourth electrical connection lines are close to one of the first side edge, the second side edge, the third side edge, and the fourth side edge.
Zhao is further relied upon to teach wherein the first pin terminals, the second pin terminals, the third pin terminals, the fourth pin terminals, the first electrical connection lines, the second electrical connection lines, the third electrical connection lines, and the fourth electrical connection lines are close to one of the first side edge, the second side edge, the third side edge, and the fourth side edge (as shown in fig. 4, the display has a side 702 (first side) and side 704 (third side) opposite the side 702, and sides 701 and 703 (equated second and fourth side edges) that are opposite each other. As shown in fig. 4, there are pins (in the binding area 80 that are closer to the side 701, and other pins in the binding area 80 that are closer to the side 703).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Zhao with the invention of Chen such that some of the pins are arranged closer to one side of the display and others are arranged closer to another side of the display opposite the one side of the display, as taught by Zhao, which constitutes combining prior art elements according to known methods to yield predictable results (i.e., arranging pins to supply signals to the display).
Regarding claims 6 and 15, Chen in view of Zhao does not appear to expressly teach wherein the first pin terminals, the second pin terminals, the third pin terminals, and the fourth pin terminals are connected to one of the first side edge, the second side edge, the third side edge, and the fourth side edge.
However, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to connect any group of pin terminals supplying a given signal to any one of the four sides of the display, which simply constitutes choosing from a finite number of identified, predictable solutions for connecting the pin terminals, with a reasonable expectation of success.
Regarding claims 9 and 18, Chen discloses further comprising a light-emitting element configured to emit light that passes through the substrate and bypasses the binding region (light emitting element 25-see fig. 10).
Claims 7 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Zhao, and further in view of Li et al. (US Pub. 2025/0133825, PCT/CN2022/128764), hereinafter Li825).
Regarding claim 7, Chen in view of Zhao does not appear to expressly teach further comprising, defining a plurality of through holes extending through the first insulation layer, each of the plurality of electrical connection lines being electrically connected to one of the plurality of functional lines through one of the plurality of through holes.
Li825 is relied upon to teach further comprising, defining a plurality of through holes extending through the first insulation layer, each of the plurality of electrical connection lines being electrically connected to one of the plurality of functional lines through one of the plurality of through holes.
further comprising, defining a plurality of through holes extending through the first insulation layer, each of the plurality of electrical connection lines being electrically connected to one of the plurality of functional lines through one of the plurality of through holes (see figs. 14-15 with description in [0070]-data line 101 is connected to data fan-out line 311 through fifth connecting part 705 through at least one ninth via hole 609 penetrating a first insulating layer 02 and second insulating layer 03).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Li825 with the inventions of Chen and Zhao to include a plurality of electrical connection lines coupled to a corresponding functional line via a through hole, as taught by Li825, which constitutes combining prior art elements according to known methods to yield predictable results (i.e., achieving a narrow border through reasonable layout of a fan-out area-see [0002]).
Claims 8 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Zhao, and further in view of Li825, and further in view of Li et al. (US Pub. 2021/0384289), hereinafter Li289.
Regarding claims 8 and 17, Chen discloses wherein the functional structural layer comprises a first metal layer, a second insulation layer, and a second metal layer stacked sequentially, the plurality of gate lines [[are]] is arranged on the first metal layer (see, for example, fig. 10 and [0070], wherein signal line 11 can be a gate lines, and the signal lines 11 are disposed on an interlayer dielectric layer 24. A first planarization layer 26 (second insulation layer) is located on a side of the interlayer dielectric layer 24, and connecting electrodes, e.g., electrodes connecting drain electrode 164 to light emitting element 25, are disposed on the first planarization layer); part of the plurality of through hole extends through the first insulation layer to enable each of the first electrical connection lines to be electrically connected to one of the plurality of gate lines (relay wires 18 connect bonding wire 6 to a corresponding signal line 11-see fig. 10 and [0071] via through holes that extend through the interlayer dielectric layer 24).
Chen in view of Zhao does not appear to expressly disclose part of the plurality of through hole extends through the second insulation layer.
However, having the through hole extend through the second and not the first insulation layer would have been an obvious design choice in view of the teachings of Chen and Zhao, and depending on the location of the electrical connection line relative to a corresponding gate line.
Chen discloses that the signal line 11 is selected from group consisting of a gate line, a data line, a touch signal line, a clock signal line, a high power voltage line, a low power voltage line, a common signal line, and a floating signal line. Therefore, Chen in view of Zhao does not appear to expressly teach and the plurality of data lines, the plurality of first power lines, and the plurality of second power lines are arranged on the second metal layer.
However, having a plurality of data lines and a plurality of power lines disposed on a same layer can be gleaned from the teachings of Li289, in for example fig. 8 with description in [0071], wherein a data line D and power line P are located in a same metal layer (third metal layer M3), while scan lines are disposed located in a same metal layer M1, below the third metal layer M3.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Li289 with the inventions of Chen and Zhao such that data lines and power supply lines are disposed on a same layer above a layer having gate lines, as taught by Li289, which constitutes combining prior art elements according to known methods to yield predictable results.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARDIS F AZONGHA whose telephone number is (571)270-7706. The examiner can normally be reached 10AM-7:00PM.
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/SARDIS F AZONGHA/Primary Examiner, Art Unit 2627
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