DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-9, 13-16, 18-20 are rejected under 35 U.S.C. 102(a)(1)(2) as being anticipated by Gambino (US 2010/0155932 A1, hereinafter, Gambino).
Regarding claim 1: Gambino discloses:
A semiconductor device (Gambino Fig 31, see annotated figure, Figure A, below) comprising:
a plurality of first transistors (field effect transistors 222 [0068]);
a plurality of second transistors stacked on the plurality of first transistors (field effect transistors 122 [0061]);
a first dielectric layer (second insulator layer 220 "comprises a dielectric material such as silicon oxide or silicon nitride" [0070]) between the plurality of first transistors and the plurality of second transistors;
a second dielectric layer (first dielectric material layer 310) between the plurality of first transistors and the plurality of second transistors, wherein the second dielectric layer is stacked on the first dielectric layer;
an interconnect layer ("The through substrate vias 146 and the at least one conductive structure 202 collectively constitute conductive electrical connections between the at least one first semiconductor device and the at least one second semiconductor device" [0096], therefore, structure 202 is the interconnect layer) between the first dielectric layer and the second dielectric layer;
a first interconnect wiring level (substrate-contact level metal interconnect structure 160 [0063] and first metal interconnect structure 180 [0079]) on a first side of a stacked structure comprising the plurality of second transistors stacked on the plurality of first transistors;
a second interconnect wiring level (second metal interconnect structure 260 [0070]) on a second side of the stacked structure opposite the first side;
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and a via (through substrate vias 146, [0096]) electrically connected to and disposed between the first and second interconnect wiring levels, wherein the via is further electrically connected to the interconnect layer (via 146 in contact with and electrically connected to 202 [0096]).
Figure A: Annotated Fig 31 from Gambino US 2010/0155932 A1
Regarding claim 2, Gambino discloses, the semiconductor device of claim 1, wherein the interconnect layer comprises one of ruthenium, molybdenum and tungsten ([0085] "The at least one conductive structure 202 is formed… A conductive material is deposited into the at least one via hole…. The conductive material may be a doped semiconductor material such as doped polysilicon or a doped silicon-containing alloy, or may be a metallic material such as W, Cu, Al, TaN, TiN, Ta, Ti, etc." therefore, the interconnect layer's conductive material as disclosed in Gambino is not limited and covers the limitations of claim 2).
Regarding claim 3, Gambino discloses, the semiconductor device of claim 1, wherein the via contacts the interconnect layer at a side surface of the interconnect layer. Referring to Gambino Fig 27, the conductive wiring structure 203 that laterally contacts the conductive structure 202 may be view as an extension of the via 146 in Fig 31. In Fig 31, Gambino labels the whole conductive structure 202 as one item; however, in discussion of Fig 27, "at least one conductive structure 202 and the at least one conductive wiring structure 203 has the same composition as the conductive fin 302 {W, Al, Ti, Ta, Co, Ni, TaN, TiN, etc. [0098]}, and has the same structural and functional characteristics as the as least one conductive structure 202…" [0108]. This specifically defines 203 as a conductive wiring element, which may be made of the same materials as the conductive through-substrate vias 146. Therefore, conductive wiring feature 203, is structurally, and functionally, an extension of the via 146, which contacts the interconnect layer (202) at a side surface and continues down to electrically connect to the second interconnect wiring layer 260.
Regarding claim 4, Gambino discloses, the semiconductor device of claim 1, wherein the via is electrically connected to the first and second interconnect wiring levels through respective first and second contacts contacting respective opposite surfaces of the via (Fig 26 clearly shows how the via 146 is electrically connected to the first and second interconnect wiring levels through the contact with "first metal wiring structures 168" [0114] on the first side and through contact with the source and drain regions 224 to connect to the second interconnect wiring level 260 on the opposite side).
Regarding claim 5, Gambino discloses, the semiconductor device of claim 1, wherein the first side of the stacked structure is on a frontside of the semiconductor device (Fig 1 first structure 99), and the second side of the stacked structure is on a backside of the semiconductor device (second structure 199).
Regarding claim 6, Gambino discloses, the semiconductor device of claim 1, wherein the via (Fig 30 via element 146) is disposed through the first (220) and second (310) dielectric layers.
Regarding claim 7, Gambino discloses, the semiconductor device of claim 1, further comprising an additional via (additional via 146 shown in Fig 26) disposed between the first interconnect wiring level (Fig 26 interconnect wiring structures 160 and 180) and the interconnect layer (Fig 26 conductive fin elements 302 [0108] which is the interconnect layer of the Fig 26 embodiment), wherein the additional via is electrically connected to the first interconnect wiring level and to the interconnect layer (in Fig 26, the additional via is not shown to be electrically connected to the interconnect layer because Fig 26 displays a different interconnect layer structure (the fins 302 without the structure 202) than Fig 31; however, Fig 31 shows the electrical connection between via 146 and interconnect layer 202, and [0089] describes the formation of through-substrate via holes, indicating that multiple vias 146 may be formed simultaneously and exist throughout different embodiments of the disclosed invention. The additional via in Fig 26 may also exist in the embodiment of Fig 31).
Regarding claim 8, Gambino discloses, the semiconductor device of claim 7, wherein a bottom surface of the additional via contacts a top surface of the interconnect layer (the additional via 146 in Fig 26 may exist in the embodiment of Fig 31, and would mirror the structure of the first and left-most via 146 which contacts a top surface of the interconnect layer 202 in Fig 31).
Regarding claim 9, Gambino discloses, the semiconductor device of claim 7, wherein the additional via is disposed through the second dielectric layer (Fig 26 additional via 146 on the right, disposed through the second dielectric layer 310).
Regarding claim 13, Gambino discloses, the semiconductor device of claim 1, wherein:
the plurality of first transistors and the plurality of second transistors are respectively parts of at least a first complementary metal-oxide semiconductor device and a second complementary metal-oxide semiconductor device ([0061] "the at least one first semiconductor device may include a first field effect transistor having a body region 122 and source and drain regions 124…" and [0068] describes the second field effect transistors. It is well-known and beyond dispute in the art that complementary metal-oxide semiconductor devices fall under the category of field effect transistors. See MPEP 2144.03);
the first interconnect wiring level comprises at least one of a first power rail and a first plurality of signal wires (In the instant application, no distinction between the structure of power rails and signal wires is made. [0093] describes, "one or more of the first, second, third, and fourth frontside interconnects … {and backside interconnects} includes a power rail and/or signal wires". Therefore, it can be seen in Gambino Fig 26 or Fig 31 that both first interconnect wiring level 160 and 180 and the second interconnect wiring level 260 include power rails and signal wires that may draw power and/or signal from the "Controlled Collapse Chip Connection (C4) pads" which "may then be bonded to a packaging substrate or yet another semiconductor chip" [0081]);
and the second interconnect wiring level comprises at least one of a second power rail and a second plurality of signal wires (see discussion of first power rail and a first plurality of signal wires above. The same structure is shown for the second interconnect wiring level 260 in Fig 26 and Fig 31).
Regarding independent claim 14, Gambino discloses, a semiconductor device comprising:
a first device layer ("second semiconductor substrate 240 including at least one second semiconductor device" [0068], see Fig 31);
a second device layer stacked on the first device layer ("first semiconductor substrate 140 including at least one first semiconductor device" [0061], see Fig 31);
a bonding dielectric layer between the first device layer and the second device layer ("second dielectric layer 210 comprises a bonding material that may be employed for bonding purposes" [0094]);
an additional dielectric layer between the first device layer and the second device layer, wherein the additional dielectric layer is stacked on the bonding dielectric layer (dielectric material layer 310) ;
an interconnect layer between the bonding dielectric layer and the additional dielectric layer (Fig 31 conductive elements 202 and 302);
a first interconnect wiring level on a first side of a stacked structure comprising the second device layer stacked on the first device layer (160 and 180);
a second interconnect wiring level on a second side of the stacked structure opposite the first side (260);
and a via electrically connected to and disposed between the first and second interconnect wiring levels, wherein the via is further electrically connected to the interconnect layer (146).
Regarding claim 15, Gambino discloses, the semiconductor device of claim 14, wherein: the via contacts the interconnect layer at a side surface of the interconnect layer; and the via is disposed through the bonding and additional dielectric layers. The following interpretation of Gambino Figs 27 and 31 mirrors the discussion of claim 3 above. Referring to Gambino Fig 27, the conductive wiring structure 203 that laterally contacts the conductive structure 202 may be view as an extension of the via 146 in Fig 31. In Fig 31, Gambino labels the whole conductive structure 202 as one item; however, in discussion of Fig 27, "at least one conductive structure 202 and the at least one conductive wiring structure 203 has the same composition as the conductive fin 302 {W, Al, Ti, Ta, Co, Ni, TaN, TiN, etc. [0098]}, and has the same structural and functional characteristics as the as least one conductive structure 202…" [0108]. This specifically defines 203 as a conductive wiring element, which may be made of the same materials as the conductive through-substrate vias 146. Therefore, conductive wiring feature 203, is structurally, and functionally, an extension of the via 146, which contacts the interconnect layer (202) at a side surface and continues down to electrically connect to the second interconnect wiring layer 260. The additional via 146 is disposed through the bonding dielectric (210) and the additional dielectric layer (310).
Regarding claim 16, Gambino discloses, the semiconductor device of claim 14, further comprising an additional via disposed through the additional dielectric layer and between the first interconnect wiring level and the interconnect layer, wherein the additional via is electrically connected to the first interconnect wiring level and to the interconnect layer (see Fig 26 additional via 146 on the right side of the figure may also be added to the embodiment of Fig 31 where it would be electrically connected to the interconnect wiring level 160 and 180 and also the interconnect layer 202 just like the first via).
Regarding independent claim 18, Gambino discloses, a semiconductor device (Fig 31) comprising: a first device layer (240); a second device layer stacked on the first device layer (140); a first dielectric layer (220) between the first device layer and the second device layer; a second dielectric layer (310) between the first device layer and the second device layer, wherein the second dielectric layer is stacked on the first dielectric layer; an extension layer (conductive elements 202) between the first dielectric layer and the second dielectric layer (The extension layer in the instant application appears to be the same structure as the interconnect layer 145 in Figs 7 & 8; however, it has been split into separate sections to become the extension layer pieces 146-1, 146-2, and 146-3 seen in Fig 9 where "the first and second extension layers, … , are isolated from each other by a portion of the second bonding dielectric layer 136" [0096].), wherein the first dielectric layer contacts at least two surfaces of the extension layer (220 contacts the bottom surface of 202 and both sides of the extended area that protrudes from 202 (which is labeled 203 in Fig 27 and then all compiled into element 202 in Fig 31) and contacts the first device layer 240); a first interconnect wiring level (160 and 180) on a first side of a stacked structure comprising the second device layer stacked on the first device layer; a second interconnect wiring level (260) on a second side of the stacked structure opposite the first side; and a via (146) electrically connected to and disposed between the first and second interconnect wiring levels, wherein the via contacts the extension layer (146 contacts 202).
Regarding claim 19, Gambino discloses, the semiconductor device of claim 18, wherein the extension layer comprises one of ruthenium, tungsten and one or more carbon nanotubes. ([0085] "The at least one conductive structure 202 is formed… A conductive material is deposited into the at least one via hole…. The conductive material may be a doped semiconductor material such as doped polysilicon or a doped silicon-containing alloy, or may be a metallic material such as W, Cu, Al, TaN, TiN, Ta, Ti, etc" therefore, the interconnect layer's conductive material as disclosed in Gambino is not limited and could include conductive materials such as ruthenium, tungsten, and one or more carbon nanotubes).
Regarding claim 20, Gambino discloses, the semiconductor device of claim 18, wherein the via contacts the extension layer at a side surface of the extension layer. The following interpretation of Gambino Figs 27 and 31 mirrors the discussion of claims 3 and 15 above. Referring to Gambino Fig 27, the conductive wiring structure 203 that laterally contacts the conductive structure 202 may be viewed as an extension of the via 146 in Fig 31. In Fig 31, Gambino labels the whole conductive structure 202 as one item; however, in discussion of Fig 27, "at least one conductive structure 202 and the at least one conductive wiring structure 203 has the same composition as the conductive fin 302 {W, Al, Ti, Ta, Co, Ni, TaN, TiN, etc. [0098]}, and has the same structural and functional characteristics as the as least one conductive structure 202…" [0108]. This specifically defines 203 as a conductive wiring element, which may be made of the same materials as the conductive through-substrate vias 146. Therefore, conductive wiring feature 203, is structurally, and functionally, an extension of the via 146, which contacts the interconnect layer (202) at a side surface and continues down to electrically connect to the second interconnect wiring layer 260.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10-12, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Gambino in view of Majhi et al. (US 2023/0197612 A1, hereinafter Majhi).
Regarding claim 10: The semiconductor device of claim 1, further comprising an additional via disposed between the second interconnect wiring level and the interconnect layer, wherein the additional via is electrically connected to the first interconnect wiring level and to the interconnect layer. Gambino discloses the semiconductor device of claim 1, but Gambino fails to disclose an additional via disposed between the second interconnect wiring level and the interconnect layer. However, in the same field of endeavor, Majhi discloses a more detailed backside (or second-side) interconnect structure that connects to a frontside interconnect structure, a device layer, and an interconnect layer. Majhi Fig 1A discloses a second backside interconnect structure 140 that contains interconnect features (e.g. conductive vias, [0038]) 144a and 144b. Majhi's interconnect layer includes conductive vias 130 which connect the frontside interconnect structure 110 to the first backside interconnect structure 120 through the device layer 106. Therefore, Majhi's conductive vias 144a and 144b both meet the limitations of an additional via (144a or 144b) disposed between the second interconnect wiring level (backside interconnect structures 120 and 140) and the interconnect layer (interconnect features 130 within the device layer 106), wherein the additional via is electrically connected to the first interconnect wiring level (frontside interconnect structure 110) and to the interconnect layer. Before the effective filing date of the claimed invention, it would have been obvious to one having ordinary skill in the art to modify the original structure of Gambino with the backside interconnect structure and vias of Majhi "to circumvent congestion of frontside interconnects due to power and signal routing" while scaling downward such semiconductor devices [Majhi 0002].
Regarding claim 11, Gambino as modified by Majhi discloses, the semiconductor device of claim 10, wherein a top surface of the additional via (Majhi Fig 1A interconnect features 144a or 144b) contacts a bottom surface of the interconnect layer (contacts bottom of interconnect features 130b, or Gambino Fig 31 interconnect layer 202 as modified to include backside interconnect structure of Majhi).
Regarding claim 12, Gambino as modified by Majhi discloses, the semiconductor device of claim 10, wherein the additional via is disposed through the first dielectric layer (Majhi Fig 1A "interconnect layer 122 of the first backside interconnect structure 120 comprise dielectric material" [0041]).
Regarding claim 17, Gambino as modified by Majhi discloses, the semiconductor device of claim 14 (Gambino Fig 31), further comprising an additional via (Gambino modified by Majhi to include an additional via on the “bottom side”, such as the structure of backside interconnect structure 140 with the interconnect vias 144a and 144b) disposed through the bonding dielectric layer (Gambino’s bonding dielectric layer: "second dielectric layer 210 comprises a bonding material that may be employed for bonding purposes" [0094]) and between the second interconnect wiring level (Gambino 260) and the interconnect layer (Gambino 202), wherein the additional via (Majhi 144a or 144b added to Gambino Fig 31) is electrically connected to the first interconnect wiring level (Gambino 160 and 180) and to the interconnect layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA MICKEY whose telephone number is (571)270-3109. The examiner can normally be reached M-F, 8am to 5pm ET.
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/TERESA N MICKEY/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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