Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim (s) 1-4, 6-9, 15-18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu (US 2017/0103943 A1) in view of Kawai (US 2022/0369457 A1).
Regarding claim 1,Hu discloses, Fig.8A, a wiring substrate (61D,62D), comprising: a first build-up part (61D) comprising an insulating layer (61D) and a conductor layer (see conductors 61T); and a second build-up part (62D) comprising an insulating layer (62D) and a conductor layer (62T) and formed such that the first build-up part (61D) is laminated on the second build-up part (62D), a minimum wiring width of wirings in the conductor layer (61T) of the first build-up part is smaller than a minimum wiring width of wirings in the conductor layer (see 62T) of the second build-up part, and a minimum inter-wiring distance of the wirings in the conductor layer of the first build-up part (see spacing between 61T and another 61T) is smaller than a minimum inter-wiring distance of the wirings in the conductor layer of the second build-up part (see spacing between 62T and another 62T).
Hu is silent with respect to wherein the first build-up part is formed such that the conductor layer includes a conductor pattern comprising a first metal layer, a second metal layer laminated on the first metal layer, and a third metal layer laminated on the second metal layer, a width of the first metal layer is larger than a width of the second metal layer, and a width of the third metal layer is larger than the width of the first metal layer.
Kawai disclose a conductor layer (1;Fig.1) includes a conductor pattern (40,34b,54;Fig.1) comprising a first metal layer (40;Fig.1), a second metal layer (42;Fig.1) laminated on the first metal layer (40), and a third metal layer (52 or 54) laminated on the second metal layer (42) , a width of the first metal layer (see width of 40) is larger than a width of the second metal layer (see width of 42), and a width of the third metal layer (see width of 54) is larger than the width of the first metal layer (40).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Kawai to modify the conductor layer of Hu in order to provide a secure electrical contact to an electrical device to perform various circuit operations.
Regarding claim 2, Hu discloses wherein the conductor layer in the first build-up part is formed such that the third metal layer of the conductor pattern includes a plating film (see 54) and that each of the first metal layer and the second metal layer includes a seed layer (see 40 and 34b) comprising a film.
It is noted that the limitations of the method steps recited in claim 2 “electrolytic plating” and “plating” are process limitations in a product claim and is treated in accordance with MPEP 2113. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process". In re Thorpe, 777Fo 2d 695,698 USPQ 964, 966 (Fed. Cir.1985). See also MPEP 2113.
Regarding claim 3 and 17, Hu discloses the claimed invention except for wherein the conductor layer in the first build-up part is formed such that the minimum wiring width of the wirings is 3 μm or less and that the minimum inter-wiring distance of the wirings is 3 μm or less. It would have been obvious to one of ordinary skill in the art at the time the invention was made to use wherein the conductor layer in the first build-up part is formed such that the minimum wiring width of the wirings is 3 μm or less and that the minimum inter-wiring distance of the wirings is 3 μm or less in order to perform various circuit operations, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ233.
Regarding claim 4 and 18, Hu discloses the claimed invention except for wherein the wherein the conductor layer in the first build-up part is formed such that an aspect ratio of the wirings is in a range of 2.0 to 4.0.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to use wherein the conductor layer in the first build-up part is formed such that an aspect ratio of the wirings is in a range of 2.0 to 4.0 in order to perform various circuit operations, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ233.
Regarding claim 6 and 20, Hu discloses a third build-up part (see 65;Fig.8A)laminated on the second build-up part (62D) on an opposite side with respect to the first build-up part (61D) and comprising an insulating layer (65), a conductor layer (67;Fig.8B) and a via conductor (63).
Regarding claim 7, Hu discloses wherein the third build-up part is formed such that the insulating layer includes a core material (see 65 made of an insulating material).
Regarding claim 8, Hu discloses, wherein the first build-up part has a surface configured to mount a component (see mounted component 662; Fig.8B).
Regarding claim 9, Hu discloses the claimed invention except for wherein the first build-up part is formed such that the insulating layer has a surface having an arithmetic mean roughness Ra in a range of 0.02 μm to 0.06 μm.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to use wherein the first build-up part is formed such that the insulating layer has a surface having an arithmetic mean roughness Ra in a range of 0.02 μm to 0.06 μm in order to perform various circuit operations, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ233.
Regarding claim 15, Hu discloses the claimed invention except for wherein the conductor pattern of the conductor layer in the first build-up part is formed such that a total thickness of the first metal layer and the second metal layer is in a range of 0.02 μm to 1 μm.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to use a total thickness of the first metal layer and the second metal layer is in a range of 0.02 μm to 1 μmin order to perform various circuit operations, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ233.
Regarding claim 16, Hu discloses the claimed invention except for the conductor pattern of the conductor layer in the first build-up part is formed such that a thickness of the first metal layer is in a range of 0.01 μm to 0.5 μm.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to use a thickness of the first metal layer is in a range of 0.01 μm to 0.5 μm in order to perform various circuit operations, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ233.
Claim (s) 5 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu (US 2017/0103943 A1) in view of Kawai (US 2022/0369457 A1) as applied to claim 1 and claim 2 above, and further in view of Kajihara (US 2017/0309558 A1).
Regarding claim 5 and 19, Hu fails to specifically disclose the first build-up part is formed such that the conductor layer has a polished surface.
Kajihara discloses a conductor layer has a polished surface (see 36; [0041]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Kajihara to modify the conductor of Hu in order to reduce intense electrical fields at sharp points and provide more consistent conductivity.
Claim (s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu (US 2017/0103943 A1) in view of Kawai (US 2022/0369457 A1) as applied to claim 1 above, and further in view of Fu et al. (US 2021/0066144 A1) hereinafter Fu.
Regarding claim 13, Hu fails to specifically disclose wherein the conductor pattern of the conductor layer in the first build-up part is formed such that the first metal layer includes an alloy comprising copper and an element other than copper and that the second metal layer is formed of substantially pure copper.
Fu discloses a first metal layer (270a;Fig.6) includes an alloy comprising copper and an element other than copper(see [0053]) and a second metal layer (250;Fig.6) is formed of substantially pure copper (250 can be made of copper ;[0052]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the material as shown by Fu to modify the first metal layer and second metal layer of Hu in order to provide superior electrical conductivity to perform various circuit operations.
Regarding claim 14, a modified Hu fails to specifically disclose wherein the first metal layer in the conductor pattern is formed such that a weight of the copper in the alloy is 90% or more of a total weight of the alloy.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to have the first metal layer in the conductor pattern is formed such that a weight of the copper in the alloy is 90% or more of a total weight of the alloy in order to provide superior electrical conductivity to perform various circuit operations, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ233.
Allowable Subject Matter
Claims 10-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for allowance:
Regarding claim 10, The prior art of record neither anticipates norrenders obvious the claimed subject matter of the instant application as a whole eithertaken alone or in combination, in particular, prior art of record does not teach" wherein the conductor layer in the first build-up part is formed such that a width of the conductor pattern is smallest at a boundary portion between the second metal layer and the third metal layer " in combination with the remaining limitations of the claim 1.
Regarding claim 11, The prior art of record neither anticipates norrenders obvious the claimed subject matter of the instant application as a whole eithertaken alone or in combination, in particular, prior art of record does not teach" wherein the conductor pattern of the conductor layer in the first build-up part is formed such that a side surface of the third metal layer has a tapered portion that is more inclined toward an inner side of the conductor pattern on a second metal layer side and that inclination of the tapered portion from a surface of the insulating layer is smaller than inclination of a side surface of the first metal layer and the second metal layer from the surface of the insulating layer " in combination with the remaining limitations of the claim 1.
Regarding claim 12, The prior art of record neither anticipates norrenders obvious the claimed subject matter of the instant application as a whole eithertaken alone or in combination, in particular, prior art of record does not teach" wherein the first build-up part is formed such that the insulating layer includes resin and inorganic particles and that the inorganic particles includes inorganic particles having sizes of 1.0 μm or less and at least partially positioned beyond an outer edge of the third metal layer toward the first metal layer and the second metal layer" in combination with the remaining limitations of the claim 1.
Therefore, prior art of record neither anticipates nor renders obvious the instantapplication claimed invention as a whole either taken alone or in combination.
Any comments considered necessary by applicant must be submitted no laterthan the payment of the issue fee and, to avoid processing delays, should preferablyaccompany the issue fee. Such submissions should be clearly labeled "Comments onStatement of Reasons for Allowance."
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETE LEE whose telephone number is (571) 270-5921. The examiner can normally be reached on Monday-Friday (2nd & 4th Friday Off). If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Timothy Dole can be reached at (571) 272-2229 The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/PETE T LEE/Primary Examiner, Art Unit 2848