Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-17 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-15 of copending Application No. 19/050,750 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because:
Instant App. 18/626,995
Reference App. 19/050,750
Claim 1.
A switching driver circuit for driving a load comprising: first and second output nodes for outputting a differential drive signal for driving the load; a driver switch network operable in a plurality of different switch states, wherein, in each switch state, each of the first and second output nodes is connected to a respective one of at least a first switching voltage, a second switching voltage and an intermediate switching voltage, wherein the intermediate switching voltage is a voltage between the first and second switching voltages and is provided by a driver capacitance that can be selectively connected to each of the first and second output nodes, and a controller configured to control the driver switch network to operate in a sequence of said switch states to generate said differential drive signal based on an input signal; wherein the controller is configured such that operation of driver switch network in said sequence of switch states to generate said differential drive signal provides voltage regulation of the intermediate voltage provided by said driver capacitance.
Claim 1.
A switching driver circuit for driving a load comprising: first and second output nodes for outputting a differential drive signal for driving the load via a filter arrangement comprising a series inductance; first and second supply nodes configured to receive first and second supply voltages respectively; an intermediate voltage node configured to receive an intermediate voltage provided by a driver capacitance, the intermediate voltage being at a voltage level between the first and second supply voltages; a driver switch network configured such that each of the first and second output nodes can be selectively connected to a respective selected one of each of the first supply node, the second supply node and the intermediate voltage node; a controller configured to control the driver switch network to operate in a sequence of said switch states to generate said differential drive signal based on an input signal; wherein the controller is configured such that operation of driver switch network in said sequence of switch states to generate said differential drive signal regulates the intermediate voltage provided by said driver capacitance.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-8, 13, & 18-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites the limitation "the first voltage" in line 1 and “the second voltage” in line 2. There is insufficient antecedent basis for these limitations in the claim. For examination purposes, examiner has interpreted “the first voltage” to read “the first switching voltage” and “the second voltage” to read “the second switching voltage”.
By virtue of their dependency on claim 6, claims 7-8 are also rejected.
Claim 13 recites the limitation “a first set of three switches” in line 6. The claim, as written, is unclear because a first set of three switches was previously introduced in the claim. For examination purposes, examiner has interpreted “a first set of three switches” to read “a second set of three switches”.
Claim 18 recites the limitation “driver switch network” in the 3rd to last line. The claim, as written, is unclear because the switch network has been previously introduced as the “network of switches”. For examination purposes, examiner has interpreted “driver switch network” to read “said network of switches”.
By virtue of its dependency on claim 18, claim 19 is also rejected.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-13 & 18-20 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Mallinson (US 2022/0399860 A1).
Regarding claim 1, Mallinson discloses, in figure 3, a switching driver circuit for driving a load comprising:
first and second output nodes for outputting a differential drive signal for driving the load differential signal driven across output nodes to load 102);
a driver switch network (switch 104, 106, 108, 110, 312, 314) operable in a plurality of different switch states (open/closed), wherein, in each switch state, each of the first and second output nodes is connected to a respective one of at least a first switching voltage, a second switching voltage and an intermediate switching voltage (Para [0053], “States (i.e., configurations) 1 and 9 in FIG. 4 provide relative voltages of +2 and −2, respectively, i.e., +V.sub.CC and −V.sub.CC. There are now three states, states 4, 5 and 6, which provide zero voltage…And there are now four states that produce relative voltages of ±1, i.e., ±½ V.sub.CC…states 2 and 3 provide a relative voltage of +1 and states 7 and 8 provide a relative voltage of −1”), wherein the intermediate switching voltage is a voltage between the first and second switching voltages (1/2 V.sub.CC which is a voltage between the first switching voltage of +V.sub.CC and the second switching voltage ground) and is provided by a driver capacitance that can be selectively connected to each of the first and second output nodes (Para [0061], “The voltage of C1 will be near the midpoint of 1, i.e., ½ V.sub.CC”…charge on capacitor C1 supplied as ½ V.sub.CC), and
a controller configured to control the driver switch network to operate in a sequence of said switch states to generate said differential drive signal based on an input signal (Para [0028], “a digital signal processor controls the switches”…to vary according to the switch state);
wherein the controller is configured such that operation of driver switch network in said sequence of switch states to generate said differential drive signal provides voltage regulation of the intermediate voltage provided by said driver capacitance (Para [0055], “There is similarly a pair of states, states 7 and 8 in FIG. 4, that provide a relative voltage of −1, again with state 6 charging capacitor C1 and state 7 discharging it. The buck regulator control loop can similarly select between these two states to ensure that capacitor C1 is at a relative voltage of +1”).
Regarding claim 2, Mallinson discloses the switching driver circuit of claim 1, and continues to disclose, in figures 3 & 4, wherein operation in said switch states results in a load current to the load and wherein the controller is configured such that, for at least some values of differential drive signal, the sequence of switch states includes at least one instance of a switch state in which the driver capacitance is charged by the load current and at least one instance of a switch state in which the driver capacitance is discharged by the load current (Para [0054], “capacitor C1 is at a relative voltage of 1 (i.e., half the bridge voltage V.sub.CC), in states 2 and 3 it may be seen that there is one state, state 2, in which the relative voltage of +1 charges capacitor C1, and another state, state 3, in which the relative voltage of +1 discharges capacitor C1”).
Regarding claim 3, Mallinson discloses the switching driver circuit of claim 2, and continues to disclose, in figures 3 & 4, wherein a differential output voltage between the first and second output nodes is the same in the switch state in which the driver capacitance is charged by the load current as in the switch state in which the driver capacitance is discharged by the load current (Para [0054], “capacitor C1 is at a relative voltage of 1 (i.e., half the bridge voltage V.sub.CC), in states 2 and 3 it may be seen that there is one state, state 2, in which the relative voltage of +1 charges capacitor C1, and another state, state 3, in which the relative voltage of +1 discharges capacitor C1”…both at the +1 voltage state).
Regarding claim 4, Mallinson discloses the switching driver circuit of claim 2, and continues to disclose, in figures 3 & 4, the controller is configured such that the load current that flows during the at least one instance of the switch state in which the driver capacitance is charged by the load current substantially matches the load current that flows during the at least one instance of the switch state in which the driver capacitance is discharged by the load current (Para [0054], “capacitor C1 is at a relative voltage of 1 (i.e., half the bridge voltage V.sub.CC), in states 2 and 3 it may be seen that there is one state, state 2, in which the relative voltage of +1 charges capacitor C1, and another state, state 3, in which the relative voltage of +1 discharges capacitor C1”…both at the +1 voltage).
Regarding claim 5, Mallinson discloses the switching driver circuit of claim 2, and continues to disclose, in figures 3 & 4, the controller is configured such that a total duration in the switching cycle of the at least one instance of the switch state in which the driver capacitance is charged by the load current is the same as the total duration in the switching cycle of the at least one instance of the switch state in which the driver capacitance is discharged by the load current (Para [0061], “equal time spend in the charge states 2 and 6 and the discharge states 3 and 7”).
Regarding claim 6, as best understood based the on 35 U.S.C. 112(b) rejection made above, Mallinson discloses the switching driver circuit of claim 2, and continues to disclose, in figures 3 & 4, wherein the first switching voltage is a first supply voltage and the second voltage is a second supply voltage (Vcc and ground).
Regarding claim 7, Mallinson discloses the switching driver circuit of claim 6, and continues to disclose, in figures 3 & 4, wherein the first supply voltage has a value V (Vcc), the second supply voltage is ground (Gnd) and the intermediate voltage has a value equal to V/2 (1/2 Vcc).
Regarding claim 8, Mallinson discloses the switching driver circuit of claim 7, and continues to disclose, in figures 3 & 4, wherein:
the switch state in which the driver capacitance is charged by the load current comprises a switch state in which one of the first and second output nodes is connected to the first supply voltage V and the other of the first and second output nodes is connected to the driver capacitance at the intermediate voltage V/2 (switch state 2 defines the first output node connected to the supply voltage Vcc via switch 104 and the second output node connected to capacitor C1 via switch 314); and
the switch state in which the driver capacitance is discharged by the load current comprises a switch state in which said one of the first and second output nodes is connected to the driver capacitance at the intermediate voltage V/2 and said other of the first and second output nodes is connected to the second voltage at ground (switch state 3 defines the first output node connected to capacitor C1 via switch 312 and the second output node connected to Gnd via switch 110).
Regarding claim 9, Mallinson discloses the switching driver circuit of claim 1, and continues to disclose, in figures 3 & 4, wherein the driver capacitance comprises a driver capacitor connected, in use, between first and second capacitor nodes (opposite sides of capacitor C1), wherein the first capacitor node can be selectively connected to each of the first and second output nodes and the second capacitor node is connected to a defined reference voltage (first capacitor node selectively connected to output nodes via switches 312, 314 and connected to Gnd via the second capacitor node).
Regarding claim 10, Mallinson discloses the switching driver circuit of claim 9, and continues to disclose, in figures 3 & 4, wherein said defined reference voltage is one of the first and second voltages (reference voltage Gnd).
Regarding claim 11, Mallinson discloses the switching driver circuit of claim 9, and continues to disclose, in figures 3 & 4, wherein said defined reference voltage is ground (reference voltage Gnd).
Regarding claim 12, Mallinson discloses the switching driver circuit of claim 9, and continues to disclose, in figures 3 & 4, wherein said driver capacitor is the only capacitor to which the first and second output nodes may be connected (capacitor C1 is the only capacitor).
Regarding claim 13, as best understood based on the 35 U.S.C. 112(b) rejection made above, Mallinson discloses the switching driver circuit of claim 9, and continues to disclose, in figures 3 & 4, wherein the driver switch network comprises, for each of the first and second output nodes:
a first set of three switches for selectively connecting a first common node to the first switching voltage, to the intermediate switching voltage and to the relevant output node respectively (switches 104, 106, 312 for left-side connections); and
a first set of three switches for selectively connecting a second common node to the second switching voltage, to the intermediate switching voltage and to the relevant output node respectively (switches 108, 110, 314 for right-side connections);
wherein the controller is configured such that in a switch state where an output node is connected to the intermediate switching voltage (states 2, 3, 7, & 8), the relevant switches of both the first and second sets of three switches are controlled to be on (relevant switches of both switch sets are controlled based on the state, see figure 4).
Regarding claim 18, as best understood based on the 35 U.S.C. 112(b) rejection made above, Mallinson discloses, in figure 3, a multi-level switching driver circuit for driving a load connected between first and second output nodes with a differential drive signal (differential signal driven across output nodes to load 102), the multi-level switching driver circuit comprising:
first and second supply nodes for receiving first and second supply voltages (Vcc and Gnd);
first and second capacitor nodes for connection, in use, to a driver capacitor (opposite ends of capacitor C1);
a network of switches (switch 104, 106, 108, 110, 312, 314) configured to selectively connect each of the first and second output nodes to a respective one of the first supply node, the second supply node or the first capacitor node (Para [0053], “States (i.e., configurations) 1 and 9 in FIG. 4 provide relative voltages of +2 and −2, respectively, i.e., +V.sub.CC and −V.sub.CC. There are now three states, states 4, 5 and 6, which provide zero voltage…And there are now four states that produce relative voltages of ±1, i.e., ±½ V.sub.CC…states 2 and 3 provide a relative voltage of +1 and states 7 and 8 provide a relative voltage of −1”); and
a controller for controlling the network of switches in a sequence of switch states to generate said differential drive signal (Para [0028], “a digital signal processor controls the switches”…to vary according to the switch state);
wherein operation of said network of switches in said sequence of switch states to generate said differential drive signal provides charge balancing of the driver capacitor (Para [0055], “There is similarly a pair of states, states 7 and 8 in FIG. 4, that provide a relative voltage of −1, again with state 6 charging capacitor C1 and state 7 discharging it. The buck regulator control loop can similarly select between these two states to ensure that capacitor C1 is at a relative voltage of +1”).
Regarding claim 19, Mallinson discloses the multi-level switching driver circuit of claim 18, and continues to disclose, in figures 3 & 4, wherein the second capacitor node is connected to a defined reference voltage (opposite end of capacitor C1 is connected to Gnd).
Regarding claim 20, Mallinson discloses, in figure 3, a multi-level switching driver circuit for driving a load in a bridge-tied-load configuration comprising:
first and second output nodes for connection, in use, to the load (separate output connections to load 102);
first and second capacitor nodes for connection, in use, to a driver capacitor (opposite ends of capacitor C1), wherein the first capacitor node can be selectively connected to each of the first and second output nodes by a switch network and the second capacitor node is connected to a defined reference voltage (switches 312, 314 selectively connect each of the first and second output nodes to the first capacitor node of capacitor C1 and the opposite end of capacitor C1 is connected to Gnd); and
a controller configured to control the multi-level switching driver circuit to generate a differential drive signal across the load based on an input signal (Para [0053], “States (i.e., configurations) 1 and 9 in FIG. 4 provide relative voltages of +2 and −2, respectively, i.e., +V.sub.CC and −V.sub.CC. There are now three states, states 4, 5 and 6, which provide zero voltage…And there are now four states that produce relative voltages of ±1, i.e., ±½ V.sub.CC…states 2 and 3 provide a relative voltage of +1 and states 7 and 8 provide a relative voltage of −1”…controlled by a digital signal processor), wherein the controller is configured, for at least some values of differential driving signal to operate in a switching cycle of states that includes (states 1 to 9):
a first state in which the first capacitor node is connected to one of the first and second output nodes and is charged by a current flowing via that one of the first and second output nodes (Para [0055], “There is similarly a pair of states, states 7 and 8 in FIG. 4, that provide a relative voltage of −1, again with state 6 charging capacitor C1 and state 7 discharging it. The buck regulator control loop can similarly select between these two states to ensure that capacitor C1 is at a relative voltage of +1”); and
a second state in which the first capacitor node is connected to the other of the first and second output nodes and is discharged by a current flowing via that other one of the first and second output nodes (Para [0055], “There is similarly a pair of states, states 7 and 8 in FIG. 4, that provide a relative voltage of −1, again with state 6 charging capacitor C1 and state 7 discharging it. The buck regulator control loop can similarly select between these two states to ensure that capacitor C1 is at a relative voltage of +1”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16 & 21 are rejected under 35 U.S.C. 103 as being unpatentable over Mallinson in view of Morgan et al. (US 12,101,085 B2), hereinafter Morgan.
Regarding claim 16, Mallinson discloses the switching driver circuits of claim 1, but does not explicitly disclose a multi-channel amplifier system comprising a plurality of switching driver circuits and wherein a common capacitance connected to a common capacitance node is configured as the driver capacitance for each of switching driver circuits.
However, Morgan discloses, in figure 4, a multi-channel amplifier system comprising a plurality of switching driver circuits (101-1 and 101-2) and wherein a common capacitance connected to a common capacitance node is configured as the driver capacitance for each of switching driver circuits (common capacitance of either voltage driving circuit 106-1, 301, or 302).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the multi-channel amplifier system of Morgan with the switching driver circuit of Mallinson, to achieve the benefit of driving different transducers in multiple difference channels to provide multi-channel audio (Morgan, Col. 1, Lines 15-22).
Regarding claim 21, Mallinson discloses, in figure 3 & 4, a multi-channel amplifier system comprising:
a switching driver (switching driver 300), each of the switching drivers being configured to selectively modulate a voltage at at least one output node of the switching driver between selected switching voltages to drive a respective load (Para [0053], “States (i.e., configurations) 1 and 9 in FIG. 4 provide relative voltages of +2 and −2, respectively, i.e., +V.sub.CC and −V.sub.CC. There are now three states, states 4, 5 and 6, which provide zero voltage…And there are now four states that produce relative voltages of ±1, i.e., ±½ V.sub.CC…states 2 and 3 provide a relative voltage of +1 and states 7 and 8 provide a relative voltage of −1”);
wherein one of said switching voltages is a capacitor voltage (from C1);
a controller for controlling operation of the switching driver in a switching cycle such that load currents flowing to or from the capacitor node from or to the of switching driver provides voltage regulation of the capacitor voltage (Para [0055], “There is similarly a pair of states, states 7 and 8 in FIG. 4, that provide a relative voltage of −1, again with state 6 charging capacitor C1 and state 7 discharging it. The buck regulator control loop can similarly select between these two states to ensure that capacitor C1 is at a relative voltage of +1”), but does not explicitly disclose a plurality of switching drivers driven by a common driver capacitance and connected to a common capacitor node.
However, Morgan discloses, in figure 3, a plurality of switching drivers driven by a common driver capacitance and connected to a common capacitor node (common capacitance of either voltage driving circuit 106-1, 301, or 302 drives switching drivers 101-1 and 101-2).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the plurality of switching drivers in the amplifier system of Mallinson, to achieve the benefit of driving different transducers in multiple difference channels to provide multi-channel audio (Morgan, Col. 1, Lines 15-22).
Allowable Subject Matter
Claims 14-15 & 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Høyerby (US 2017/0359037 A1) [Figure 6. Discloses A multi-level class D audio power amplifier for supplying an N-level drive signal to a loudspeaker. The multi-level class D audio power amplifier includes a switching matrix having controllable semiconductor switches where the switching matrix include at least (N−2) switch inputs, coupled to respective ones of (N−2) DC input voltage nodes, and at least 2*(N−2) switch outputs coupled to respective ones of 2*(N−2) intermediate nodes of a first output driver. A control circuit is configured to sequentially connect each of the (N−2) DC input voltages to a predetermined set of nodes of the 2*(N−2) intermediate nodes of the first output driver via the switching matrix in accordance with one or more of the 2*(N−1) modulated control signals of the first output driver. N is a positive integer larger than or equal to 3.]
Lesso et al. (US 2023/0030111 A1) [Figure 1. Discloses switching drivers for driving a transducer. A switching driver (202) has supply nodes for receiving supply voltages (VSH, VSL) defining at least one input voltage and an output node (104). A controller (205) controls operation of the first switching driver to generate a drive signal for the transducer at the output node (104), based on an input signal (Sin). A first capacitor (201a) is connected between first and second capacitor nodes (104, 204a) and a second capacitor (201b) is connected between the second capacitor node (204a) and a third capacitor node (204b). A network of switches (203) selectively connects any of the driver output node, the second capacitor node and the third capacitor node to either of a respective pair of said supply nodes, with the first capacitor node connected to the first driver output node.]
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TYLER J PERENY whose telephone number is (571)272-4189. The examiner can normally be reached M-F 7:30-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Taelor Kim can be reached at (571) 270-7166. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TYLER J PERENY/ Examiner, Art Unit 2836
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