DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2 & 19-26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xu (2022/0021324).
With regard to claims 1 & 2, Xu, in Figure 5, discloses a safety circuit, comprising: at least one PWM input pin (PWMx3 input to 605) configured to receive at least one PWM driving signal (PWMx3); a power supply input pin (FVGD+) (configured to receive a system supply voltage; a first safety input pin (STO1) configured to receive a first safety signal and a second safety input pin (STO2) configured to receive a second safety signal; a high-side driving output node (gate drive signal from 605H) configured to produce a high-side gate driving signal and a low-side driving output node (gate drive signal from 605l) configured to produce a low-side gate driving signal; a power supply output node (VGD) configured to produce a driver supply voltage; a first logic circuit (OP1, OP3 & Q1) configured to: in response to the first safety signal being de-asserted, propagate the at least one PWM driving signal to produce the high-side gate driving signal and the low-side gate driving signal; and in response to the first safety signal being asserted, disable propagation of the at least one PWM driving signal and de-assert the high-side gate driving signal and the low-side gate driving signal; and a second logic circuit (OP2, OP3 & Q2) configured to: in response to the second safety signal being de-asserted, couple the power supply output node to the power supply input pin to propagate the system supply voltage as the driver supply voltage; and in response to the second safety signal being asserted, decouple the power supply output node from the power supply input pin to disable propagation of the system supply voltage (paragraphs 0043, 0044, 0066 & 0067 teaches that when the STO signals are disabled, power is provided to the drivers 605H & 605L and PWM is passed from motor controller 607 to the drivers as well and further teaches that when the STO signals are enabled, power is removed from the drivers and the PWM signals are no longer transferred from the motor controller to the drivers) (re claim 1), wherein the at least one PWM input pin comprise a high-side PWM input pin configured to receive a high-side PWM driving signal and a low-side PWM input pin configured to receive a low-side PWM driving signal, and wherein the first logic circuit is configured to: in response to the first safety signal being de-asserted, propagate the high-side PWM driving signal to the high-side driving output node to produce the high-side gate driving signal and propagate the low-side PWM driving signal to the low-side driving output node to produce the low-side gate driving signal, and in response to the first safety signal being asserted, disable propagation of the high-side PWM driving signal to the high-side driving output node, disable propagation of the low-side PWM driving signal to the low-side driving output node, and de-assert the high-side gate driving signal and the low-side gate driving signal (paragraphs 0043, 0044, 0066 & 0067) (re claim 2).
With regard to claims 19 & 20, Xu, in Figure 5, discloses a driver system, comprising: a control unit (607); a safety circuit that includes: at least one PWM input pin (input of 605H coupled to PWMx3); a power supply input pin (FVGD+); a first safety input pin (STO1) and a second safety input pin (STO2); a high-side driving output node (gate signal drive coupled to 605H); a low-side driving output node (gate signal drive coupled to 605L); a power supply output node (VGD); a first logic circuit (OP1, OP3 &Q1); a second logic circuit (OP2, OP3 &Q2); a gate driver device (605H & 605L) coupled to the safety circuit; a power stage; (IGBTx3) wherein: the control unit is configured to produce at least one PWM driving signal (PWMx3) for controlling operation of the power stage; the safety circuit is configured to receive the at least one PWM driving signal (via 613_a & 613_b), a first safety signal (STO1) and a second safety signal (STO2) and produce a high-side gate driving signal, a low- side gate driving signal and a driver supply voltage; and the gate driver device is configured to receive the high-side gate driving signal, the low-side gate driving signal and the driver supply voltage and produce shifted PWM driving signals for driving respective switches of the power stage (as seen in Fig. 5, the PWM signal is shifted for Vcc to FVGD+) (re claim 19), wherein: the first logic circuit is configured to: in response to the first safety signal being de-asserted, propagate the at least one PWM driving signal to produce the high-side gate driving signal and the low-side gate driving signal; and in response to the first safety signal being asserted, disable propagation of the at least one PWM driving signal and de-assert the high-side gate driving signal and the low-side gate driving signal; and the second logic circuit configured to: in response to the second safety signal being de-asserted, couple the power supply output node to the power supply input pin to propagate a system supply voltage as the driver supply voltage; and in response to the second safety signal being asserted, decouple the power supply output node from the power supply input pin to disable propagation of the system supply voltage (paragraphs 0043, 0044, 0066 & 0067 teaches that when the STO signals are disabled, power is provided to the drivers 605H & 605L and PWM is passed from motor controller 607 to the drivers as well and further teaches that when the STO signals are enabled, power is removed from the drivers and the PWM signals are no longer transferred from the motor controller to the drivers) (re claim 20).
With regard to claims 21-26, Xu, in Figure 5, discloses a device, comprising: a first input pin configured to receive a PWM driving signal (input of 605H coupled to PWMx3); a first safety input pin (STO1) configured to receive a first safety signal; a high-side driving output node (gate drive signal coupled to output of 605H) configured to produce a high-side gate driving signal; a power supply output node (VGD) configured to produce a driver supply voltage; a first logic circuit (OP1, OP3 & Q1) configured to: in response to the first safety signal being de-asserted, propagate the PWM driving signal to produce the high-side gate driving signal; and in response to the first safety signal being asserted, disable propagation of the PWM driving signal and de-assert the high-side gate driving signal (paragraphs 0043, 0044, 0066 & 0067 teaches that when the STO signals are disabled, power is provided to the drivers 605H & 605L and PWM is passed from motor controller 607 to the drivers as well and further teaches that when the STO signals are enabled, power is removed from the drivers and the PWM signals are no longer transferred from the motor controller to the drivers) (re claim 21), further comprising: a power supply input pin configured to receive a system supply voltage (FVGD+); a second safety input pin (STO2) configured to receive a second safety signal; and a low-side driving output node (Gate Drive Signal coupled to 605L) configured to produce a low-side gate driving signal (re claim 22), wherein the first logic gate is configured to produce the low-side gate driving signal by propagating the PWM driving signal (via OP3) (re claim 23), wherein the first logic gate is configured to de- assert the low-side gate driving signal by disabling the propagation of the PWM driving signal (via OP3) (re claim 24), further comprising a second logic circuit (OP2, OP3 & Q2) configured to: in response to the second safety signal being de-asserted, couple the power supply output node to the power supply input pin to propagate the system supply voltage as the driver supply voltage; and in response to the second safety signal being asserted, decouple the power supply output node from the power supply input pin to disable propagation of the system supply voltage (paragraphs 0043, 0044, 0066 & 0067) (re claim 25), further comprising a first logic gate (D1, D2) coupled to the first logic circuit and to the second logic circuit (re claim 26).
Allowable Subject Matter
Claims 3-12 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 3 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record does not teach or fairly suggest a safety circuit comprising all the features as recited in the claims and in combination with the safety circuit further comprising: a first backup activation circuit configured to force the second safety signal to an asserted state in response to the first combined failure signal being asserted; and a second backup activation circuit configured to force the first safety signal to an asserted state in response to the second combined failure signal being asserted.
Claim 4 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record does not teach or fairly suggest a safety circuit comprising all the features as recited in the claims and in combination with the first logic circuit comprises: a first AND logic gate configured to apply AND logic processing to the at least one PWM driving signal and the first safety signal to produce the high-side gate driving signal; and a second AND logic gate configured to apply AND logic processing to the at least one PWM driving signal and the first safety signal to produce the low-side gate driving signal.
Claims 5 & 6 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because they depend on claim 4 which would also be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 7 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record does not teach or fairly suggest a safety circuit comprising all the features as recited in the claims and in combination with the second logic circuit being configured to receive a square wave self-test signal, and wherein the second logic circuit comprises: a first switch and a second switch arranged in series between the power supply input pin and the power supply output node, the first switch being controlled by the output of an AND logic gate configured to apply AND logic processing to the second safety signal and the self-test signal, and the second switch being controlled by the self-test signal; and a third switch and a fourth switch arranged in series between the power supply input pin and the power supply output node, the third switch being controlled by the output of an AND logic gate configured to apply AND logic processing to the second safety signal and to the complement of the self-test signal, and the fourth switch being controlled by the complement of the self-test signal.
Claim 8 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because it depends on claim 7 which would also be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 9 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because it depends on claim 3 which would also be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 10 & 11 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because they depend on claim 8 which would also be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 12 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record does not teach or fairly suggest a safety circuit comprising all the features as recited in the claims and in combination with the first logic circuit being configured to assert a first internal feedback signal in response to the high-side gate driving signal and the low-side gate driving signal being de-asserted while the first safety signal is asserted; the second logic circuit is configured to assert a second internal feedback signal in response to a voltage at the power supply output node being lower than a threshold value; and the safety circuit is further configured to assert, at a feedback output pin, a feedback signal in response to any one of the first internal feedback signal and the second internal feedback signal being asserted.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Upadhyaya (US 11,349,381), Knudsen (US 2021/0296882), Wang (US 2006/0061340), Guenter (US 2023/0299706) and Zhang (US 2023/0353049) all teach motor driving circuits wherein an STO signal disables the motor driver to ensure that the motor is operated safely and share similarities with Applicant’s invention.
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/Scott Bauer/Primary Examiner, Art Unit 2838
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