DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
Claims 1, 11, and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The examiner agrees the argument given in the Written Opinion of the International Searching Authority Re Item VIII. The wording “dual-stage Schottky barrier” refers to the energy barrier formed by a Schottky junction and would not comprise physical materials or the formation thereof. For the purpose of examination, the examiner interpreted the “dual-stage Schottky barrier” as a “dual-stage Schottky barrier {layers, stages, junction, contact area, etc.}” thereby making the claims refer to the physical structure of the metals that create the Schottky barrier rather than the energy barrier itself.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4-13 are rejected under 35 U.S.C. 102(1) as being clearly anticipated by Takagi et al. JP 2016097873 A, hereinafter "Takagi".
Regarding independent claim 1, Takagi discloses 1: a semiconductor device (Fig 1) comprising: a dual-stage Schottky barrier (Schottky metal layer 30a and first gate metal layer 30b), wherein the dual-stage Schottky barrier comprises: a first stage (30a) formed over a substrate stack (substrate 10), wherein the first stage comprises an upper layer (30a) having a length corresponding to a gate length for the device (Schottky metal layer 30a has gate length L1 [discussion of Fig 1]); and a second stage (30d) formed at least partially over the first stage, wherein the second stage comprises a contact segment (first gate metal layer 30b, see Fig 3E) having a length less than the gate length (shown in Fig 1).
Regarding claim 4, Takagi discloses 4: The semiconductor device of Claim 1, further comprising a T-shaped metal gate (gate metal layer 30c, T-shaped in Fig 1) formed over the second stage.
Regarding claim 5, Takagi discloses 5: The semiconductor device of Claim 1, further comprising an early passivation layer (Fig 3D first insulating layer 24a) formed over the first stage.
Regarding claim 6, Takagi discloses 6: The semiconductor device of Claim 5, wherein: the second stage comprises sidewalls (Fig 1 two side surfaces 32 of the first gate metal layer 30b); and the device further comprises a gate electrode (30c) formed over the second stage (30d and 30b).
Regarding claim 7, Takagi discloses 7: The semiconductor device of Claim 5, further comprising a T-shaped metal gate (30c T-shaped in Fig 1) formed over the second stage (30d and 30b).
Regarding claim 8, Takagi discloses 8: The semiconductor device of Claim 5, further comprising: a gate electrode (30c) formed over the second stage (30d and 30b); and a post-gate passivation layer (Fig 3E second insulating layer 24c) formed over the early passivation layer (24a) and the gate electrode.
Regarding claim 9, Takagi discloses 9: The semiconductor device of Claim 1, further comprising: a gate electrode formed over the second stage (30c formed on 30b); and a post-gate passivation layer formed over the gate electrode (see Fig 1 24 and Fig 3E 24c).
Regarding claim 10, Takagi discloses 10: The semiconductor device of Claim 1, wherein: the substrate stack (semiconductor layer 11 in Fig 2) comprises a recess (opening 40a); and the first stage is formed at least partially in the recess of the substrate stack (see Fig 2A-B).
Regarding independent claim 11, Takagi discloses 11: A method comprising: forming a first stage of a dual-stage Schottky barrier over a substrate stack for a semiconductor device (Fig 2A-B), wherein the first stage comprises an upper layer (30a with length L1) having a length corresponding to a gate length for the device; and forming a second stage (30d in Fig 1) of the dual-stage Schottky barrier at least partially over the first stage, wherein the second stage comprises a contact segment having a length less than the gate length (contact segment, first gate metal layer 30b, see Fig 3E).
Regarding claim 12, Takagi discloses 12: The method of Claim 11, further comprising forming a gate electrode (formation of gate electrode 30c shown in Fig 3B-C) over the second stage.
Regarding claim 13, Takagi discloses 13: The method of Claim 12, further comprising forming a post-gate passivation layer (addition of second insulating layer 24c in Fig 3E) over the gate electrode.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3, 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Takagi in view of Tabatabaie-Alavi et al US10026823 B1, hereinafter "Tabata".
Takagi discloses the semiconductor device of claim 1 and the method of claim 11; however, Takagi fails to explicitly disclose the first stage and the second stage comprising a plurality of metal layers wherein: the first stage comprises a first layer, a second layer, a third layer, and a fourth layer, wherein the upper layer comprises the fourth layer; the second stage comprises a fifth layer and a sixth layer, wherein the contact segment comprises at least a portion of the fifth layer; each of the first layer, the third layer, and the fifth layer comprises nickel; and each of the second layer, the fourth layer, and the sixth layer comprises platinum.
However, Tabata, in the same field of endeavor, discloses a Schottky contact structure (gate electrode structure 20 of Fig 2) with multiple stacks of metal layers (layers 24, 26, 28, 30, 32, 34) that alternate nickel and platinum materials. Tabata discloses the motivation for having layers of alternating nickel and platinum within a stacked gate structure below a top electrode layer made of gold as, “alternating barrier layers is more effective than the use of a single thick Ni and Pt layers (greater than several thousand Angstroms) because grain structures of the individual layers are interrupted by arranging and alternating Ni and Pt layers, thereby reducing the migration of the gold to the semiconductor layer reducing FET leakage” (Tabata Col 2 Line 60-65). Therefore, it would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to modify the semiconductor device structure of Takagi with the stacked metal Schottky contact layers disclosed in Tabata to reduce FET leakage (Tabata Col 2 line 65).
Regarding claim 2, Takagi in view of Tabata discloses 2: The semiconductor device of Claim 1, wherein each of the first stage and the second stage comprises a plurality of metal layers (modify the Schottky metal layer 30a of Takagi Fig 1 to include the alternating nickel and platinum layers 24, 26, 28, and 30, respectively, of Tabata Fig 2, and modify the second stage metal layer of Takagi 30d to include Tabata’s metal layers 32, 34, and 22 made of Ni, Pt, and Au, respectively, where the three layers 32, 34, and 22 thereby makeup the contact segment of the second stage referred to in claim 1) .
Regarding claim 3, Takagi in view of Tabata discloses 3: The semiconductor device of Claim 1, wherein: the first stage comprises a first layer (24), a second layer (26), a third layer (28), and a fourth layer (30), wherein the upper layer comprises the fourth layer; the second stage comprises a fifth layer (32) and a sixth layer (34), wherein the contact segment (32, 34, 22) comprises at least a portion of the fifth layer; each of the first layer, the third layer, and the fifth layer comprises nickel (see Tabata Fig 2); and each of the second layer, the fourth layer, and the sixth layer comprises platinum (see Tabata Fig 2).
Regarding claim 14, Takagi in view of Tabata discloses 14: The method of Claim 11, wherein each of the first stage and the second stage comprises a plurality of metal layers (modification of the method of Takagi discussed in claim 11 to include the plurality of metal layers disclosed in Tabata through the method shown in Tabata Figs 5A-D) .
Regarding claim 15, Takagi in view of Tabata discloses 15: The method of Claim 11, wherein: forming the first stage of the dual-stage Schottky barrier comprises forming a first layer (24), a second layer (26), a third layer (28), and a fourth layer (30), wherein the upper layer comprises the fourth layer; forming the second stage of the dual-stage Schottky barrier comprises forming a fifth layer (32) and a sixth layer (34), wherein the contact segment (layers 32, 34, 22) comprises at least a portion of the fifth layer; each of the first layer, the third layer, and the fifth layer comprises nickel; and each of the second layer, the fourth layer, and the sixth layer comprises platinum (refer to Tabata Fig 2 formed by the method of Figs 5A-D as they are modified into to the first stage structure 30a and second stage structure 30d of Takagi Fig 1 and see discussion of claims 2-3 above).
Claims 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Takagi in view of Immorlica et al. US8003504 B2, hereinafter “Immorlica”. Takagi discloses the method of creating the semiconductor device in claims 1-10; however, the step of "forming an early passivation layer over the first stage" is not disclosed in Takagi, as Takagi does not explicitly form the first stage, form an early passivation layer, then etch the early passivation layer to partially expose the first stage, then form a second stage, in that specific order.
However, in the same field of endeavor, Immorlica (Fig 4A-F) discloses a method for forming a thin Schottky metal layer before depositing a dielectric passivation layer, then etching the passivation layer, followed by the final step of depositing gate and/or field plate metal. It would have been obvious to one having ordinary skill in the art before the effective filing date to modify the method of creating the device disclosed in Takagi with the order of steps in Immorlica who forms the Schottky metal layer first for two purposes: "The first is to form a Schottky contact at the gate and the second is to protect the semiconductor from dry etch damage, since the plasma etch terminates when it hits the thin Schottky metal. This results in a higher-power device and better reliability as well as lower gate leakage" (Immorlica [Col 4 Lines 50-55]).
Regarding independent claim 16, Takagi in view of Immorlica discloses 16: A method (Immorlica Fig 4-8) comprising: forming a first stage of a dual-stage Schottky barrier (“refractory metal layer 60 that provides Schottky contact to substrate 16” [Immorlica Col 8 Line 58]) over a substrate stack (16) for a semiconductor device, wherein the first stage comprises an upper layer having a length corresponding to a gate length for the device; forming an early passivation layer (Fig 4E passivation layer 32) over the first stage; patterning and etching the early passivation layer (Fig 4F, the passivation layer “is subjected to ion etching” [Col 8 lines 49-50]) to partially expose the first stage; and forming a second stage of the dual-stage Schottky barrier at least partially over the first stage (the modification of the method steps in view of Immorlica disclose the previous steps of the method in claim 16, while Takagi discloses the following portion of claim 16 in the method of formation shown in Fig 4A-D) wherein the second stage (Takagi 130b first gate metal layer) comprises a contact segment having a length less than the gate length (top surface of 130b has a length less than the length of the gate metal layer 130c).
Regarding claim 17, Takagi in view of Immorlica discloses 17: The method of Claim 16, further comprising forming a gate electrode (gate metal layer 130c Takagi Fig 4C-D) over the second stage.
Regarding claim 18, Takagi in view of Immorlica discloses 18: The method of Claim 17, further comprising forming a post-gate passivation layer (insulator layer 124 Takagi Fig 4D) over the gate electrode.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Takagi in view of Immorlica, further in view of Tabata. Claims 19 and 20 both depend on the independent claim 16. Takagi in view of Immorlica discloses the method of claim 16; however Takagi modified by Immorlica fails to disclose each of the first stage and the second stage comprises a plurality of metal layers and the limitation of claim 20 wherein: forming the first stage of the dual-stage Schottky barrier comprises forming a first layer, a second layer, a third layer, and a fourth layer, wherein the upper layer comprises the fourth layer; forming the second stage of the dual-stage Schottky barrier comprises forming a fifth layer and a sixth layer, wherein the contact segment comprises at least a portion of the fifth layer; each of the first layer, the third layer, and the fifth layer comprises nickel; and each of the second layer, the fourth layer, and the sixth layer comprises platinum.
However, as discussed above for claims 2-3 and 14-15, Tabata discloses the motivation for having layers of alternating nickel and platinum within a stacked gate structure below a top electrode layer made of gold as, “alternating barrier layers is more effective than the use of a single thick Ni and Pt layers (greater than several thousand Angstroms) because grain structures of the individual layers are interrupted by arranging and alternating Ni and Pt layers, thereby reducing the migration of the gold to the semiconductor layer reducing FET leakage” (Tabata Col 2 Line 60-65).
Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of the claimed invention, to modify the disclosed method of Takagi to have the order of steps disclosed in Immorlica and further modify the method of formation to include more layers of Ni and Pt as disclosed in Tabata to reduce FET leakage (Tabata Col 2 line 65).
Regarding claim 19, Takagi in view of Immorlica and further in view of Tabata discloses 19: The method of Claim 16 (Takagi in view of Immorlica discussed above), wherein each of the first stage and the second stage comprises a plurality of metal layers (the alternating metal layers shown in Tabata Fig 2 and method of formation disclosed in Figs 5A-D).
Regarding claim 20, Takagi in view of Immorlica and further in view of Tabata discloses 20: The method of Claim 16 (Takagi in view of Immorlica discussed above), wherein: forming the first stage of the dual-stage Schottky barrier comprises forming a first layer (24), a second layer (26), a third layer (28), and a fourth layer (30), wherein the upper layer comprises the fourth layer; forming the second stage of the dual-stage Schottky barrier comprises forming a fifth layer (32) and a sixth layer (34), wherein the contact segment (layers 32, 34, 22) comprises at least a portion of the fifth layer; each of the first layer, the third layer, and the fifth layer comprises nickel; and each of the second layer, the fourth layer, and the sixth layer comprises platinum (refer to Tabata Fig 2 formed by the method of Figs 5A-D as they are modified into to the first stage structure 30a and second stage structure 30d of Takagi Fig 1 and see discussion of claims 2-3 above).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA MICKEY whose telephone number is (571)270-3109. The examiner can normally be reached M-F, 8am to 5pm ET.
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/TERESA N MICKEY/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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