DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .’
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 17 April, 2026 has been entered.
Response to Amendment
The Amendment filed 17 April, 2026 has been entered. Claims 1-5, 7-12, and 14-22 remain pending in the application. Applicant’s amendments to the Claims have necessitated further search and consideration. Rejections under 35 USC § 103 have been updated in response to amendments. Rejections under 35 USC § 112 have been addressed and are withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 7-10, 12, 15-17, 19, and 21-22 are rejected under 35 U.S.C. 103 as being obvious over Malladi et al (U.S. Patent Pub. No. 2021/0311739), hereinafter referred to as Malladi, in combination with Vantrease (U.S. Patent No. 10,402,329), Satish et al (U.S. Patent No. 10,365,827), hereinafter referred to as Satish, and Guim Bernat et al (U.S. Patent Pub. No. 2022/0014588), hereinafter referred to as G-B.
In regard to claim 1, Malladi teaches a method comprising: receiving, at a computational device, a command, wherein the computational device comprises at least one computational resource and a memory and wherein the command is sent from a host using a first protocol of a first communication interface (Paragraph 0005, lines 1-4 disclose function-in-memory circuits (110 in Fig. 2A) which receive instructions over a CXL protocol (Paragraph 0024); Fig. 4B shows FIM circuits include processing components and SRAM; Fig. 4A item 420 shows this is a single device; ¶ 0057 CXL interface circuit communicates with the host over an interface (i.e. first interface) using CXL (i.e. a first protocol)); performing, using the at least one computational resource, based on the command, a computational operation, wherein the computational operation generates a result (Paragraph 0005, lines 6-9); and sending, from the computational device, using a second protocol of a second communication interface, the result; accessing, using the second protocol, at least a portion of the memory (¶ 0014, ¶ 0057-0058 memory module communicates over DDR interface (i.e. second interface) by converting CXL transactions to specific instruction streams for the memory device (i.e. supporting some second protocol specifically for accessing the memory));
Malladi does not teach storing, in the at least a portion of the memory, the command, however Satish discloses submission queues inside I/O controllers which store, in at least a portion of the memory, a command (Column 10, line 60 to Column 11, line 4), achieving the claimed limitation when implemented in the SRAM (Column 6, lines 42-50 I/O controllers utilize SRAM for storage) of the CXL interface circuit of the FIM circuits disclosed in Malladi, which utilize the CXL protocol for host communication (Malladi Paragraph 0059). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Satish in order to store commands and to improve storage array performance (Column 1, lines 61-63).
The previously cited references do not teach an embodiment wherein the second communication interface is configured to modify, using a third protocol, a copy of data stored at a first location based on modifying the data stored at a second location. However, Vantrease discloses an arbitrated interconnect 114 in Fig 2D which can write a modified copy of a cache line back to memory connected over DDR (i.e. second interface) using a handshake or other suitable protocol (i.e. third protocol) when indicated (Column 9, lines 50-54 writeback; Column 6, lines 25-32 memory is coupled via DDR; Column 14, lines 17-23 handshake protocol), achieving the claimed limitation when combined with Malladi's adapter circuit and DDR memory. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Vantrease in order to allow for coherent data updates and provide a "minimally invasive method" to block transactions on unmodified cache data (Column 3, lines 29-33).
The previously cited references do not explicitly teach using different protocols for commands, memory access and coherent transactions, however G-B teaches a connected network of computational devices over CXL (¶ 0024) utilizing multiple different CXL protocols (¶ 0024, lines 9-13). This includes the CXL.io (i.e. first; general I/O) protocol for command access (¶ 0025, lines 1-7) and the CXL.mem (second; memory access) and/or CXL.cache (third; cache transaction) protocols for memory access and coherence (¶ 0026, lines 1-11; ¶ 0027). While previously cited references would support multiple protocols in combination, G-B explicitly provides motivation and support for performing different actions using three protocols as claimed. A person of ordinary skill would be able to combine the disclosure of G-B in the CXL interface of Malladi along with the techniques of Vantrease in order to use three different protocols for command I/O, memory device access, and coherence transactions respectively as claimed. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of G-B in order to separately handle certain memory access transactions and avoid the increased latency of multiple handshake operations in other protocol implementations (¶ 0022).
As for claim 2, the previously cited references teach the method of claim 1. Additionally, Malladi Paragraph 0048, describes a process by which the result of an operation is sent to memory. The DDR interface of Malladi can be configured to use a second protocol such as DDR2, DDR3, etc. (i.e. separate memory access protocol; Paragraph 0022), and storing the result in memory would functionally require use of one of the specified memory access protocols (see Fig. 2B, DRAM connected to FIM modules), achieving the claimed limitation.
As for claim 3, the previously cited references teach the method of claim 1. Additionally, Malladi teaches an embodiment wherein: the second protocol comprises a cache protocol; and the sending the result is performed using the cache protocol (Paragraph 0014, lines 4-5; memory device is connected via cache coherent protocol interface, e.g. second protocol must comprise a cache protocol of some kind) and G-B in claim 1 includes the use of CXL.mem or CXL.cache for coherence (¶ 0026, lines 1-11), meaning a person of ordinary skill in the art would be capable of using the other, non-coherent protocol for other memory transactions. Therefore, using CXL.cache to send a result (i.e. some normal operation of the cache protocol) and CXL.mem for coherence would achieve the claimed limitation.
As for claim 5, the previously cited references teach the method of claim 1. Additionally, Malladi teaches an embodiment wherein the command is received using a protocol (Paragraph 0024) and G-B teaches communication using CXL.io (¶ 0025) as well as CXL.mem (¶ 0027) between devices, meaning both protocols can be used to receive commands, achieving the claimed limitation.
As for claim 7, the previously cited references teach the method of claim 1. Additionally, G-B teaches a connected network of computational devices over CXL (¶ 0024) utilizing multiple CXL protocols (¶ 0024, lines 9-13). This includes the CXL.io protocol for command access (i.e. first protocol, ¶ 0025, lines 1-7), which in combination may be used to send commands to and receive commands at the CXL circuit of Malladi, achieving the claimed limitation.
In regard to claim 8, Malladi discloses a physical apparatus (see Figs. 2A-2C) which carries out methods taught in the disclosure. As for the remaining limitations of claim 8, Applicant is directed to the rejection of claim 1 above as the claims share limitations and are therefore rejected on shared rationale. Additionally, while the nominal "first" and "second" protocols are switched in claim 8, the rationale of claim 1 would still address these limitations as they do not change the actual function of the apparatus.
In regard to claim 9, Applicant is directed to the rejection of claim 2 above as the claims share limitations and are therefore rejected on shared rationale.
In regard to claim 10, Applicant is directed to the rejection of claim 3 above as the claims share limitations and are therefore rejected on shared rationale.
In regard to claim 12, Applicant is directed to the rejection of claim 5 above as the claims share limitations and are therefore rejected on shared rationale. Additionally,
In regard to claim 16, Applicant is directed to the rejection of claim 9 above as the claims share limitations and are therefore rejected on shared rationale. While claim 16 specifies receiving at the host (control circuit) over a protocol, this is functionally captured by the addressed limitation of sending to the host over a protocol, achieving the claimed limitation.
In regard to claim 17, Applicant is directed to the rejection of claim 10 above as the claims share limitations and are therefore rejected on shared rationale. While claim 17 specifies receiving at the host (control circuit) over a protocol, this is functionally captured by the addressed limitation of sending to the host over a protocol, achieving the claimed limitation.
In regard to claim 19, Applicant is directed to the rejection of claim 12 above as the claims share limitations and are therefore rejected on shared rationale. While claim 19 specifies receiving at the host (control circuit) over a protocol, this is functionally captured by the addressed limitation of sending to the host over a protocol, achieving the claimed limitation.
In regard to claim 21, the previously cited references teach the method of claim 1. Additionally, Satish teaches command queues to store commands in a controller (Column 10, line 60 to Column 11, line 1) wherein commands are retrieved from (i.e. detected in) the queue (Column 11, lines 1-7), achieving the claimed limitation.
As for claim 22, the previously cited references teach the apparatus of claim 8. They do not teach the remaining limitations of claim 22. Additionally, Satish teaches completion queues to store completions in a controller (Column 11, lines 8-9) wherein completed commands are retrieved from (i.e. detected in) the queue (Column 11, lines 9-11), achieving the claimed limitation.
Claims 4, 11, and 18 are rejected under 35 U.S.C. 103 as being obvious over Malladi, Vantrease, Satish, G-B, and Johar et al (U.S. Patent Pub. No. 2015/0356019), hereinafter referred to as Johar.
As for claim 4, the previously cited references teach the method of claim 1. They do not teach the remaining limitations of claim 4. However, Johar teaches allocating, using a protocol, additional memory at the computational device; and storing, in the additional memory, at least a portion of the result. Paragraph 0016, lines 24-28 disclose a write allocate policy which achieves the claimed limitation. Paragraph 0006, lines 24-26 explain that the write allocate policy stores a local copy of accessed data, i.e. allocating and storing the result in additional memory that was not addressed originally. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Johar in order to cache accessed items (Paragraph 0016, lines 27-28) which would reduce access latency as known in the art. This cache policy could be implemented using the CXL.mem (i.e. second; memory access) protocol along with CXL.cache as disclosed by G-B ¶ 0026-0027, achieving the claimed limitation.
In regard to claim 11, Applicant is directed to the rejection of claim 4 above as the claims share limitations and are therefore rejected on shared rationale. Additionally, the cited disclosure of Johar concerning a cache unit could be combined by one of ordinary skill in the art with any one of the various CXL protocols used by previously cited references for cache-type transactions (e.g. CXL.cache), achieving the claimed limitation.
In regard to claim 18, Applicant is directed to the rejection of claim 11 above as the claims share limitations and are therefore rejected on shared rationale.
Claims 14, 15, and 20 are rejected under 35 U.S.C. 103 as being obvious over Malladi, Vantrease, Satish, G-B, and Chirca et al (U.S. Patent Pub. No. 2022/0156192), hereinafter referred to as Chirca.
As for claim 14, the previously cited references teach the method of claim 1. They do not teach the remaining limitations of claim 14. However, Chirca discloses a data routing unit (DRU 300 in Fig. 3) which includes an MMU 328 for address translation (Paragraph 0041, lines 3-6; e.g. computational device which produces and sends a result after an operation of a computational resource (address translation by MMU)). The DRU is connected to at least two different interfaces with differing protocols (direct write of a MMR e.g. DMA, and a PSI-L interface; Paragraph 0031, lines 14-17) and can receive commands and send responses from one or more of said interfaces (Paragraph 0031, lines 13-14; ¶ 0032, lines 11-12). When combined with the disclosure of Malladi, the claimed limitation of [sending and] receiving commands at the device from an additional interface using an additional protocol is achieved. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Chirca in order to ensure responsiveness of processing networks (Paragraph 0016).
In regard to claim 15, Applicant is directed to the rejections of claims 1 and 8 above as the claims share limitations and are therefore rejected on shared rationale, as well as the rejection of claim 14 which addresses the limitation wherein the result is sent from the computational device using a third protocol of a second communication interface as the multiple interfaces and protocols used in Chirca may also receive responses (for ex. PSI-L interface in ¶ 0032).
In regard to claim 20, Applicant is directed to the rejection of claim 14 above as the claims share limitations and are therefore rejected on shared rationale.
Response to Arguments
Applicant's arguments filed 17 April, 2026 (see pages 7-8 of response) have been fully considered. Remarks directed to amended claims and the suitability of reference Chirca were not persuasive. Previously cited references were found to teach the claimed limitations as amended, and rejections have been updated. Reference Chirca was also still found to teach the limitation wherein commands and responses may be sent and received using additional protocols on additional interfaces, as shown in the updated rejections.
Conclusion
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/ZAKARIA MOHAMMED BELKHAYAT/Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139
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