DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 10-2023-0057685, filed on May 3rd, 2023.
Information Disclosure Statement
The information disclosure statement (IDS) filed on April 5th, 2024 is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 19 recites the limitation “the preliminary oxide pattern” in line 1 of said claim. There is insufficient antecedent basis for this limitation in the claim, as “a preliminary oxide pattern” was never introduced. Examiner is seeking clarification on whether this term was meant to refer to “a preliminary oxide semiconductor pattern” or “a preliminary metal oxide pattern” or if “the preliminary oxide pattern” as stated should be amended to “a preliminary oxide pattern”. For the purposes of compact prosecution, Examiner shall interpret “the preliminary oxide pattern” as “a preliminary oxide pattern”.
Claim 20 is rejected due to its dependence upon previously rejected claim (i.e., Claim 19).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 4, 17, 19 is/are rejected under 35 U.S.C 102(a)(1) as being anticipated over Chen et al. (US20190319100A1), hereinafter after Chen.
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Annotated Chen Fig. 4a with directional arrows
As to Claim 1, Chen teaches: Method for manufacturing a semiconductor device (Fig 6 process), comprising:
forming mold insulation patterns (alternating stack 32 and 42) on a substrate (substrate (9, 10), [0046] “A stepped cavity is formed within the volume from which portions of the alternating stack (32, 42) are removed through formation of the stepped surfaces”, Fig. 3A, 4A) each of the mold insulation patterns (32, 42) extending in a second direction (hd1) parallel to an upper surface of the substrate (Fig. 4A, [0049] In another embodiment, multiple “columns” of staircases can be formed along a first horizontal direction hd1”).
forming an oxide semiconductor layer (blocking dielectric layer 52, OSL, [0064] “blocking dielectric layer 52 can include a dielectric semiconductor compound such as silicon oxide”) conformally on sidewalls and upper surfaces of the mold insulation patterns (32,42) and the substrate (9,10) between the mold insulation patterns (Fig. 6A);
forming a first metal oxide layer (blocking dielectric layer 52, metal oxide layer (MOL), [0062] “blocking dielectric layer can include a dielectric metal oxide layer”, [0062] “blocking dielectric layer 52 can include a single dielectric material layer or a stack of a plurality of dielectric material layers”) on the oxide semiconductor layer (OSL 52) to cover the oxide semiconductor layer (OSL 52, Fig. 6A);
forming a first sacrificial layer (semiconductor oxide core layer 622) on the first metal oxide layer (MOL 52) to fill a trench between the mold insulation patterns ((32,42), Fig 6E-6F);
patterning the first sacrificial layer (622, [0085] “the horizontal portion of the semiconductor oxide core layer 622 overlying the horizontal portion of the semiconductor channel layer 60L can be removed, for example, by a recess etch”), the first metal oxide layer (MOL 52, [0095] “blocking dielectric layer 52 can be etched by a respective anisotropic etch process”), and the oxide semiconductor layer (OSL 52, [0095] “blocking dielectric layer 52 can be by a respective anisotropic etch process”) to form a first structure extending a first direction, parallel to the upper surface of the substrate and perpendicular to the second direction (Fig. 6A-6B, Fig. 6E-6F), the first structure including a preliminary first metal oxide layer pattern (PMOL 52), a preliminary oxide semiconductor layer pattern (POSL 52) and a first sacrificial layer pattern stacked (SLP 62, Fig. 6E-6F);
forming a preliminary second metal oxide layer pattern (tunneling dielectric layer 56, [0095] “the tunneling dielectric layer 56, the charge storage layer 54, the blocking dielectric layer 52 are sequentially anisotropically etched”, PSMOL 56) selectively on a sidewall of the preliminary oxide semiconductor layer pattern (POSL 52, Fig. 6B);
removing selective portions of the first structure (PMOL 52, POSL 52, SLP 62), and the preliminary second metal oxide layer pattern (PSMOL 56) from the upper surfaces of the mold insulation patterns (32,42) to form an oxide semiconductor layer pattern (OSLP 52), a first metal oxide layer pattern (MOLP 52), and a second metal oxide layer pattern (SMOLP 56) covering a surface of the oxide semiconductor layer pattern (OSLP 52) on the sidewalls of the mold insulation patterns (32,42) and on the substrate (9,10) between the mold insulation patterns (Fig. 6A-6B, Fig. 6E-6F);
removing the remaining first sacrificial layer pattern (SLP 622, Fig. 6E-6F); and
forming a conductive layer pattern (charge storage layer 54, CLP 54) extending in the second direction on the sidewalls of the mold insulation patterns, and on the first and second metal oxide layer patterns formed on the sidewalls of the mold insulation patterns (Fig. 6B, [0065] “the charge storage layer 54 can include a continuous layer or patterned discrete portions of a conductive material such as doped polysilicon or a metallic material that is patterned into multiple electrically isolated portions.”)
As to Claim 3, Chen teaches: The method of claim 1 (Fig 6 process), wherein the first and second metal oxide layer patterns (MOLP 52, SMOLP 52) include substantially the same material composition. ([0063] “the blocking dielectric layer 52 includes aluminum oxide”, [0068] “tunneling dielectric layer 56 can include…dielectric metal oxides (such as aluminum oxide and hafnium oxide”).
As to Claim 4, Chen teaches: The method of claim 1 (Fig 6 process), wherein the first and second metal oxide layer patterns (MOLP 52, SMOLP 52) include at least one of aluminum oxide, zirconium oxide, hafnium oxide, or titanium oxide ([0063] “the blocking dielectric layer 52 includes aluminum oxide”, [0068] “tunneling dielectric layer 56 can include…dielectric metal oxides (such as aluminum oxide and hafnium oxide”).
As to Claim 17, Chen teaches: Method for manufacturing a semiconductor device (Fig. 6a process), comprising:
forming a preliminary oxide semiconductor layer pattern (POSL, 52) on a substrate (9,10);
forming a preliminary metal oxide layer pattern (PMOL, 52) selectively on an exposed surface of the preliminary oxide semiconductor layer pattern, the preliminary metal oxide layer pattern covering the exposed surface of the preliminary oxide semiconductor layer pattern (Fig. 6a);
forming a sacrificial layer (622) on the preliminary metal oxide layer pattern (PMOL 52);
removing at least portions of the sacrificial layer (622, Fig 6E-6F)), the preliminary metal oxide layer pattern and the preliminary oxide semiconductor layer pattern (PMOL 52, POSL 52, Fig. 6A-6B) to form an oxide semiconductor layer pattern (OSLP 52), a metal oxide layer pattern (MOLP 52), and a sacrificial layer pattern (SLP 62);
removing the remaining sacrificial layer pattern (SLP 62, Fig. 6E-6F); and
forming a conductive layer pattern (charge storage layer 54) on the metal oxide layer pattern ([0065] “the charge storage layer 54 can include a continuous layer or patterned discrete portions of a conductive material”).
As to Claim 19, Chen teaches: The method of claim 17, further comprising forming mold insulation patterns (32,42) on the substrate (9,10), and wherein the preliminary oxide pattern (blocking dielectric layer 52) is conformally formed on sidewalls of the mold insulation patterns and the substrate between the mold insulation patterns (Fig. 6A, [0064] “In this case, the dielectric semiconductor compound of the blocking dielectric layer 52 can be formed by a conformal deposition method such as low pressure”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2, 5, 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claim(s) 1, 3-4, 17, 19 above, and further in view of Vinasco et al. (US 20210305255 A1); hereinafter Vinasco.
As to Claim 2, Chen teaches: The method of claim 1 (Chen, Fig 6 process),
Chen does not explicitly teach: wherein the oxide semiconductor layer pattern includes at least one of InxGayZnzO, InxSnyZnzO, InxZnyO, ZnxO, ZnxSnyO, ZnxOyN, ZrxZnySnzO, HfxInyZnzO, GaxZnySnzO, AlxZnySnzO, or YbxGayZnzO. Chen does disclose an oxide semiconductor layer (OSL 52) with a composition of silicon oxide ([0064]) but does not expressly disclose the composition materials in the instant claim.
However, in an analogous art, Vinasco teaches wherein the oxide semiconductor layer pattern (channel layer 107) includes at least one of InxGayZnzO, InxSnyZnzO, InxZnyO, ZnxO, ZnxSnyO, ZnxOyN, ZrxZnySnzO, HfxInyZnzO, GaxZnySnzO, AlxZnySnzO, or YbxGayZnzO ([0043] “the channel layer 107 may include a material selected from the group consisting of...InGaZnO (a-IGZO)”). Note: the claim is noted to have at least one of the materials listed, Vinasco discloses one of the materials).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the composition of the oxide semiconductor layer as taught by Chen by including InxGayZnzO as a composition of the oxide semiconductor layer. One would be motivated to do so as this channel material is “an attractive option to fuel Moore’s law” allowing for high-speed devices [Vinasco, 0003].
As to Claim 5, Chen teaches: The method of claim 1 (Chen, Fig 6 process), wherein the first (Chen, MOLP 52) and second metal oxide layer patterns (Chen, SMOLP 56) includes aluminum oxide (Chen, [0063] “the blocking dielectric layer 52 includes aluminum oxide”, [0068] “tunneling dielectric layer 56 can include…dielectric metal oxides (such as aluminum oxide and hafnium oxide”).
Chen does not explicitly teach: wherein the oxide semiconductor layer pattern includes at least one of InxGayZnzO, InxSnyZnzO, InxZnyO, ZnxO, ZnxSnyO, ZnxOyN, ZrxZnySnzO, HfxInyZnzO, GaxZnySnzO, AlxZnySnzO, or YbxGayZnzO. Chen does disclose an oxide semiconductor layer (OSL 52) with a composition of silicon oxide ([0064]) but does not expressly disclose the composition materials in the instant claim.
However, in an analogous art, Vinasco teaches wherein the oxide semiconductor layer pattern (channel layer 107) includes at least one of InxGayZnzO, InxSnyZnzO, InxZnyO, ZnxO, ZnxSnyO, ZnxOyN, ZrxZnySnzO, HfxInyZnzO, GaxZnySnzO, AlxZnySnzO, or YbxGayZnzO ([0043] “the channel layer 107 may include a material selected from the group consisting of...InGaZnO (a-IGZO)”). (Note: the claim is noted to have at least one of the materials listed, Vinasco discloses one of the materials.)
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the composition of the oxide semiconductor layer as taught by Chen by having the oxide semiconductor layer consist of InxGayZnzO. One would be motivated to do so as this channel material is “an attractive option to fuel Moore’s law” allowing for high-speed devices [Vinasco, 0003].
As to Claim 11, Chen teaches: The method of claim 1 (Chen, Fig. 6 process), further comprising: forming a lower conductive layer pattern (Chen, electrically conductive layers 46) extending in the first direction on the substrate (Chen, (9,10)) (Chen, Fig. 13A, [0120] “A plurality of electrically conductive layers 46 can be formed in the plurality of backside recesses 43”)
Chen does not explicitly teach: forming a pad conductive pattern connected to an uppermost surface of the oxide semiconductor layer pattern; and forming a capacitor on the pad conductive pattern. Chen does disclose an oxide semiconductor layer (Chen, OSL 52) and conductive portions [vertical semiconductor channels 60] formed on the oxide semiconductor layer pattern (Chen, OSLP 52), however, the conductive portions are not formed on the uppermost surface of the oxide semiconductor layer. Additionally, the conductive portions are not the same as a pad conductive pattern that a capacitor is formed on.
However, in an analogous art, Vinasco teaches forming a pad conductive pattern (shared contact electrode 101, first contact electrode 105) connected to an uppermost surface of the oxide semiconductor layer pattern (channel layer 107); and forming a capacitor on the pad conductive pattern (Fig. 13A).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the structure of the memory device as taught by Chen to include a pad conductive pattern formed on the uppermost surface on an oxide semiconductor layer and to form a capacitor on the pad conductive pattern. One would be motivated to do so as a capacitor can be used to store data and hold charge with an ability to represent two-bit values, 0 and 1, respectively discharged or charged (Vinasco, [0011]).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claim(s) 1, 3-4, 17, 19 above, and further in view of Sung et al. (US 20210242012 A1); hereinafter Sung.
As to Claim 7, Chen teaches: The method of claim 1 (Chen, Fig. 6 process), wherein the first metal oxide layer pattern (Chen, MOLP 52) is
Chen does not explicitly teach: formed by introducing a metal precursor onto the preliminary oxide semiconductor layer pattern and reacting the metal precursor with an oxide included in the preliminary oxide semiconductor layer pattern, or by alternately introducing metal precursor and an oxygen agent. Chen does teach preliminary oxide semiconductor layer pattern (POSL 52), first metal oxide layer pattern (MOLP 52), and CVD or ALD as a suitable formation method for a first metal oxide layer pattern.
However, in an analogous art, Sung formed by introducing a metal precursor (metal precursor [0046]) onto the preliminary oxide semiconductor layer pattern (single crystalline semiconductor layer, [0009] “single crystalline semiconductor layer may be a ZnO layer”, [0037] “substrate S may be a single crystalline substrate”) and reacting the metal precursor (metal precursor [0046]) with an oxide in the preliminary oxide semiconductor layer pattern, or by alternately introducing metal precursor and an oxygen agent. (Fig. 1A, [0046] “The reactive gas may react with the metal precursor adsorbed on the substrate S. The reactive gas may be specifically an oxidant which may oxidize the metal precursor to form a metal oxide unit layer”).
(Note: the claim is noted to have two respective methods of either reacting the metal precursor with an oxide in the preliminary oxide semiconductor layer pattern, or by alternatively introducing metal precursor and an oxygen agent, Sung discloses one of those methods.)
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the CVD or ALD formation method for the first metal oxide pattern as taught by Chen by substituting introducing a metal precursor agent and an oxygen agent to a preliminary oxide semiconductor layer pattern to form a first metal oxide pattern. One would be motivated to do so to obtain a lower surface roughness allowing for improved device reliability (Sung, [0053]).
Claim(s) 6,18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen/Sung as applied to claim 7 above, and further in view of Cai et al. (CN 111106061 A); hereinafter Cai.
As to Claim 6, Chen/Sung teaches: The method of claim 1 (Chen, Fig. 6 process), wherein the second metal oxide layer pattern is (Chen, SMOLP 56) formed by introducing a metal precursor (Sung, metal precursor [0046]) onto the preliminary oxide semiconductor layer pattern (Sung, single crystalline semiconductor layer, [0009] “single crystalline semiconductor layer may be a ZnO layer”, [0037] “substrate S may be a single crystalline substrate”) and reacting the metal precursor (Sung, metal precursor [0046]) with an oxide. (Sung, Fig. 1A, [0046]).
Chen/Sung does not explicitly teach: and reacting the metal precursor (conductive material precursor 802) with an oxide included in the preliminary oxide semiconductor layer pattern. Sung does teach forming a metal oxide layer by reacting a metal precursor with an oxygen agent (Sung, [0046]).
However, in an analogous art, Cai teaches and reacting the metal precursor with an oxide included in the preliminary oxide semiconductor layer pattern (Cai, (50)).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the oxidation method as taught by Chen/Sung to oxidize the metal layer formed by the precursor by diffusing elements from an underlying layer to form a metal oxide layer. One would be motivated to do so to control the thickness of the metal oxide layer to be formed (Cai, (50)).
As to Claim 18, Chen/Sung teaches: The method of claim 17 (Chen, Fig. 6 process), wherein the preliminary metal oxide layer pattern (Chen, PMOL 52) is formed by introducing a metal precursor (Sung, metal precursor [0046]) onto the preliminary oxide semiconductor layer pattern (Sung, single crystalline semiconductor layer, [0009] “single crystalline semiconductor layer may be a ZnO layer”, [0037] “substrate S may be a single crystalline substrate”).
Chen/Sung does not explicitly teach: and reacting the metal precursor (conductive material precursor 802) with an oxide included in the preliminary oxide semiconductor layer pattern. Sung does teach forming a metal oxide layer by reacting a metal precursor with an oxygen agent (Sung, [0046]).
However, in an analogous art, Cai teaches and reacting the metal precursor with an oxide included in the preliminary oxide semiconductor layer pattern (Cai, (50)).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the oxidation method as taught by Chen/Sung to oxidize the metal layer formed by the precursor by diffusing elements from an underlying layer to form a metal oxide layer. One would be motivated to do so to control the thickness of the metal oxide layer to be formed (Cai, (50)).
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claim 1, 3-4, 17, 19 above, and further in view of Kang et al. (US 20220285162 A1); hereinafter Kang.
As to Claim 8, Chen/Kang teaches: The method of claim 1 (Chen, Fig. 6a process), wherein after forming the preliminary second metal oxide layer pattern (Chen, PSMOL 56),
Chen does not explicitly teach: forming a second sacrificial layer on the substrate to cover the first structure and the preliminary second metal oxide layer pattern, wherein the second sacrificial layer includes a material substantially the same material composition as a material of the first sacrificial layer pattern, and wherein the first sacrificial layer pattern and the second sacrificial layer are removed together in one or more removal processes. Chen does teach a first structure (PMOL 52, POSL 52, SLP 62), the preliminary second metal oxide layer pattern (PSMOL 56), first sacrificial pattern (SLP 62), and a removal process for a first sacrificial pattern (SLP 62, Fig. 6E-6F).
However, in an analogous art, Kang teaches: forming a second sacrificial layer (third sacrificial dielectric layer 115) on the substrate (101) to cover the first structure, and the preliminary second metal oxide layer pattern (first pad layer 111A, [0045], [0044] “may be formed by an oxide layer”, Fig. 17),
wherein the second sacrificial layer (115) includes a material substantially the same material composition as a material of the first sacrificial layer pattern (first sacrificial dielectric layer 105, [0034] “The first sacrificial dielectric layer 105 may be formed by a spin-on hardmask (SOH) layer” [0066] “The third sacrificial dielectric layer 115 may be formed by a spin-on hardmask (SOH) layer”), and
wherein the first sacrificial layer pattern (105) and the second sacrificial layer (115) are removed together in one or more removal processes (Fig. 13-14, Fig. 17-18, [0055] “In an embodiment of the present disclosure, in step S109, the first sacrificial dielectric layer 105 is removed”, [0085] “performed to remove the third sacrificial dielectric layer to form second pattern structures”).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the silicon oxide composition of the first sacrificial layer as taught by Chen to include a spin-on hard mask material. One would be motivated to do so as it is a known technique used to spread the material to achieve uniform coverage.
As to Claim 9, Chen/Kang teaches: The method of claim 1 (Chen, Fig. 6a process),
Chen does not explicitly teach: wherein the first sacrificial layer pattern includes a spin-on hard mask material. Chen does teach the first sacrificial layer pattern (SLP 62) being made of silicon oxide ([0086]), but does not disclose the spin-on hard mask material in the instant claim.
However, in an analogous art, Kang teaches: wherein the first sacrificial layer pattern (105) includes a spin-on hard mask material ([0034]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the silicon oxide composition of the first sacrificial layer as taught by Chen to include a spin-on hard mask material. One would be motivated to do so as it is a known technique used to spread the material to achieve uniform coverage.
Claim(s) 10, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claim 1, 3-4, 17, 19 above, and further in view of Xi (US20220005686A1); hereinafter Xi.
As to Claim 10, Chen teaches: The method of claim 1 (Chen, Fig. 6a process),
Chen does not explicitly teach: wherein the first sacrificial layer pattern (Chen, SLP 62) is removed by an ashing process and a cleaning process using a cleaning solution. Chen does teach recess etch as a removal method for the first sacrificial layer.
However, in an analogous art, Xi teaches: wherein the first sacrificial layer pattern (mask layer 200) is removed by an ashing process and a cleaning process using a cleaning solution (Fig. 2-4, [0027] “the mask layer 200 are ashed by using a second mixed gas which contains oxygen”, [0028] “the mask layer 200 is removed”, [0029] “the semiconductor structure is cleaned”).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the removal method of a recess etch as taught by Chen to be a removal method by an ashing and cleaning process. One would be motivated to perform an ashing process to prevent residual etching materials from continuing to etch the underlying structures (Xi, [0024]) and to perform a cleaning process to repair defects on the surfaces of the feature portions (Xi, [0030]).
As to Claim 20, Chen teaches: The method of claim 19,
Chen does not explicitly teach: wherein the first sacrificial layer pattern (Chen, SLP 62) is removed by an ashing process and a cleaning process using a cleaning solution. Chen does teach recess etch as a removal method for the first sacrificial layer.
However, in an analogous art, Xi teaches: wherein the first sacrificial layer pattern (mask layer 200) is removed by an ashing process and a cleaning process using a cleaning solution (Fig. 2-4, [0027] “the mask layer 200 are ashed by using a second mixed gas which contains oxygen”, [0028] “the mask layer 200 is removed”, [0029] “the semiconductor structure is cleaned”).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the removal method of a recess etch as taught by Chen to be a removal method by an ashing and cleaning process. One would be motivated to perform an ashing process to prevent residual etching materials from continuing to etch the underlying structures (Xi, [0024]) and to perform a cleaning process to repair defects on the surfaces of the feature portions (Xi, [0030]).
Claim(s) 12-13 is/are rejected under 35 U.S.C 103 as being unpatentable over Chen/Kang as applied to Claims 8-9, and further in view of Hsu et al. (US 9349728 B1); hereinafter Hsu.
As to Claim 12, Chen/Kang teaches: Method for manufacturing a semiconductor device, comprising:
forming first conductive layer patterns (Chen, electrically conductive layers 46) on a substrate (Chen, (9,10)), each of the first conductive layer patterns extending in a first direction parallel to an upper surface of the substrate (Chen, Fig. 13A, [0120])
forming mold insulation patterns (Chen, (32,42)) on the first conductive layer pattern (46), each of the mold insulation patterns (Chen, (32,42)) extending in a second direction parallel to the upper surface of the substrate (Chen, substrate (9,10), [0046], Fig. 3A-4A) and perpendicular to the first direction (Fig. 6A);
forming an oxide semiconductor layer (Chen, OSL 52) conformally on sidewalls and upper surfaces of the mold insulation patterns (Chen, (32,42)) and an upper surface of the first conductive layer pattern (Chen 46) between the mold insulation patterns (Chen, Fig. 6A, Fig. 13A);
forming a first metal oxide layer (Chen, MOL 52) on the oxide semiconductor layer (Chen, OSL 52) to cover the oxide semiconductor layer (Chen, Fig. 6A);
forming a first sacrificial layer (Chen, 622) on the first metal oxide layer (Chen, MOL 52) to fill a trench between the mold insulation patterns (Chen, (32,42), Fig. 6E-6F);
patterning the first sacrificial layer (Chen, 622, [0085]), the first metal oxide layer (Chen, MOL 52, [0095]) and the oxide semiconductor layer (Chen, OSL 52) to form a first structure extending the first direction (Chen, Fig. 6A-6B, Fig. 6E-6F), the first structure including a preliminary first metal oxide layer pattern (Chen, PMOL 52), a preliminary oxide semiconductor layer pattern (Chen, POSL 52) and a first sacrificial layer pattern (Chen, SLP 62) stacked (Chen, Fig. 6E-6F);
forming a preliminary second metal oxide layer pattern (Chen, PSMOL 56) selectively on a sidewall of the preliminary oxide semiconductor layer pattern (Chen, POSL 52, Fig. 6B);
forming a second sacrificial layer (Kang, 115) on the substrate (Kang, 101) to cover the first structure (Chen, Fig. 6A-6B) and the preliminary second metal oxide layer pattern (Kang, 111A, [0045], [0044], Fig.17);
removing the sacrificial layer structure (Kang, first sacrificial dielectric layer 105, 115, [0055]” In an embodiment of the present disclosure, in step S109, the first sacrificial dielectric layer 105 is removed”, Fig. 13-14, [0086] “performed to remove the third sacrificial dielectric layer “, Fig. 23-24); and
forming a second conductive layer pattern (Chen, CLP 54) extending in the second direction on the sidewalls of the mold insulation patterns and on the first and second metal oxide layer patterns (Chen, MOLP 52, SMOLP 56) formed on the sidewalls of the mold insulation patterns (Chen, Fig. 6A-6B).
Chen/Kang does not explicitly teach: planarizing upper portions of the first structure, the second sacrificial layer and the preliminary second metal oxide layer pattern to expose the upper surface of the mold insulation pattern to form an oxide semiconductor layer pattern having a U-shaped cross-section, a first metal oxide layer pattern, a second metal oxide layer pattern covering surfaces of the oxide semiconductor layer pattern, and a sacrificial layer structure on the first and second metal oxide layer patterns.
However, in an analogous art, Hsu teaches: planarizing upper portions of the first structure, the second sacrificial layer and the preliminary second metal oxide layer pattern to expose the upper surface of the mold insulation pattern (Fig. 5, [C.4 L.5-6]“CMP is conducted to remove part of the protective layer 50 and part of the channel layer”) to form an oxide semiconductor layer pattern having a U-shaped cross-section, a first metal oxide layer pattern, a second metal oxide layer pattern covering surfaces of the oxide semiconductor layer pattern, and a sacrificial layer structure on the first and second metal oxide layer patterns (Fig. 5, [C.4 L.11-14]“ “after the planarizing process reveals a U-shaped cross-sectional profile”).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the method of forming a semiconductor device as taught by Chen/Kang to include a planarization step along with a U-shaped cross-section. One would be motivated to do so as planarization allows for even surfaces (Hsu, [C.4 L.9]) and a semiconductor layer having a U-shaped cross-section allows for a fabrication flow if integration is needed (Hsu, [Abstract]).
As to Claim 13, Chen/Kang/Hsu teaches: The method of claim 12, wherein the first and second sacrificial layers include a spin-on hard mask material (Kang, [0034], [066]).
Claim(s) 14 is/are rejected under 35 U.S.C 103 as being unpatentable over Chen/Kang/Hsu as applied to Claims 12-13, and further in view of Xi.
As to claim 14 Chen/Kang/Hsu teaches: The method of claim 12, wherein the sacrificial layer structure (Kang, (105,115)).
Chen/Kang/Hsu does not teach: is removed by an ashing process and a cleaning process using a cleaning solution. Kang teaches removal of the sacrificial layer structure, but does not disclose a specific method.
However, in an analogous art, Xi teaches: is removed by an ashing process and a cleaning process using a cleaning solution (Fig. 2-4, [0027], [0028], [0029]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the removal as taught by Kang to be a removal method by an ashing and cleaning process. One would be motivated to perform an ashing process to prevent residual etching materials from continuing to etch the underlying structures (Xi, [0024]) and to perform a cleaning process to repair defects on the surfaces of the feature portions (Xi, [0030]).
Claim(s) 15 is/are rejected under 35 U.S.C 103 as being unpatentable over Chen/Kang/Hsu as applied to Claim 12-13, and further in view of Sung and Cai.
As to claim 15 Chen/Kang/Hsu teaches: The method of claim 12 (Chen Fig. 6E-6F; Kang elements 105, 115),
Chen/Kang/Hsu does not explicitly teach: is formed by introducing a metal precursor onto the preliminary oxide semiconductor layer pattern and reacting the metal precursor with an oxide included in the preliminary oxide semiconductor layer pattern. Chen discloses a second metal oxide layer pattern (SMOLP, 56) but does not detail the formation.
In an analogous art, Sung teaches: metal oxide layer pattern (metal oxide unit layer) is formed by introducing a metal precursor (Sung, metal precursor, [0046]) onto the preliminary oxide semiconductor layer pattern (Sung, single crystalline semiconductor layer, [0009] “single crystalline semiconductor layer may be a ZnO layer”, [0037] “substrate S may be a single crystalline substrate”).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to supplement a formation method for the second metal oxide pattern as taught by Chen/Kang/Hsu by substituting introducing a metal precursor agent and an oxygen agent to a preliminary oxide semiconductor layer pattern to form a first metal oxide pattern. One would be motivated to do so to obtain a lower surface roughness allowing for improved device reliability (Sung, [0053]).
Chen/Kang/Hsu/Sung does not explicitly teach: reacting the metal precursor with an oxide included in the preliminary oxide semiconductor layer pattern.
In an analogous art, Cai teaches and reacting the metal precursor with an oxide included in the preliminary oxide semiconductor layer pattern (Cai, (50)).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the oxidation method as taught by Chen/Kang/Hsu/Sung to oxidize the metal layer formed by the precursor by diffusing elements from an underlying layer to form a metal oxide layer. One would be motivated to do so to control the thickness of the metal oxide layer to be formed (Cai, (50)).
Claim(s) 16 is/are rejected under 35 U.S.C 103 as being unpatentable over Chen/Kang/Hsu as applied to Claim 12, and further in view of Vinasco.
As to claim 16 Chen/Kang/Hsu teaches: The method of claim 12, further comprising:
Chen does not explicitly teach: forming a pad conductive pattern connected to an uppermost surface of the oxide semiconductor layer pattern; and forming a capacitor on the pad conductive pattern. Chen does disclose an oxide semiconductor layer (Chen, OSL 52) and conductive portions [vertical semiconductor channels 60] formed on the oxide semiconductor layer pattern (Chen, OSLP 52), however, the conductive portions are not formed on the uppermost surface of the oxide semiconductor layer. Additionally, the conductive portions are not the same as a pad conductive pattern that a capacitor is formed on.
However, in an analogous art, Vinasco teaches forming a pad conductive pattern (shared contact electrode 101, first contact electrode 105) connected to an uppermost surface of the oxide semiconductor layer pattern (channel layer 107); and forming a capacitor on the pad conductive pattern (Fig. 13A).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the structure of the memory device to include a pad conductive pattern formed on the uppermost surface on an oxide semiconductor layer and to form a capacitor on the pad conductive pattern. One would be motivated to do so as a capacitor can be used to store data and hold charge with an ability to represent two-bit values 0 and 1, respectively discharged or charged (Vinasco, [0011]).
Conclusion
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/MASHAL AHMED/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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