DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This non-final office action is responsive to Applicants' application filed on 04/05/24. Claims 1-20 are presented for examination and are pending for the reasons indicated herein below.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7-13 and 18 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dias (US 20180342951 A1)
Regarding method claims 1-5, 7-8, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device "inherently performs the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated.
Regarding claim 9. Dias teaches a control circuit [fig 3] for a power converter [¶19] comprising N power stage circuits coupled in parallel, wherein N is a positive integer, the control circuit comprising:
an enable unit [330 with 340] configured to control an operation mode of the power converter [output of 20];
and b) a pulse shielding unit [350, output of 350 delays (disables) pulse to turn on switches to charge inductor current, 315s] configured to disable at least one pulse in a first trigger signal for controlling each phase power stage circuit in the power converter to start [fig 4 transition to ] operating when the power converter enters a first operating mode [fig 4, high load mode], in order to reduce a fluctuation amplitude of the output signal [implicit since delay helps mitigate unwanted charge of inductor current, ¶34-¶35].
Regarding claim 10. Dias teaches the control circuit of claim 9, wherein: a) the pulse of the first trigger signal is enabled in a time interval when an output voltage is less than a threshold signal [delay happens after step 1110 in fig 11]; and b) at least one pulse in the first trigger signal is disabled in a time interval when the output voltage is not less than the threshold signal [during low load fig 4 shows a delay pulse when output is below threshold].
Regarding claim 11. Dias teaches the control circuit of claim 9, wherein the enable unit comprises a comparator configured to compare an output voltage of the power converter against a first threshold [function of 330], wherein: a) when the output voltage rises above the first threshold, an enable signal is generated and is active to control the power converter to enter the first operating mode [i.e. output of 330]; and b) when an output voltage drops below the first threshold, the enable signal is inactive to control [function of 340, ¶55] the power converter to enter a second operation mode [low power mode].
Regarding claim 12. Dias teaches the control circuit of claim 9, wherein the pulse shielding unit is configured to select the number of pulses in the first trigger signal to be disabled [function of device], and to disable the corresponding number of pulses to generate a second trigger signal when the power converter enters the first operation mode [section rsiSlp shows a gap before entering high load mode].
Regarding claim 13. Dias teaches the control circuit of claim 9, wherein the pulse shielding unit is configured to select the number of pulses to be disabled according to a difference between an output voltage [330 indirectly controls 350] of the power converter and the first threshold, such that the number of pulses to be shielded is larger [interpreted as pulses having a larger duty cycle] when the difference is larger [1030 is larger than 1020 during right side event of fig 10].
Regarding claim 18. Dias teaches the control circuit of claim 9, comprising: a) a logic distribution unit [340 with drivers] configured to sequentially distribute the pulses [function of drivers] of a second trigger signal generated by disabling at least one pulse in the first trigger signal to each phase power stage circuit [305/310] when the power converter is in the first operation mode [340 sends pulses in all modes]; and b) wherein when the power converter is in the second operation mode, the pulses of the first trigger signal are sequentially distributed to each phase power stage circuit, in order to control an operation timing of each phase power stage circuit [implicit claim 16 method is applied to multi-phase operation].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 14 rejected under 35 U.S.C. 103 as being unpatentable over Dias (US 20180342951 A1) in view of Shiraishi et al. (US 20130214751 A1)
Regarding claim 14. Dias teaches the control circuit of claim 9.
However, Dias does not explicitly mention a circuit wherein the pulse shielding unit comprises a counting module controlled by an enable signal generated by the enable unit to count the pulses in the first trigger signal, and configured to activate a first indication signal when a count value is not less than a count threshold.
Shiraishi teaches a circuit wherein the pulse shielding unit comprises a counting module [41-43 fig 12] controlled by an enable signal [phase, fig 12] generated by the enable unit to count the pulses in the first trigger signal, and configured to activate a first indication signal [¶81-¶83] when a count value is not less than a count threshold [i.e. when 0 counts threshold].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the features of Shiraishi in order to provide an improvement in response speed to load change and a reduction in ripple amplitude.
Claims 6 and 20 rejected under 35 U.S.C. 103 as being unpatentable over Dias (US 20180342951 A1) in view of Peretz (US 20220294343 A1)
Regarding method claim 6, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device "inherently performs the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated.
Regarding claim 20. Dias teaches the control circuit of claim 9.
However, Dias does not explicitly mention a circuit further comprising a feedback control circuit configured to generate the first trigger signal for controlling each phase power stage circuit to start operating according to a feedback signal representing an output voltage and a current sampling signal representing a total inductor current through loop compensation.
Shiraishi teaches a circuit further comprising a feedback control circuit [fig 1, see fb by voltage sensor] configured to generate the first trigger signal [i.e. delay signal by DL-ADC] for controlling each phase power stage circuit to start operating according to a feedback signal [output of voltage sensor] representing an output voltage and a current sampling signal [output of current sensor] representing a total inductor current through loop compensation.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the features of Shiraishi in order to provide a digital controller for high-performance multiphase buck VRM, including current balancing modules that enable even load distribution between the phases [¶6].
Allowable Subject Matter
Claims 15-17 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if the claim objections stated above were overcome.
Examiner Note
The examiner cites particular columns and lines numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bryan Perez whose telephone number is (571)272-8837. The examiner can normally be reached on Mon.-Fri. (7:30 – 5:00).
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Monica Lewis, can be reached on (571) 272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://portal.uspto.gov/external/portal. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/BRYAN R PEREZ/Examiner, Art Unit 2838