Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Amendment
This Office action is in response to Applicant's communication filed August 20, 2025 in response to the Office action dated May 20, 2025.
Claims 1,2,11,12,15, and 19 have been amended. Claims 1-20 are pending in this application.
NOTE:
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art reference and any interpretations of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP 2123.
Specification
In view of Applicant’s amendment, objections to the specification are withdrawn.
Claim Rejections - 35 USC § 102
In view of Applicant’s amendment, 102 rejections are withdrawn
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et. al., U.S Patent Pub No. 2019/0220396 (hereinafter Lin) in view of Na et. al., U.S Patent Pub No. 2022/0197560 (hereinafter Na).
Regarding Claim 1, Lin teaches a storage device comprising: a non-volatile memory device configured to store data in a data area and metadata corresponding to the data in a spare area distinguished from the data area (Fig.1, 3; Para18-20 "Furthermore, there is a spare area for each physical page to store metadata."); and a memory controller configured to perform a translation operation of translating a logical address received from an outside to a physical group address, receive first metadata and second metadata different from each other from the non-volatile memory device based on the physical group address (Fig.3-5A, Para18-20 "The mapping between LBA of data (arranged by a host) and a location/address ( e.g. a physical address) allocated to store the data is recorded into a logical-to-physical mapping table L2P for data management." Para24-27 "For example, the microcontroller 320 has the functionality of a flash translation layer (FTL)." Para31-33), and perform an index check operation of selecting a piece of the metadata corresponding to the logical address from the first metadata and the second metadata (Fig.4, 5A"check map" Para5-6,30-31 "the control unit 302 may built a check map to label each entry, that can be mapped to the group mapping table L2P G, in the mapping table P2L_S of the source block GC_S").
However, Lin fails to teach but Na teaches the physical group address being mapped to a plurality of logical address, the plurality of logical address including the logical address received from the outside (Fig.4,11;Para5 "a command schedule controller configured to search for a first physical address group in response to a scheduling event signal from the command generation controller, the first physical address group including at least one second physical address including a page number that corresponds to a physical address stored in the first read command queue" Para72-73).
Lin and Na are analogous art because they are from the same field of endeavor. They both relate to data management in a storage system.
Therefore, before the effective filling date of claimed invention was made, it would have been obvious to a person of ordinary skill in the art to modify the above method, as taught by Lin, and incorporating the read command processing, as taught by Na.
One of ordinary skill in the art would have been motivated to do this modification in order to utilize known method of data processing, as suggested by Na (Para2-6).
Regarding claim 9, the combination of Lin and Na teaches all the limitations of the base claims as outlined above.
Further, Lin teaches wherein the first metadata contains a first logical block address, and the index check operation includes comparing the logical address and the first logical block address (Fig.1, 4; Para33, 39-40"the content (e.g.,LBA#Ox0l000OO0) of the selected second entry are compared with the physical address (e.g., PBA#Ox000l0OO0)and the logical address (LBA#0x0lO00000) of the group logical-to-physical table L2P G#256 to determine whether the mapping relationships match each other").
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Um et. al., U.S Patent Pub No. 2022/0171569 (hereinafter Um) in view of Na et. al., U.S Patent Pub No. 2022/0197560 (hereinafter Na).
Regarding Claim 11 Um teaches a storage device comprising: a non-volatile memory device configured to store first data, first metadata corresponding to the first data, second data different from the first data, and second metadata corresponding to the second data (Fig.2, 3,4; Para7-9 "the first FTL core configured to write first user data from the host device and second metadata in one among the plurality of first nonvolatile memories, and the second metadata is related to second user data stored in the plurality of second nonvolatile memories" Para58-61, 63-65); and
a memory controller that includes a flash translation layer containing first mapping information in which a first logical address corresponding to the first metadata and a physical group address are mapped with each other and second mapping information in which a second logical address corresponding to the second metadata and the physical group address are mapped with each other(Fig.2-5; Para7-9 "In an embodiment of the present disclosure, a data storage device may include: a nonvolatile memory device which includes a first nonvolatile memory group including a plurality of first nonvolatile memories coupled to a first flash translation layer (FTL) core and a second nonvolatile memory group including a plurality of second nonvolatile memories coupled to a second FTL core" Para44-49, 65-67,70-73).
However, Um fails to teach but Na teaches the physical group address being mapped to a plurality of logical address, the plurality of logical address including the first logical address and the second logical address (Fig.4,11;Para5 "a command schedule controller configured to search for a first physical address group in response to a scheduling event signal from the command generation controller, the first physical address group including at least one second physical address including a page number that corresponds to a physical address stored in the first read command queue" Para72-73).
Um and Na are analogous art because they are from the same field of endeavor. They both relate to data management in a storage system.
Therefore, before the effective filling date of claimed invention was made, it would have been obvious to a person of ordinary skill in the art to modify the above method, as taught by Um, and incorporating the read command processing, as taught by Na.
One of ordinary skill in the art would have been motivated to do this modification in order to utilize known method of data processing, as suggested by Na (Para2-6).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Parry et. al., U.S Patent Pub No. 2023/0051212 (hereinafter Parry) in view of Na et. al., U.S Patent Pub No. 2022/0197560 (hereinafter Na).
Regarding Claim 19 Parry teaches an electronic system comprising: a host device configured to send a read command and a logical address (Fig.1, 5;para12-13 "a host system coupled with the memory system may reference data (e.g., if issuing read, write, or other commands associated with the data) using logical addresses (e.g., logical block addresses (LBAs), virtual addresses, system addresses, or other logical addresses)"); and a storage device configured to receive the read command and the logical address, translate the logical address to a physical group address, read a plurality of logical block addresses stored in advance in association with the physical group address, in response to the read command, and send data corresponding to one logical block address corresponding to the logical address among the plurality of logical block addresses, to the host device (Fig. 1,3-5; Para12-14 "The memory system may store the mapping between logical addresses and physical addresses in a mapping or a table (e.g., a logical-to-physical (L2P) mapping or L2P table) which may be updated if changes are made to the logical or physical addresses" read command is translated and data is sent to host Para22-23, 40-42,69-70 "During a read operation, the memory system may compare the logical address included in the read command with the logical address included in the metadata as a validation check that the read data is correct.").
However, Parry fails to teach but Na teaches the physical group address being mapped to a plurality of logical address, the plurality of logical address including the logical address (Fig.4,11;Para5 "a command schedule controller configured to search for a first physical address group in response to a scheduling event signal from the command generation controller, the first physical address group including at least one second physical address including a page number that corresponds to a physical address stored in the first read command queue" Para72-73).
Parry and Na are analogous art because they are from the same field of endeavor. They both relate to data management in a storage system.
Therefore, before the effective filling date of claimed invention was made, it would have been obvious to a person of ordinary skill in the art to modify the above method, as taught by Parry, and incorporating the read command processing, as taught by Na.
One of ordinary skill in the art would have been motivated to do this modification in order to utilize known method of data processing, as suggested by Na (Para2-6).
Claims 2, 3, 5, 6, are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Na as applied to claim 1 above, further in view of Parry et. al., U.S Patent Pub No. 2023/0051212 (hereinafter Parry).
Regarding claim 2, the combination of Lin and Na teaches all the limitations of the base claims as outlined above.
However, Lin and Na fails to teach but Parry teaches wherein the memory controller is configured to send a read command for data corresponding to the piece of metadata selected from the first and second metadata, to the non-volatile memory device (Fig.1,5; Para11-12, 14 "the memory system may receive a command to read an L2P entry that may point directly to a physical address, or may point to an entry of the L2L table" Para69-70,92-93).
Lin, Na, and Parry are analogous art because they are from the same field of endeavor. They all relate to data management in a storage system.
Therefore, before the effective filling date of claimed invention was made, it would have been obvious to a person of ordinary skill in the art to modify the above method, as taught by Lin and Na, and incorporating the read command processing, as taught by Parry.
One of ordinary skill in the art would have been motivated to do this modification in order to utilize known method of data processing, as suggested by Parry (Para11-12).
Regarding claim 3, the combination of Lin, Na, and Parry teaches all the limitations of the base claims as outlined above.
Further, Parry teaches wherein the physical group address corresponds to a first plane of the non-volatile memory device (Fig.1,4; Para30-32 "Each die 160 may include one or more planes 165, and each plane 165 may include a respective set of blocks 170, where each block 170 may include a respective set of pages 175, and each page 175 may include a set of memory cells.").
Regarding claim 5, the combination of Lin, Na, and Parry teaches all the limitations of the base claims as outlined above.
Further, Lin teaches wherein the non-volatile memory device is configured to store first data corresponding to the first metadata and second data corresponding to the second metadata, and perform a sequential write operation on the first plane in an order of the first metadata, the second metadata, and the first data (Fig.5A,B,7; Para42-43 "In Step S512, data from labeled and valid second entries is sequentially copied to a destination block").
Regarding claim 6, the combination of Lin, Na, and Parry teaches all the limitations of the base claims as outlined above.
Further, Lin teaches wherein the memory controller is configured to perform a check operation on the first metadata after a read operation on the first and second metadata (Fig.4, 5A"check map" Para5-6,30-31).
Claims 4, 7, 8, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Parry, in view of Na as applied to claim 3 above, further in view of Kaneko et. al., U.S Patent Pub No. 2024/0176537 (hereinafter Kaneko).
Regarding claim 4, the combination of Lin, Na, and Parry teaches all the limitations of the base claims as outlined above.
However, the combination fails to teach but Kaneko teaches wherein the physical group address contains channel information, bank information, block information, physical-page information, and plane information on the first plane (Fig.2,3, Para48-49 "a physical address may be represented by, for example, a channel number, a bank number, a plane identifier, a block address, a page address, and an offset address in a page").
Lin, Na, Parry, and Kaneko are analogous art because they are from the same field of endeavor. They all relate to data management in a storage system.
Therefore, before the effective filling date of claimed invention was made, it would have been obvious to a person of ordinary skill in the art to modify the above method, as taught by Lin, Na, and Parry, and incorporating the physical address, as taught by Kaneko.
One of ordinary skill in the art would have been motivated to do this modification in order to utilize more efficient approach of data management, as suggested by Kaneko (Para3-6).
Regarding claim 7, the combination of Lin, Na, and Parry teaches all the limitations of the base claims as outlined above.
Further, Kaneko teaches wherein the physical group address contains bank information, block information, physical-page information, plane information, and index information(Fig.2,3, Para48-49 "a physical address may be represented by, for example, a channel number, a bank number, a plane identifier, a block address, a page address, and an offset address in a page").
Regarding claim 8, the combination of Lin, Na,Parry, and Kaneko teaches all the limitations of the base claims as outlined above.
Further, Kaneko teaches wherein the memory controller is configured to receive the first metadata through a first channel, and receive the second metadata through a second channel different from the first channel (Fig.2-4; Para48-49, 82-83 "the NAND flash interface 316 writes data in parallel in a maximum of twelve NAND flash chips (the number of parallel writes=12)").
Regarding claim 10, the combination of Lin, Na, and Parry teaches all the limitations of the base claims as outlined above.
Further, Kaneko teaches wherein the memory controller is configured to receive hash data corresponding to the logical address, from the outside, the first metadata contains first hash data, and the index check operation includes comparing the hash data and the first hash data (Fig.2-3; Para311 "When the logical address corresponding to the missing data is searched for from the read history table 3121, the logical address is hashed and referred to the corresponding memory position, and is determined to be a hit when there is valid data").
Claims 12-18, are rejected under 35 U.S.C. 103 as being unpatentable over Um in view of Na as applied to claim 11 above, further in view of Lin et. al., U.S Patent Pub No. 2019/0220396 (hereinafter Lin).
Regarding claim 12, the combination of Um and Na teaches all the limitations of the base claims as outlined above.
However, Um and Na fails to teach but Lin teaches wherein the non-volatile memory device is configured to receive the physical group address from the memory controller, read the first metadata and the second metadata based on the physical group address, perform an index check operation of selecting the first metadata and the second metadata based on a logical address provided from an outside, and send one of the first and second data to the memory controller based on the index check operation(Fig.4, 5A"check map" Para5-6,30-31 "the control unit 302 may built a check map to label each entry, that can be mapped to the group mapping table L2P G, in the mapping table P2L_S of the source block GC_S" Para36-38).
Um, Na, and Lin are analogous art because they are from the same field of endeavor. They all relate to data management in a storage system.
Therefore, before the effective filling date of claimed invention was made, it would have been obvious to a person of ordinary skill in the art to modify the above method, as taught by Um and Na, and incorporating the index check, as taught by Lin.
One of ordinary skill in the art would have been motivated to do this modification in order to utilize known method of data processing, as suggested by Lin (Para4-7).
Regarding claim 13, the combination of Um, Na, and Lin teaches all the limitations of the base claims as outlined above.
Further Lin teaches wherein the non-volatile memory device includes a control logic that is configured to perform the index check operation(Fig.4, 5A"check map" Para5-6,30-31 "the control unit 302 may built a check map to label each entry, that can be mapped to the group mapping table L2P G, in the mapping table P2L_S of the source block GC_S"36-38).
Regarding claim 14, the combination of Um, Na, and Lin teaches all the limitations of the base claims as outlined above.
Further Lin teaches wherein the control logic is configured to recess the logical address, and perform the index check operation based on the logical address(Fig.4, 5A"check map" Para5-6,30-31,36-38 ).
Regarding claim 15, the combination of Um, Na, and Lin teaches all the limitations of the base claims as outlined above.
Further Lin teaches wherein the memory controller is configured to receive the first metadata and the second metadata based on the first mapping information and the second mapping information, and perform an index check operation of selecting the first metadata and the second metadata based on a logical address received from an outside, and the non-volatile memory device is configured to send one of the first and second data to the memory controller based on the index check operation(Fig.4, 5A"check map" Para5-6,30-31,36-38 ).
Regarding claim 16, the combination of Um, Na, and Lin teaches all the limitations of the base claims as outlined above.
Further Lin teaches wherein when performing a read operation on the first data, the memory controller is configured to perform an index check operation on the first metadata between a read operation on the first metadata and a read operation on the second metadata(Fig.4, 5A"check map" Para5-6,30-31,36-38 ).
Regarding claim 17, the combination of Um, Na, and Lin teaches all the limitations of the base claims as outlined above.
Further Lin teaches wherein the physical group address corresponds to a first plane of the non-volatile memory device, and when a sequential write operation on the first plane is performed, the sequential write operation is performed in an order of the first metadata, the first data, and the second metadata(Fig.5A,B,7; Para42-43 "In Step S512, data from labeled and valid second entries is sequentially copied to a destination block").
Regarding claim 18, the combination of Um, Na, and Lin teaches all the limitations of the base claims as outlined above.
Further Lin teaches wherein the memory controller is configured to send a read command based on the index check operation(Fig.4, 5A"check map" Para5-6,30-31,36-38).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Parry in view of Na as applied to claim 19 above, further in view of Lin et. al. U.S Patent Pub No. 2019/0220396 (hereinafter Lin).
Regarding claim 20, the combination of Parry and Na teaches all the limitations of the base claims as outlined above.
However, Parry and Na fails to teach but Lin teaches wherein a size of the data is 4 kB (Fig.1 Para45-46 " Using the buffer 225 to temporarily store data during transfers may allow data to be buffered as commands are being processed, thereby reducing latency between commands and allowing arbitrary data sizes associated with commands.") or use Lin(Fig.3 Para18-19 "one memory cell may be 4 KB").
Parry, Na, and Lin are analogous art because they are from the same field of endeavor. They all relate to data management in a storage system.
Therefore, before the effective filling date of claimed invention was made, it would have been obvious to a person of ordinary skill in the art to modify the above method, as taught by Parry and Na, and incorporating the data size, as taught by Lin.
One of ordinary skill in the art would have been motivated to do this modification in order to utilize known method of data processing, as suggested by Lin (Para4-7).
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot in view of the new grounds of rejection above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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TASNIMA . MATIN
Primary Examiner
Art Unit 2135
/TASNIMA MATIN/Primary Examiner, Art Unit 2135
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