DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
Claims 1-9, and 11-19 have been amended.
This action is Final.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1, 4-11, and 14-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Khatri et al. (hereinafter as Khatri) PGPUB 2015/0338896.
As per claim 1, Khatri teaches a device [FIG. 1: management controller 110] comprising one or more circuits to:
receive measurements from two or more interconnect devices [FIG. 1 and 0029 processing nodes 150A-D (interconnect devices); and 0044: (power management module 120 within management controller 110 receives power usage data and workload data from several node controllers 160 of each processing node)];
determine, based on the measurements, a power consumption of each interconnect device from the two or more interconnect devices relative to the two or more interconnect devices [0044: (power usage data (power consumption) of each processing node (interconnect device) is obtained) and 0041: (some processing nodes are allocated a higher power consumption level than other processing nodes (relative to the two or more interconnect devices)];
generate, based on the power consumption of each interconnect device relative to the two or more interconnect devices, respective power instructions for each interconnect device from the two or more interconnect devices [0044: (current node power consumption for each processing node A-D within the IHS is received and a total available system power 313 of the IHS is determined; based on the power consumption, a power threshold (power instruction) is determined for each of the processing nodes)]; and
allocate power between the two or more interconnect devices by distributing the respective power instructions to each interconnect device from the two or more interconnect devices [0044 and 0053: (micro-controller 122 of management controller 110 provides the power thresholds to the respective node controllers of each processing node to trigger them to set CPU peak power limits based on the power threshold; the triggering is the allocation power process, and it is performed by providing the processing node with its respective power threshold)].
As per claim 4, Khatri teach the device of claim 1, wherein the one or more circuits are further to receive data associated with one or more throttling mechanisms performed by at least one of the two or more interconnect devices, wherein the respective power instructions are generated further based on the data associated with one or more throttling mechanisms [0031 and 0036-0037: (firmware has data to perform dynamic peak power limiting of processing nodes and the peak power limits are provided to node controllers to perform the dynamic peak power limiting)].
As per claim 5, Khatri teach the device of claim 4, wherein, in response to distributing the respective power instructions, a rate of throttling occurrences across the two or more interconnect devices is reduced [0031 and 0036: (frequency is adjusted according to the provided power limits; throttling would be reduced when there are fewer peak power limits are provided)].
As per claim 6, Khatri teach the device of claim 1, wherein the one or more circuits are further to determine an average power consumption over a period of time for each interconnect device from the two or more interconnect devices [0033 and 0038].
As per claim 7, Khatri teach the device of claim 6, wherein the power consumption comprises an average power consumption of each interconnect device from the two or more interconnect devices over time [0038 and 0041].
As per claim 8, Khatri teach the device of claim 1, wherein in response to distributing the respective power instructions to each interconnect device from the two or more interconnect devices, more power is allocated to one or more interconnect devices of the two or more interconnect devices than other interconnect devices of the two or more interconnect devices [FIG. 4A: (different power limits and allocations provided to different nodes, thus more power is allocated to one than another)].
As per claim 9, Khatri teach the device of claim 8, wherein one or more of bandwidth of traffic, packet rates, and compute operations across the one or more interconnect devices increase relative to the other interconnect devices [FIG. 4A: (different power limits and allocations provided to different nodes and thus power consumption of one compute operation on one processing node is increased relative to another processing node)].
As per claim 10, Khatri teach the device of claim 1, wherein the measurements comprise one or more of power measurements and performance measurements [0033: (measure, track, and record power consumed as power usage data)].
Claim 11 is similar in scope to claim 1 as addressed above and is thus rejected under the same rationale.
Claim 14 is similar in scope to claim 4 as addressed above and is thus rejected under the same rationale.
Claim 15 is similar in scope to claim 5 as addressed above and is thus rejected under the same rationale.
Claim 16 is similar in scope to claim 6 as addressed above and is thus rejected under the same rationale.
Claim 17 is similar in scope to claim 7 as addressed above and is thus rejected under the same rationale.
Claim 18 is similar in scope to claim 1 as addressed above and is thus rejected under the same rationale.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 2-3, 12-13, and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Khatri et al. (hereinafter as Khatri) PGPUB 2015/0338896, and further in view of Huang et al. (hereinafter as Huang) PGPUB 2018/0307288.
As per claim 2, Khatri teach the device of claim 1, wherein each interconnect device from the two or more interconnect devices performs a workload for a computing device [0033: (workload for each of the processing nodes and each of the CPUs within each processing node of IHS)].
Khatri does not teach wherein in response to distributing the respective power instructions to each interconnect device from the two or more interconnect devices, differences in one or more of bandwidth of traffic, packet rates, and compute operations across the two or more interconnect devices are reduced.
Huang also teaches a plurality of processing nodes and allocation of power to the nodes by a management controller [0043 and FIG. 1]. Huang is thus similar to Khatri because they teach a management controller that controls the amount of power used by the processing nodes. Huang further teaches wherein in response to distributing the respective power instructions to each interconnect device from the two or more interconnect devices, differences in one or more of bandwidth of traffic, packet rates, and compute operations across the two or more interconnect devices are reduced [0044 and FIG. 3: (after performing power balancing process, power of the different nodes converge to 350W for each of the nodes; thus each power balancing process reduces the differences in power draw of computational operations between the nodes)].
The combination of Khatri with Huang yields Khatri providing power thresholds for each of the processing nodes such that after several iteration, they converge to a common power consumption.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Huang’s teachings of reducing the differences in power consumption for computing operations between each processing node in Khatri. One of ordinary skill in the art would have been motivated to reduce the difference in power consumption between processing nodes in Khatri because it allows for a fair balancing of power between different processing nodes when there is high demand from all the processing nodes but insufficient power supply, thus providing efficient balancing of power between multiple nodes [Huang 0006].
As per claim 3, Khatri and Huang teach the device of claim 2, wherein the one or more circuits are further to store the respective power instructions for each interconnect device from the two or more interconnect devices in memory [FIG. 1 and FIG. 2: (power management module 120 of management controller stores node peak power limits for each processing node)] and associate the respective power instructions with one or more applications executed by the computing device [0032 and 0062: (the peak power limits commands are provided to node controllers of each processing node which uses programmable logic/software for implementing power management application)].
Claim 12 is similar in scope to claim 2 as addressed above and is thus rejected under the same rationale.
Claim 13 is similar in scope to claim 3 as addressed above and is thus rejected under the same rationale.
Claim 19 is similar in scope to claim 2 as addressed above and is thus rejected under the same rationale.
Claim 20 is similar in scope to claim 3 as addressed above and is thus rejected under the same rationale.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 11, and 18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim et al. (PGPUB 2023/0009853) teaches power allocation to peripheral devices, and that some peripheral devices may be permitted to consume more power than another device [0014].
Fossati et al. (PGPUB 2020/0089296) teaches a power allocator that adjusts power allocation to display device and peripheral device based on measured power use at the display device [0040].
Varma et al. (PGPUB 2016/0239068) teaches allocation power to different devices using power messages [claim 11].
Fossati et al. (PGPUB 2013/0305064) teaches adjusting power allocation to monitor and peripheral device.
Ernohazy et al. (PGPUB 2022/0116235) teaches providing power to device relative to one or more other devices in a network [0174 and 0176].
Rong et al. (PGPUB 2020/0019230) teaches updating a respective power budget for each of multiple computing nodes and sending to each node a respective power budget rule.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANNY CHAN whose telephone number is (571)270-5134. The examiner can normally be reached Monday - Friday 10-7 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J. Jung can be reached at 5712703779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANNY CHAN/Primary Examiner, Art Unit 2175
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