This action is in response to the amendments filed on 11/06/2025, in which claims 1-20 are presented for the examination.
Allowable Subject Matter
Claims 13-14 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 15-18 are allowed.
Response to Arguments
Applicant's arguments filed 11/06/2025 have been fully considered but they are not persuasive.
Applicant respectfully submits the cited references do not teach or suggest a controller that is configured to "apply first error correction decoding to the first data to obtain second data ...; and apply the second error correction decoding to the second data," as claimed.
Response:
Examiner respectfully disagrees. Yang teaches in Fig. 1 including LDPC decoder 120 applies ECC to incoming data (i e , “DATA”), decoding controller 130 may output error-corrected data DATA_C to a second external device, DATA_C is considered as second data as claimed.
After the adjusting the error rate (Fig. 2, step 150, arrow goes back to S120 and the entire process from S120-160 is reiterated), output at S160 after first iteration is considered as third data as claimed.
Thus, examiner believes Yang teaches a controller that is configured to "apply first error correction decoding to the first data to obtain second data ...; and apply the second error correction decoding to the second data," as claimed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang (US 2019/0190539, referred herein after Yang).
As per claim 1, Yang discloses a storage device comprising:
a nonvolatile memory device (Fig. 3, memory 110); and
a controller (Fig. 3, controller 130) configured to:
receive first data from the nonvolatile memory device (Fig. 2, step S110, data received, [0032]);
apply first error correction decoding (Fig. 1, LDPC 120 decoder applies ECC to incoming data) to the first data (Fig. 1, [0028], DATA), to obtain second data (Fig. 1, DATA_C, [0030], decoding controller 130 may output error-corrected data DATA_C to a second external device, DATA_C is considered as second data);
control an error correction capability and an error detection capability of second error correction decoding based on information about the first error correction decoding; and (Fig. 2, step S150, [0035], decoding parameter adjusted);
apply the second error correction decoding to the second data based on the error correction capability and the error detection capability to obtain third data (Fig. 2, step S120-S160, [0035], “Afterwards, the process proceeds to operation S120, in which LDPC decoding is again iterated. If it is determined in operation S140 that an error does not exist, the adaptive decoding controller 130 may output error-corrected data DATA_C to the second external device in operation S160.”, after the adjusting the error rate, decoding process reiterates from steps S120-S160, output at S160 after first iteration is considered as third data as claimed).
As per claim 5, Yang discloses the storage device of claim 1, wherein the controller comprises a Low Density Parity Check (LDPC) decoder configured to perform the first error correction decoding, and wherein the information about the first error correction decoding comprises structural information about the LDPC decoder ([0097]-[0098]).
As per claim 19, Yang discloses a method of operating a storage device which includes a nonvolatile memory device (Fig. 3, memory 110); and a controller (Fig. 3, controller 130), the method comprising:
applying, by the controller, Low Density Parity Check (LDPC) decoding (Fig. 1, LDPC 120 decoder applies ECC to incoming data) to first data (Fig. 1, [0028], DATA) transferred from the nonvolatile memory device to obtain second data (Fig. 1, DATA_C, [0030], decoding controller 130 may output error-corrected data DATA_C to a second external device, DATA_C is considered as second data);
controlling, by the controller, an error correction capability and an error detection capability of polar code Successive Cancelation List (SCL) decoding, based on decoding information about the LDPC decoding (Fig. 2, step S150, [0035], decoding parameter adjusted);
applying, by the controller, the polar code SCL decoding to the second data based on the error correction capability and the error detection capability to obtain third data (Fig. 2, step S120-S160, [0035], “Afterwards, the process proceeds to operation S120, in which LDPC decoding is again iterated. If it is determined in operation S140 that an error does not exist, the adaptive decoding controller 130 may output error-corrected data DATA_C to the second external device in operation S160.”, after the adjusting the error rate, decoding process reiterates from steps S120-S160, output at S160 after first iteration is considered as third data as claimed).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2-4, 6 are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Jang et al. (US 2021/0013902, referred herein after Jang).
As per claim 2, Yang does not specifically disclose the storage device of claim 1, wherein the second error correction decoding comprises polar code Successive Cancelation List (SCL) decoding;
However, Jang discloses the second error correction decoding comprises polar code Successive Cancelation List (SCL) decoding (Fig. 9A, [0321]-[0322]);
Therefore it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Jang’s method to transmit and receive signal in communication system into Yang’s error correction device because one of the ordinary skill in the art would have been motivated to provide significant improvements in error correction performance compared to simpler methods.
As per claim 3, Jang discloses the storage device of claim 2, wherein the third data comprises information bits, a frozen bit, and dynamic frozen bits, and wherein the controller is further configured to control which of the dynamic frozen bits is used for error correction and which of the dynamic frozen bits is used for error detection ([0048], [0084]-[0085]).
As per claim 4, Jang discloses the storage device of claim 3, wherein the controller is further configured to increase the error correction capability by controlling a dynamic frozen bit having a preceding position, from among the dynamic frozen bits used for the error detection, to be used for the error correction ([0105], [0118]-[0119]).
As per claim 6, Yang does not specifically disclose the storage device of claim 1, wherein the controller comprises a Low Density Parity Check (LDPC) decoder configured to perform the first error correction decoding, and wherein the information about the first error correction decoding indicates a degree of each of variable nodes of an LDPC code of the LDPC decoder;
However, Jang discloses controller comprises a Low Density Parity Check (LDPC) decoder configured to perform the first error correction decoding, and wherein the information about the first error correction decoding indicates a degree of each of variable nodes of an LDPC code of the LDPC decoder ([0027]-[0028], [0063]);
Therefore it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Jang’s method to transmit and receive signal in communication system into Yang’s error correction device because one of the ordinary skill in the art would have been motivated to provide significant improvements in error correction performance compared to simpler methods.
As per claim 20, Yang does not specifically disclose the method of claim 19, further comprising: performing, by the controller, the LDPC decoding with respect to the third data; modifying, by the controller, the error correction capability and the error detection capability; and performing, by the controller, the polar code SCL decoding;
However, Jang discloses performing, by the controller, the LDPC decoding with respect to the third data; modifying, by the controller, the error correction capability and the error detection capability; and performing, by the controller, the polar code SCL decoding (Fig. 9A, [0321]-[0322]);
Therefore it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Jang’s method to transmit and receive signal in communication system into Yang’s error correction device because one of the ordinary skill in the art would have been motivated to provide significant improvements in error correction performance compared to simpler methods.
Claims 7-11 are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Zhang et al. (US 2018/0076929, referred herein after Zhang).
As per claim 7, Yang discloses the storage device of claim 1, wherein the controller comprises a Low Density Parity Check (LDPC) decoder (Fig. 1, LDPC decoder 120) configured to perform the first error correction decoding, and
Yang does not specifically disclose the information about the first error correction decoding indicates a number of cycles of the LDPC decoder;
However, Zhang discloses the information about the first error correction decoding indicates a number of cycles of the LDPC decoder ([0041], [0102], [0107]-[0108]);
Therefore it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Zhang’s method for encoding data using polar decoding into Yang’s error correction device because one of the ordinary skill in the art would have been motivated to improve overall transmission capacity.
As per claim 8, Yang discloses the storage device of claim 1, wherein the controller comprises a Low Density Parity Check (LDPC) decoder (Fig. 1, LDPC decoder 120) configured to perform the first error correction decoding,
Yang does not specifically disclose the wherein the information about the first error correction decoding indicates a length of a cycle of the LDPC decoder;
However, Zhang discloses the information about the first error correction decoding indicates a length of a cycle of the LDPC decoder ([0107], [0108]);
Therefore it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Zhang’s method for encoding data using polar decoding into Yang’s error correction device because one of the ordinary skill in the art would have been motivated to improve overall transmission capacity.
As per claim 9, Yang discloses the storage device of claim 1, wherein the first error correction decoding comprises LDPC (Low Density Parity Check) decoding Fig. 1, LDPC decoder 120), and
Yang does not specifically disclose the information about the first error correction decoding comprises status information about the LDPC decoding;
However, Zhang discloses the information about the first error correction decoding comprises status information about the LDPC decoding ([0107], [0108]);
Therefore it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Zhang’s method for encoding data using polar decoding into Yang’s error correction device because one of the ordinary skill in the art would have been motivated to improve overall transmission capacity.
As per claim 10, Yang discloses the storage device of claim 1, wherein the first error correction decoding comprises Low Density Parity Check (LDPC) decoding (Fig. 1, LDPC decoder 120) performed using check nodes,
Yang does not specifically disclose the information about the first error correction decoding indicates a number of the check nodes not satisfying a check condition;
However, Zhang discloses the information about the first error correction decoding indicates a number of the check nodes not satisfying a check condition ([0113]-[0116]);
Therefore it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Zhang’s method for encoding data using polar decoding into Yang’s error correction device because one of the ordinary skill in the art would have been motivated to improve overall transmission capacity.
As per claim 11, Yang discloses the storage device of claim 1, wherein the first error correction decoding comprises Low Density Parity Check (LDPC) decoding,
Yang does not specifically disclose the information about the first error correction decoding indicates a number of iterations of the LDPC decoding;
However, Zhang discloses the information about the first error correction decoding indicates a number of iterations of the LDPC decoding ([0099]-[0104]);
Therefore it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Zhang’s method for encoding data using polar decoding into Yang’s error correction device because one of the ordinary skill in the art would have been motivated to improve overall transmission capacity.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Chen et al. (US 2019/0042356, referred herein after Chen).
As per claim 12, Yang discloses the storage device of claim 1, wherein the first error correction decoding comprises Low Density Parity Check (LDPC) decoding,
Yang does not specifically disclose the information about the first error correction decoding indicates a syndrome weight of the LDPC decoding;
However, Chen discloses the information about the first error correction decoding indicates a syndrome weight of the LDPC decoding ([0012], [0034], [0040]);
Therefore it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Chen’s data access method into Yang’s error correction device because one of the ordinary skill in the art would have been motivated to reduce a number of re-read operations and potentially avoid data recovery operations.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KAMINI B PATEL/ Primary Examiner, Art Unit 2114