DETAILED ACTION
1. This office action is in response to communication filed on 01/08/2026. Claims 3, 7 and 11 have been amended. Claims 1-12 are pending on this application.
Response to Arguments
2. Applicant's arguments filed 01/08/2026 with respect to claims 1, 5 and 9 have been fully considered but they are not persuasive.
Under remarks applicant argued Hurwitz fails to teach “"pre- conditioning the comparator by maintaining a constant voltage across non-linear capacitors of the comparator during a sampling phase of the comparator" as recited in Claim 1, 5 and 9 from the following reasons:
First, Hurwitz’s "short both comparator inputs to Vinit" equalizes charge at a single node; it does not maintain constant terminal-to-terminal voltages across the comparator input device's non-linear capacitors during the sampling phase. Shorting the two comparator input pins to a common potential does not control, let alone hold constant, the voltages between the gate, source, drain, and bulk of the differential input pair transistors (e.g., Vgs, Vgd, Vds). The sources of the input devices in a regenerative comparator are not at Vinit when the inputs are shorted; they are set by internal biasing/tail current and device operation. Consequently, the parasitic capacitors resident "across" those device terminals do not experience a maintained constant voltage during sampling. At most, Hurwitz sets an initial, equalized charge condition at the comparator input pins; it is not the claimed constant-across-the-parasitic pre-conditioning of the comparator input device during the sampling phase.
Second, Hurwitz's technique is a pin-level initial condition applied while the comparator is decoupled from actual signal sampling. Hurwitz explicitly uses separate sampling capacitors (e.g., Cblk, Cwht) to hold the pixel values, and in all conversion modes the comparator compares the top plates of those external sampling capacitors while their bottom plates are driven (by SAR or ramp). Thus, Hurwitz's "sampling" when it shorts both inputs to Vinit is not sampling of the analog input onto the comparator input device, much less in a manner that bootstraps the device terminals to keep Vgs/Vgd/Vds constant. The comparator in Hurwitz is not used as a top-plate sampling element; rather, external sampling capacitors perform the sampling. By contrast, claims 1 and 7 recite a "top-plate sampled comparator" and a pre-conditioning that is implemented at the comparator so that the voltages across its internal non-linear capacitors are kept constant during the sampling phase.
Third, Hurwitz seeks to equalize-or approximate-parasitic charge at the instant of sampling and to match end-of-conversion state by judicious choice of Vinit (e.g., set Vinit= Vrst). It does not disclose maintaining those parasitic device voltages constant "during a sampling phase." Hurwitz's own rationale recognizes that the parasitic capacitances are state-dependent and that its mitigation idea is to ensure equal initial charge at sampling; nothing in Hurwitz describes, suggests, or requires continuously maintaining constant terminal-to-terminal voltages across the comparator's non-linear capacitors throughout the sampling interval, which is the specific pre-conditioning recited in Claims 1, 5, and 9.
Examiner respectful disagrees from the following:
For the first reason: the argument “hold constant, the voltages between the gate, source, drain, and bulk of the differential input pair transistors (e.g., Vgs, Vgd, Vds) are not in the claimed invention; therefore, Fig. 10 of Hurwitz discloses applying a constant voltage Vinit across two non-linear capacitor C1 and C2 of comparator 40 for maintain a constant voltage VC1(0) = VC2(0) across two non-linear capacitor C1 and C2 of the comparator 40 during sampling (paragraph 0089 discloses “shorted to Vinit during sampling”).
For the second reason the argument “sampling of the analog input onto the comparator input device, much less in a manner that bootstraps the device terminals to keep Vgs/Vgd/Vds constant such that d a pre-conditioning that is implemented at the comparator so that the voltages across its internal non-linear capacitors are kept constant during the sampling phase” are not in the claimed invention.
For the third reason, Fig. 10 of Hurwitz clearly discloses maintaining constant terminal-to-terminal voltages (maintaining Constant Vinit at Positive terminal and Negative terminal C1 and C2 of comparator 40) across the comparator's non-linear capacitors (C1 and C2) throughout the sampling interval (paragraph 0089 discloses “shorted to Vinit during sampling”).
As explained above, applicant fails to distinct the pre-condition arrangement of comparator in claims 1, 5 and 9 of application over the pre-condition arrangement of comparator Hurwitz.
Applicant needs to distinct precondition of the comparator of claimed invention by “during sample phase by coupling an analog input signal to gate, drain, and source of a transistor of the comparator” in the claimed invention (1, 5, and 9) to overcome precondition arrangement comparator of Hurwitz.
Fig. 10 of Hurwitz clearly discloses a precondition of a comparator 40 with non-linearity capacitors C1 and C2 (paragraph 0089 discloses “the non-linearity in the parasitic capacitors”); by applied a constant voltage Vinit (paragraph 0090 discloses “Vinit should be set equal to Vrst”) across non-linear capacitors (C1, C2 to obtain VC1(0) = VC2(0)) at input terminals of comparator 40 during sampling (paragraph 0089 discloses “shorted to Vinit during sampling”) as recited in Claim 1, 5 and 9.
Accordingly, the rejections under 35 U.S.C. § 102 of claims 1, 5 and 9 and dependent claims 2- 4, 6-8, and 10-12 are sustained in this office action.
Claim Objections
3. Claims 3, 7 and 11 objected to because of the following informalities: “the input of comparator” in each claim should be change to - - an input of comparator- - for proper antecedent basis.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
5. Claims 1- 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hurwitz et al. Pub. No. 2019/0115931.
Regarding claim 1. Figs. 3-and 10 of Hurwitz et al. a method for maintaining sampling linearity (paragraph 0051 discloses “correction factor can be linear or non-linear”) in a top-plate sample (top-plate of capacitors CBLK, CWHT) comparator (40), comprising: pre-conditioning the comparator (precondition of 40) by maintaining a constant voltage (paragraph 0090 discloses “Vinit should be set equal to Vrst”) across non-linear capacitors (C1, C2 in Fig. 10; paragraph 0089 discloses “the non-linearity in the parasitic capacitors at the input of the comparator circuit. To reduce the charge error to zero, the charge stored in both parasitic input capacitances must be equal at sampling. To meet the condition VC1(0) = VC2(0), both inputs of the comparator circuit 40 can be shorted to Vinit during sampling. Shorting the inputs of the comparator circuit 40 to Vinit can cause an equal charge to be stored at C.sub.1 and C.sub.2 during sampling”) of the comparator (40) during a sampling phase (paragraph 0089 discloses “shorted to Vinit during sampling”) of the comparator (40).
Regarding claim 2. The method of Claim 1, Figs 3 and 10 of Hurwitz et al. further discloses wherein maintaining the constant voltage (Vinit) across non-linear capacitors (C1, C2 in Fig. 10; paragraph 0089 discloses “the non-linearity in the parasitic capacitors at the input of the comparator circuit. To reduce the charge error to zero, the charge stored in both parasitic input capacitances must be equal at sampling. To meet the condition VC1(0) = VC2(0), both inputs of the comparator circuit 40 can be shorted to Vinit during sampling. Shorting the inputs of the comparator circuit 40 to Vinit can cause an equal charge to be stored at C1 and C.2 during sampling”) of the comparator (40) during a sampling phase (paragraph 0089 discloses “shorted to Vinit during sampling”) of the comparator (40) comprises sampling an analog input signal (input signal from COL) to the comparator (40) onto all terminals of an input device (+ and - terminal input devices of 40) of the comparator (40).
Regarding claim 3. The method of Claim 1, Fig. 10 further discloses wherein maintaining the constant voltage (paragraph 0090 discloses “Vinit should be set equal to Vrst”) across non-linear capacitors (C1, C2) of the comparator (40) during a sampling phase (paragraph 0089 discloses “shorted to Vinit during sampling”) of the comparator (40) comprises coupling non-input terminals of an input device (non-input terminals of switching in Fig. 10) of the comparator (40 in Fig. 10) to the input of the comparator (+/- input terminals compactors 40) .
Regarding claim 4. The method of Claim 1, Fig. 3 and Fig. 10 of Hurwitz et al. further disclose wherein maintaining the constant voltage (Vinit) across non-linear capacitors (C1, C2 in Fig. 10; paragraph 0089 discloses “the non-linearity in the parasitic capacitors at the input of the comparator circuit. To reduce the charge error to zero, the charge stored in both parasitic input capacitances must be equal at sampling. To meet the condition VC1(0) = VC2(0), both inputs of the comparator circuit 40 can be shorted to Vinit during sampling. Shorting the inputs of the comparator circuit 40 to Vinit can cause an equal charge to be stored at C.sub.1 and C.sub.2 during sampling”) of the comparator (40) during a sampling phase (paragraph 0089 discloses “shorted to Vinit during sampling”) of the comparator (40) comprises coupling all terminals of an input device (controlling terminals of input switching device in Fig. 10) of the comparator (40) to a top plate (top-plate of capacitors CWHT) of a reference digital-to-analog converter (DAC 36 in Fig. 3) of a successive approximation register analog-to-digital converter (SAR ADC of Fig. 3; paragraph 0013).
Regarding claim 5. Figs. 3-and 10 of Hurwitz et al. discloses top-plate (top-plate of capacitors CBLK, CWHT) of sampled comparator (40) comprising: sampling transistors (transistors are implicit to comparator because transistors are the fundamental building blocks of a comparator, which compares two input voltages and outputs a signal indicating which is higher); sampling switches (sampling switching of Vint in Fig. 10; ); non-linear capacitors (C1, C2 in Fig. 10; paragraph 0089 discloses “the non-linearity in the parasitic capacitors at the input of the comparator circuit. To reduce the charge error to zero, the charge stored in both parasitic input capacitances must be equal at sampling. To meet the condition VC1(0) = VC2(0), both inputs of the comparator circuit 40 can be shorted to Vinit during sampling. Shorting the inputs of the comparator circuit 40 to Vinit can cause an equal charge to be stored at C1 and C.2 during sampling); and circuitry (switching circuitry of Fig. 10) configured to pre-condition (precondition of the comparator 40 in Fig. 10) by maintaining a constant voltage (paragraph 0090 discloses “Vinit should be set equal to Vrst”) across non-linear capacitors (C1, C2 in Fig. 10; paragraph 0089 discloses “the non-linearity in the parasitic capacitors at the input of the comparator circuit. To reduce the charge error to zero, the charge stored in both parasitic input capacitances must be equal at sampling. To meet the condition VC1(0) = VC2(0), both inputs of the comparator circuit 40 can be shorted to Vinit during sampling. Shorting the inputs of the comparator circuit 40 to Vinit can cause an equal charge to be stored at C.sub.1 and C.sub.2 during sampling”) of the comparator (40) during a sampling phase (paragraph 0089 discloses “shorted to Vinit during sampling”) of the comparator (40) in order to maintain sampling linearity (paragraph 0051 discloses “correction factor can be linear or non-linear”) of the comparator (40).
Regarding claim 6. The top-plate sampled comparator of Claim 5, Fig. 3 and Fig. 10 further disclose wherein maintaining the constant voltage (Vinit) across non-linear capacitors (C1, C2 in Fig. 10; paragraph 0089 discloses “the non-linearity in the parasitic capacitors at the input of the comparator circuit. To reduce the charge error to zero, the charge stored in both parasitic input capacitances must be equal at sampling. To meet the condition VC1(0) = VC2(0), both inputs of the comparator circuit 40 can be shorted to Vinit during sampling. Shorting the inputs of the comparator circuit 40 to Vinit can cause an equal charge to be stored at C.sub.1 and C.sub.2 during sampling”) of the comparator (40) during a sampling phase (paragraph 0089 discloses “shorted to Vinit during sampling”)) of the comparator (40) comprises sampling (BLK and WHT in Fig. 3) an analog input signal (input signal from COL in Fig. 3) to the comparator (40) onto all terminals of an input device (input and output terminals of switching device in Fig. 10) of the comparator (40 in Fig. 10).
Regarding claim 7. The top-plate sampled compactor of Claim 5, Fig. 10 further discloses wherein maintaining the constant voltage (paragraph 0090 discloses “Vinit should be set equal to Vrst”) across non-linear capacitors (C1, C2) of the comparator (40) during a sampling phase (paragraph 0089 discloses “shorted to Vinit during sampling”) of the comparator (40) comprises coupling non-input terminals of an input device (output terminals of switching in Fig. 10) of the comparator (40 in Fig. 10) to the input of the comparator (+/- input terminals compactors 40).
Regarding claim 8. The top-plate sampled comparator of Claim 5, Fig. 3 and Fig. 10 further discloses wherein maintaining the constant voltage (Vinit) across non-linear capacitors (C1, C2 in Fig. 10; paragraph 0089 discloses “the non-linearity in the parasitic capacitors at the input of the comparator circuit. To reduce the charge error to zero, the charge stored in both parasitic input capacitances must be equal at sampling. To meet the condition VC1(0) = VC2(0), both inputs of the comparator circuit 40 can be shorted to Vinit during sampling. Shorting the inputs of the comparator circuit 40 to Vinit can cause an equal charge to be stored at C1 and C2 during sampling”) of the comparator (40) during a sampling phase (paragraph 0089 discloses “shorted to Vinit during sampling”) of the comparator (40) comprises coupling all terminals of an input device (+/- input terminals) of the comparator(40) to a top plate (top-plate of capacitor CWHT) of a reference digital-to-analog converter (DAC 36 in Fig. 3) of a successive approximation register analog-to-digital converter (SAR ADC of Fig. 3; paragraph 0013).
Regarding claim 9. Fig. 3 and Fig. 10 of Hurwitz et al. discloses a successive approximation register analog-to-digital converter ( paragraph 0013 disclose SAR ADC of Fig. 3) comprising: a reference digital-to-analog converter (DAC 36); a successive approximation register (34); and a top-plate (top plate of CBLK) sampled comparator (40) configured to compare a reference signal (POS signal ) generated by the reference digital-to-analog converter (36) to an analog input signal (analog signal NEG) in order to generate a comparator output (output of 40) to the successive approximation register (34), the comparator (40) comprising: sampling transistors (transistors is implicit to comparator 40 because transistors are the fundamental building blocks of a comparator, which compares two input voltages and outputs a signal indicating which is higher); sampling switches (sampling switches in Fig. 10) ; non-linear capacitors (C1, C2 in Fig. 10; paragraph 0089 discloses “the non-linearity in the parasitic capacitors at the input of the comparator circuit. To reduce the charge error to zero, the charge stored in both parasitic input capacitances must be equal at sampling. To meet the condition VC1(0) = VC2(0), both inputs of the comparator circuit 40 can be shorted to Vinit during sampling. Shorting the inputs of the comparator circuit 40 to Vinit can cause an equal charge to be stored at C.sub.1 and C.sub.2 during sampling”); and circuitry (switching circuitry of Fig. 10) configured to pre-condition (short to Vinit) the comparator (40) by maintaining a constant voltage (Vint) across non-linear capacitors (C1, C2 in Fig. 10; paragraph 0089 discloses “the non-linearity in the parasitic capacitors at the input of the comparator circuit. To reduce the charge error to zero, the charge stored in both parasitic input capacitances must be equal at sampling. To meet the condition VC1(0) = VC2(0), both inputs of the comparator circuit 40 can be shorted to Vinit during sampling. Shorting the inputs of the comparator circuit 40 to Vinit can cause an equal charge to be stored at C.sub.1 and C.sub.2 during sampling”) of the comparator (40) during a sampling phase (paragraph 0089 discloses “shorted to Vinit during sampling”) of the comparator (40) in order to maintain sampling linearity (paragraph 0051 discloses “correction factor can be linear or non-linear”) of the comparator (40).
Regarding claim 10. The successive approximation registers analog-to-digital converter of Claim 9, Fig. 3 and Fig. 10 further disclose wherein maintaining the constant voltage (V1) across non-linear capacitors (C1, C2 in Fig. 10; paragraph 0089 discloses “the non-linearity in the parasitic capacitors at the input of the comparator circuit. To reduce the charge error to zero, the charge stored in both parasitic input capacitances must be equal at sampling. To meet the condition VC1(0) = VC2(0), both inputs of the comparator circuit 40 can be shorted to Vinit during sampling. Shorting the inputs of the comparator circuit 40 to Vinit can cause an equal charge to be stored at C.sub.1 and C.sub.2 during sampling”) of the comparator (40) during a sampling phase of the comparator (paragraph 0089 discloses “shorted to Vinit during sampling” of comparator 40) comprises sampling an analog input signal (analog signal COL in Fig. 3) to the comparator (40) onto all terminals of an input device (+ and – input device) of the comparator).
Regarding claim 11. The successive approximation registers analog-to-digital converter of Claim 9, Fig. 10 further disclose wherein maintaining the constant voltage (paragraph 0090 discloses “Vinit should be set equal to Vrst”) across non-linear capacitors (C1, C2) of the comparator (40) during a sampling phase (paragraph 0089 discloses “shorted to Vinit during sampling”) of the comparator (40) comprises coupling non-input terminals of an input device (output terminals of switching device in Fig. 10) of the comparator (40 in Fig. 10) to the input of the comparator (+/- input terminals compactors 40)
Regarding claim 12. The successive approximation registers analog-to-digital converter of Claim 9, Fig. 3 and Fig. 10 further disclose wherein maintaining the constant voltage across non-linear capacitors C1, C2 in Fig. 10; paragraph 0089 discloses “the non-linearity in the parasitic capacitors at the input of the comparator circuit. To reduce the charge error to zero, the charge stored in both parasitic input capacitances must be equal at sampling. To meet the condition VC1(0) = VC2(0), both inputs of the comparator circuit 40 can be shorted to Vinit during sampling. Shorting the inputs of the comparator circuit 40 to Vinit can cause an equal charge to be stored at C.sub.1 and C.sub.2 during sampling”) of the comparator during a sampling phase of the comparator comprises coupling all terminals of an input device of the comparator to a top plate of a reference digital-to-analog converter of a successive approximation register analog-to-digital converter.
Conclusion
6. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 8:30 – 5:00 Monday-Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications.
03/21/2026
/LINH V NGUYEN/Primary Examiner, Art Unit 2845
Prosecution Insights