DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The present application is being examined under the claims filed 02/11/2026. Claims 1, 8, and 15 have been amended. Claims 1-20 are pending. Claims 1-20 are rejected.
Response to Arguments
I. Applicant's arguments filed 02/11/2026 have been considered but are moot due to the
new grounds of rejection, as well as the newly cited portions of the references previously presented.
II. No additional arguments were made as to the dependent claims, and as such, the rejection is maintained.
Claim Objections
Claim 1 is objected to because of the following informalities:
Regarding Claim 1, line 5 includes the word “and”, even though the limitation is no longer the penultimate entry in the list. Examiner notes that this error is not present in amended independent claims 8 and 15.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1- 5, 8- 12, and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2006/0288243 A1) in view of Ulmer et. al. (US 2013/0073884 A1) [previously cited].
Regarding Claim 1, Kim discloses a method (Kim par. 57, method for controlling the power of a multi-core processor) comprising:
monitoring, by a processor of an information handling system (Kim FIG 1, automatic power-mode control apparatus 200 [i.e., processor] including monitoring unit 230), a relative state of charge of a battery of the information handling system (Kim par. 29, conditions monitored by monitoring unit 230 include the remaining power of an associated battery);
modifying a user-selectable […] table mode based on the relative state of charge of the battery (Kim FIG. 3 and par. 45, threshold values for the remaining power of battery are set in order to control the processor mode of the multi-core processor based on the remaining power of battery, and may be changed depending on computer system, and may be set to different values by the user [i.e., user selectable]; and Kim par. 49, existing mode is replaced with the set mode; and Kim par. 44, the interrelationship between monitored conditions and modes is stored in a memory device, such as a look-up table [i.e., table modes]); and
transmitting, by the processor of the information handling system, a portable code to disable a processor core of a central processing unit of the information handling system (Kim par. FIG. 1 and 42, automatic power-mode control apparatus 200 [i.e., processor] includes automatic mode change unit 220, which controls the power supplied to each core based on the selected processor mode (see par. 40, modes involve operating a portion of the cores, therefore mode switching requires some cores be disabled) and through the power control unit 240 connected to each core; [also see instant app. par. 31, embedded optimizer 215 may provide feedback also referred to as a portable code (p-code) hint to control framework 250 to enable or disable a specific processor and/or processor cores, i.e., control command from power-mode apparatus 200 is a portable code]) in response to detecting that the relative state of charge of the battery is equal to a threshold percentage (Kim par. 45, battery power rangers are based on the number of operated cores; also see par. 46, e.g., "in the case of the multi-core processor including three cores, the processor mode may be set to mode # 1 so as to operate only one core when the remaining power of battery is less than 30%"; and Kim par. 31, embedded optimizer 215 may be configured to automatically adjust a number of processor and/or processor cores based on a set of criteria that includes the RSOC of battery [i.e., change mode in response to detecting]); and
subsequent to the transmitting of the portable code to disable the processor core of the central processing unit of the information handling system, removing hardware affinity of the processor core […] (Kim FIG. 3 and par. 39, modes for the processor include operating only one core, operating a portion of cores, or operating all cores [i.e., non-operating cores are disabled, and not running]; [see instant application par. 44, "method proceeds to block 540 where the operating system may provide a p-code hint to the processor scheduler that the processor cores with the removed hardware affinity may no longer be part of the schedule", i.e., disabling and not scheduling cores is removing hardware affinity]).
Kim does not explicitly teach:
modifying a user-selectable thermal table mode;
subsequent to the transmitting of the portable code to disable the processor core of the central processing unit of the information handling system, removing hardware affinity of the processor core with one or more threads;
In the analogous art of power saving methods in information handling systems (Ulmer par. 2), Ulmer teaches:
modifying a […] thermal table mode based on [expected power savings given the current device condition] (Ulmer par. 154, a table lookup algorithm may be implemented by the low power resource mode selections solver [note: table is thermal because temperature effects on potential power savings are used as a parameter, see par. 22]; and Ulmer par. 80, the solver is used to determine which low power modes for the various resources should be entered [e.g., global modes c & d]);
subsequent to the transmitting of the portable code to disable the processor core of the central processing unit of the information handling system, removing hardware affinity of the processor core with one or more threads (Ulmer par. 86 and 89, cores send a sleep set [i.e., notification] to indicate entering a sleep mode; and par. 56, operating system honors core state when scheduling; and Ulmer par. 54, active state may indicate that an operating system is actively scheduling threads on the core [i.e. cores have one or more threads]);
Therefore, it would have been obvious of one of ordinary skill in the art, having the teachings of Kim and Ulmer before him, before the effective filing date of the claimed invention, to combine Kim’s method for selecting processor modes based on battery charge level with Ulmer’s use of a thermal table and method of disabling a multi-threaded processor, the motivation being to account for temperature affecting power drain (Ulmer par. 22, account for temperature effects on potential power saving) and further tailor processor modes to account for power consumption (Ulmer par. 2, a mobile device's battery life and power consumption characteristics are becoming ever more important considerations for consumers of mobile devices) respectively.
Regarding Claim 2, Kim in view of Ulmer discloses the method of claim 1, further comprising notifying an operating system of the information handling system to park the processor core (Ulmer par. 53, parked modules include a node power architecture (NPA) resource on each respective core that allows an operating system to indicate whether a core is “active” or “parked”; and par. 41, operating systems are configured to block and wait for cores to enter sleep mode).
Therefore, it would have been obvious of one of ordinary skill in the art, having the teachings of Kim and Ulmer before him, before the effective filing date of the claimed invention, to combine Kim’s method for selecting processor modes based on battery charge level with Ulmer’s notifying an operating system, the motivation being to allow functionality on a greater number of systems (Ulmer par. 151, the method described does not require a process that resides above the sleep process to monitor the cores (as required by other operating systems), and does not require the cores to block and wait until all the global resources are idle (as required by other operating systems)).
Regarding Claim 3, Kim in view of Ulmer discloses the method of claim 1, further comprising determining a processor core type to be disabled. The method of claim 1, further comprising determining a processor core type to be disabled (Ulmer par. 37, the processing cores may be heterogeneous and/or implement different functions (also see par. 31, SOC 200 may include a number of heterogeneous processors, such as a digital signal processor (DSP) 202, a modem processor 204, a graphics processor 206, and an application processor 208, each of which may include one or more cores); and par. 49, the dynamic sleep framework may identify the core(s) to which each low power resource (LPR) applies [i.e., a type of processor core] and place the cores that correspond to the LPR into a low power/sleep mode).
Regarding Claim 4, Kim in view of Ulmer discloses the method of claim 1, further comprising determining a number of processor cores to be disabled (Kim FIG. 3 and par. 46, based on the battery charge level, a different number of processor cores are disabled).
Regarding Claim 5, Kim in view of Ulmer discloses the method of claim 1, further comprising notifying an operating system that the processor core is offline (Ulmer par. 86 and 89, cores send a sleep set [i.e., notification] to indicate entering a sleep mode; and par. 56, operating system honors core state when scheduling).
The same motivation that was utilized for combining Kim and Ulmer as set forth in claim 2 is equally applicable to claim 5.
Regarding Claim 8, Kim discloses an information handling system (Kim FIG. 1 and par. 26, a portable computer system), comprising:
a battery (Kim par. 38, monitoring unit 230 continuously checks the remaining power of the battery);
a central processing unit including a plurality of processor cores (Kim FIG 1, processor 100 with cores 101, 103, 105); and
a processor to communicate with the battery (Kim par. 38, monitoring unit 230 [which is part of mode control apparatus 200, i.e., processor] continuously checks the remaining power of the battery), the processor to:
transmit a first portable code to modify a user-selectable […] table mode based in response to a detection that a relative state of charge of the battery is equal to a threshold percentage (Kim FIG. 3 and par. 45, threshold values for the remaining power of battery are set in order to control the processor mode of the multi-core processor based on the remaining power of battery, and may be changed depending on computer system, and may be set to different values by the user [i.e., user selectable]; and Kim par. 44, interrelationship between monitored conditions and modes is stored in a memory device, such as a look-up table [i.e., table modes]; [also see instant app. par. 31, embedded optimizer 215 may provide feedback also referred to as a portable code (p-code) hint to control framework 250 to enable or disable a specific processor and/or processor cores, i.e., control command from power-mode apparatus 200 is a portable code]); and
transmit a second portable code to disable one a processor core of the processor cores of the central processing unit based on the relative state of charge of the battery (Kim par. FIG. 1 and 42, automatic power-mode control apparatus 200 [i.e., processor] includes automatic mode change unit 220, which controls the power supplied to each core based on the selected processor mode and through the power control unit 240 connected to each core; [see instant app. par. 31, embedded optimizer 215 may provide feedback also referred to as a portable code (p-code) hint to control framework 250 to enable or disable a specific processor and/or processor cores]; and Kim par. 31, embedded optimizer 215 may be configured to automatically adjust a number of processor and/or processor cores based on a set of criteria that includes the RSOC of battery [i.e., change mode in response to detecting battery charge]);
The remaining limitations of claim 8 are similar in scope to claim 1 as addressed above and are thus rejected under the same rationale.
Regarding Claim 9, the claim is similar in scope to claim 2 as addressed above and is thus rejected under the same rationale.
Regarding Claim 10, the claim is similar in scope to claim 3 as addressed above and is thus rejected under the same rationale.
Regarding Claim 11, the claim is similar in scope to claim 4 as addressed above and is thus rejected under the same rationale.
Regarding Claim 12, the claim is similar in scope to claim 5 as addressed above and is thus rejected under the same rationale.
Regarding Claim 15, Kim discloses a non-transitory computer-readable medium to store instructions that are executable to perform operations (Kim par. 17, a computer-readable recording medium stores a computer-executable program code to cause a computer to control a power management mode of a multi-core processor).
The remaining limitations of claim 15 are similar in scope to claim 1 as addressed above and are thus rejected under the same rationale.
Regarding Claim 16, the claim is similar in scope to claim 2 as addressed above and is thus rejected under the same rationale.
Regarding Claim 17, the claim is similar in scope to claim 3 as addressed above and is thus rejected under the same rationale.
Regarding Claim 18, the claim is similar in scope to claim 5 as addressed above and is thus rejected under the same rationale.
Claims 6-7, 13-14, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Ulmer, further in view of Bhandaru et. al. (US 2019/0317585 A1) [previously cited].
Regarding Claim 6, Kim in view of Ulmer discloses the method of claim 1.
Kim in view of Ulmer does not explicitly disclose further comprising in response to detecting a system reboot of the information handling system, enabling the processor core.
In the analogous art of independently managing processor cores of a multicore processor for power saving, Bhandaru teaches:
further comprising in response to detecting a system reboot of the information handling system, enabling the processor core (Bhandaru par. 35-38, on system reboot, the ACPI tables [specify power states for each core, see par. 15] and the SPD flag [specify to operate cores independently or in single p-state, see par. 26] are read once [i.e., at system reboot, the operating states of the cores are set to their original ACPI mapping, i.e. enabled]).
Therefore, it would have been obvious of one of ordinary skill in the art, having the teachings of Kim, Ulmer, and Bhandaru before him, before the effective filing date of the claimed invention, to combine Kim and Ulmer’s method of enabling and disabling processor cores with Bhandaru’s use of tables to initialize processor cores at boot, the motivation being to further optimizing a system for maximum performance at minimum power consumption during the boot process (Bhandaru par. 4).
Regarding Claim 7, Kim in view of Ulmer discloses the method of claim 1.
Kim in view of Ulmer discloses a scheduler processor map (Ulmer par. 71, sleep_lpr node 452 [i.e., scheduler processor map] is used identify specific cores to which a low power mode applies, including sleep state; and par. 56, operating system honors core state when scheduling).
Kim in view of Ulmer does not explicitly disclose in response to detecting a system reboot, resetting a scheduler processor map.
In the analogous art of independently managing processor cores of a multicore processor for power saving, Bhandaru teaches:
further comprising in response to detecting a system reboot, resetting a processor map (Bhandaru par. 35-38, on system reboot, power states for all cores are reset using a ACPI map).
Therefore, it would have been obvious of one of ordinary skill in the art, having the teachings of Wang, Ulmer, and Bhandaru before him, before the effective filing date of the claimed invention, to combine Wang and Ulmer’s data structure storing processor modes for scheduling with Bhandaru’s use of tables to reset processor core power states at boot, resulting in a reset to the scheduler map utilized by the operating system for thread scheduling; the motivation of setting the core power states at boot being to further optimizing a system for maximum performance at minimum power consumption during the boot process (Bhandaru par. 4).
Regarding Claim 13, the claim is similar in scope to claim 6 as addressed above and is thus rejected under the same rationale.
Regarding Claim 14, the claim is similar in scope to claim 7 as addressed above and is thus rejected under the same rationale.
Regarding Claim 19, the claim is similar in scope to claim 6 as addressed above and is thus rejected under the same rationale.
Regarding Claim 20, the claim is similar in scope to claim 7 as addressed above and is thus rejected under the same rationale.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLE JIAWEI WENTZEL whose telephone number is (703) 756-4762. The examiner can normally be reached 9:30am-5:30pm ET (Mon-Fri).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached on (571) 270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.J.W./Examiner, Art Unit 2175
/ANDREW J JUNG/Supervisory Patent Examiner, Art Unit 2175