DETAILED ACTION
Drawings
The drawings are objected to because figures 1, 4, 5, 12, 14, and 16-21 appear to be missing lines along the top and/or right edges. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lo (US 2020/0098803).
As to claims 1 and 14, Lo teaches a photodetector (annotated fig. 2 below) manufactured using a high-voltage CMOS technology ([0018]), the photodetector comprising:
a monocrystalline silicon substrate (102) having a top surface, a substrate conductivity type and a substrate doping concentration ([0019], and [0024]);
a medium-voltage well region (108) having a first conductivity type (p), extending into said semiconductor substrate to a first depth (d1) from said top surface ([0022]);
a first high-voltage well region (114) having a second conductivity type (n), extending into said semiconductor substrate from said first depth to a second depth (d2) from said top surface, said second depth (d2) being larger than said first depth (d1), forming a first active metallurgical p-n junction with said medium-voltage well region ([0026]); and
a buried layer (112) having a second conductivity type (n), substantially distant from said top surface, forming a first isotype metallurgical junction with said first high-voltage well region at a distance D from said top surface, said distance D being larger than said first depth ([0024]).
Lo does not explicitly teach said first active metallurgical p-n junction produces a built-in electric field, said electric field having a depth-dependent intensity profile and said electric field profile having a maximum between 0.2D and 0.8D when measured from said top surface, or
wherein said photodetector is characterized by a Dark Count Rate (DCR) lower than 0.25 Hz per micrometer square at an excess voltage of 5 V and at a temperature of 300 K.
However, lines 1-11 on p. 10 and lines 15-23 on p. 11 of the specification in the instant application implies that the distance of the p-n junction affects the vertical electric field and lines 24-29 of p. 11 implies that the voltage and temperature chosen affect the DCR.
That is, determining the appropriate depths to fabricate the layers and the ideal voltages and temperatures to apply to the contacts affects the electric field and the DCR.
Furthermore, the Applicant has not shown that anything other than modifying these values leads to the electric field maximum and DCR values claimed. As such, one of ordinary skill in the art would adjust these values to optimize the photodetector according to desired properties so as to fabricate a customizable device. Since neither of these values appear to the result of non-routine experimentation or having yielded unexpected results, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233.
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Allowable Subject Matter
Claims 2-13 and 15-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art taken either singularly or in combination fails to anticipate or fairly suggest the limitations of the claims listed above in such a manner that a rejection under 35 U.S.C. 102 or 103 would be proper.
The prior art fails to teach a combination of all of the features in the claims. As to claims 3 and 16, Lo does not teach said buried layer (114) has the same conductivity type as said substrate (113) conductivity type and has a doping concentration substantially equal to said substrate doping concentration. Substrate layer 113 is p-type whereas the buried region is n-type.
As to claims 2 and 15, Lo teaches a second high-voltage well region (109) having a first conductivity type (p), extending into said semiconductor substrate to said third depth (d3) from said top surface, wherein said second high-voltage well region (109) surrounds and overlaps with a portion of said medium-voltage well region (108, see fig. 2 above),
the second high-voltage well region (109) forms a second passive metallurgical p-n junction with said first high-voltage well region (114, see fig. 2 above); and
a third high-voltage well region (104) having a second conductivity type (n), extending into said semiconductor substrate to said second depth (d3) from said top surface, wherein said third high-voltage well region (104) surrounds said second high-voltage well region (109), forming a second isotype metallurgical junction with said buried layer (see fig. 2 above), and
the third high-voltage well region (104) forming a third passive metallurgical p-n junction with said second high-voltage well region (109), said third passive metallurgical p-n junction being substantially perpendicular to said top surface (see fig. 2 above).
Lo fails to teach the second high-voltage well region (109) forms a first passive metallurgical p-n junction with said buried layer (112). Layers 109 and 112 do not share an interface.
Lo also fails to teach the second passive metallurgical p-n junction being substantially perpendicular to said top surface (see fig., 2 above, it is parallel).
The remaining claims are allowable at least because they depend from allowable claims 2 or 15.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any response to this Office Action should be faxed to (571) 273-8300 or mailed to:
Commissioner for Patents
P.O. Box 1450
Alexandria, VA 22313-1450
Hand-Delivered responses should be brought to:
Customer Service Window
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREN M KUSUMAKAR whose telephone number is (571)270-3520. The examiner can normally be reached on Monday – Friday from 7:30a – 4:30p EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KAREN KUSUMAKAR/
Primary Examiner, Art Unit 2897
6/9/26
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