DETAILED ACTION
Notice of Pre-AIA or AIA Status
Applicant’s amendment, filed 03/06/2026, for application number 18/628,503 has been received and entered into record. Claims 22-28, 32-35, 39 are amended. Claims 29-31, 38, 41 and 42 are cancelled. Claims 43 and 44 are added. Thus, claims 22-28, 32-37, 39-40 and 43-44 are presented for examination.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 22-28, 33-35, 39, 40, 43 and 44 are rejected under 35 U.S.C. 103 as being unpatentable over Peterson (US20140351526A1) in view of Sabih et al. (US 9,557,795 B1).
Regarding claim 22, Peterson teaches an apparatus (Figures 1-2B), comprising:
a processing unit including a plurality of processor cores (Figure 1, processor unit 110 and RAM 120 and “Data processing elements include, for example, circuits such as an ASIC (Application Specific Integrated Circuit), portions or circuits of individual processor cores, entire processor cores,” par 0040 and paragraph 32), wherein the processing unit is configured to support operation of the processor cores as a plurality of data processing pipelines including respective subsets of the processor cores (“Data processing elements include, for example, circuits such as an ASIC (Application Specific Integrated Circuit), portions or circuits of individual processor cores, entire processor cores, individual processors, and/or programmable hardware devices such as a field programmable gate array (FPGA), as well as any combinations thereof.” Par 0040 and “Controller 132 may be configured to control the pipeline functionality described herein using ASICs (Application Specific Integrated Circuits), software or firmware executed on one or more processor cores, and/or programmable hardware devices such as a field programmable gate array (FPGA), as well as any combinations thereof.” Par 0032 and Figure 1, data pipelines 136);
wherein the processing unit is configured to receive data and control distribution of the data to the data processing pipelines (“packetizer 420 is configured to control MUX's 430A-N in order to direct data to pipelines 202A-N” par 0070 and paragraph 50 and Figure 4), wherein each of the data processing pipelines is configured to support a maximum data processing rate (“Including multiple pipelines in storage controller 400 may allow data processing elements in each pipeline 202 to operate at lower clock frequencies while still maintaining high data processing bandwidth.” Par 0080) [the maximum data processing rate corresponds to the data processing bandwidth that each pipeline maintains during operation].
However, Peterson does not explicitly teach wherein, to control powering of the data processing pipelines, the processing unit is configured to: determine, based on a value of a parameter indicative of an incoming data rate of the data to the processing unit and based on the maximum data processing rate supported by each of the data processing pipelines, a quantity of the data processing pipelines to be powered; and control, based on the quantity of the data processing pipelines to be powered, powering of the data processing pipelines to support processing of the data.
In the analogous art, Sabih teaches wherein, to control powering of the data processing pipelines, the processing unit is configured to:
determine, based on a value of a parameter indicative of an incoming data rate of the data to the processing unit and based on the maximum data processing rate supported by each of the data processing pipelines, a quantity of the data processing pipelines to be powered (“Because controller 203 is configured to track how many of data processors of data processors 206 are active or inactive, controller 203 effectively knows the amount of information handling capacity or performance level for data processors 206.” Col. 6, ll. 51-56 and “the number of processors allocated is increased when the input data rate increases, and the number of processors allocated is decreased when the output data rate decreases.” Col. 9, ll. 14-17 and “data analyzer 204 may … increase or decrease the number of active data processors of data processors 206, or a combination thereof.” Col. 8, ll. 61-67) [parameter indicative of incoming data rate corresponds to the average incoming data rate and maximum data processing rate corresponds to information handling capacity]; and
control, based on the quantity of the data processing pipelines to be powered, powering of the data processing pipelines to support processing of the data (“Responsive to data analyzer 204 detecting a flag … an action may be taken such as, for example, activating or disabling one or more of data processors of data processors 206” col. 6, ll. 32-35 and “controller 203 or data analyzer 204 may be configured to power down a portion, such as one or more, of data processors of data processors 206.” Col. 9, ll. 61-64 and “It should be understood that multiple processors may be used for such parallel processing and by clocking various blocks, a pipelined architecture may be implemented… In other words, one or more data processors may have their power consumption reduced responsive to a lowered demand for performance, again where such power reduction may be obtained by powering down one or more of data processors 206, ” Col. 10, ll. 31-34) [the processing unit controls the powering of the units based on the quantity necessary to support the workload].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Peterson and Sabih before him before the effective filing date of the claimed invention, to have modified Peterson to incorporate the teachings of Sabih regarding the control logic for parallel data processing to address the need for increased bandwidth and throughput and have the ability to dynamically maintain power consumption at an optimally reduced power consumption level. (Sabih, column 10)
Regarding claim 23, Peterson and Sabih teach the apparatus of claim 22. Sabih further teaches wherein, to determine the value of the parameter indicative of the incoming data rate of the data to the processing unit, the processing unit is configured to:
count, during a data rate sampling interval, an amount of the data received at the processing unit (“data analyzer 204 may be configured to process both incoming and outgoing data for determining an incoming average data rate and an outgoing average data rate.” Col. 8, ll. 49-52 and column 6 paragraph 5) [“average” requires the processing unit to count amount of data received over an interval of time]; and
compute, based on the data rate sampling interval and the amount of the data received at the processing unit, the value of the parameter indicative of the incoming data rate of the data to the processing unit (“In response to an indication from data analyzer 204 indicating a current incoming data rate or a moving average of incoming data, controller 203 … may invoke either a power saving mode or a performance enhancing mode,” col. 7, ll. 8-14) [the moving average corresponds to the parameter representing the data rate].
Regarding claim 24, Peterson and Sabih teach the apparatus of claim 22. Sabih further teaches wherein the quantity of the data processing pipelines to be powered includes a subset of data processing pipelines from the plurality of data processing pipelines (“a subset of the plurality of processors may be operated at a full rate responsive to the first mode; and at least one processor of the plurality of processors may be operated in an idle mode responsive to the second mode.” Col. 2, ll. 44-48 and column 10, paragraph 2).
Regarding claim 25, Peterson and Sabih teach the apparatus of claim 22. Sabih further teaches wherein the quantity of the data processing pipelines to be powered includes each of the data processing pipelines from the plurality of data processing pipelines (“In an embodiment where performance level is controlled by reducing frequency of operation, it may be that all data processors in data processors 206 are active however their frequency of operation is either increased or decreased in order to be within an acceptance range.” Col. 10, ll. 3-8) [this shows scenario where all processors are active while managing the workload by frequency scaling].
Regarding claim 26, Peterson and Sabih teach the apparatus of claim 22. Sabih further teaches wherein the processing unit is configured to modify the quantity of the data processing pipelines to be powered based on a change in the value of the parameter indicative of the incoming data rate of the data to the processing unit (“In this embodiment, the number of processors allocated is increased when the input data rate increases, and the number of processors allocated is decreased when the output data rate decreases.” Col. 9, ll. 14-17).
Regarding claim 27, Peterson and Sabih teach the apparatus of claim 22. Sabih further teaches wherein the processing unit is configured to determine the quantity of the data processing pipelines to be powered based on respective power control capabilities of the respective data processing pipelines (“Responsive to data analyzer 204 detecting a flag set by converter 202, an action may be taken such as, for example, activating or disabling one or more of data processors of data processors 206 or throttling up or down the operating frequency of one or more of such data processors, or a combination thereof.” Col. 6, ll. 32-37) [the processing unit determines quantity and power state of the pipelines by selecting between specific capabilities like clock gating, frequency scaling, or full deactivation for those units].
Regarding claim 28, Peterson and Sabih teach the apparatus of claim 22. Sabih further teaches wherein, to control powering of the data processing pipelines, the processing unit is configured to:
modify an amount of power supplied to one or more of the data processing pipelines (“controller 203 or data analyzer 204 may be configured to power down a portion, such as one or more, of data processors of data processors 206.” Col. 9, ll. 61-64).
Regarding claim 33, Peterson and Sabih teach the apparatus of claim 22. Sabih further teaches wherein, to control powering of the data processing pipelines to support processing of the data, the processing unit is configured to:
reduce or turn off power to one or more of the data processing pipelines based on a determination that the quantity of the data processing pipelines to be powered is less than a current quantity of the data processing pipelines powered for the processing unit (“In this embodiment, the number of processors allocated is increased when the input data rate increases, and the number of processors allocated is decreased when the output data rate decreases.” Col. 9, ll. 14-17 and “If the current performance level is greater than the maximum performance level of the acceptance range, then a power reduction or conserving mode for data processors 206 may be invoked.” Col. 7, ll. 48-51).
Regarding claim 34, Peterson and Sabih teach the apparatus of claim 22. Sabih further teaches wherein, to control powering of the data processing pipelines to support processing of the data, the processing unit is configured to:
increase or turn on power to one or more of the data processing pipelines based on a determination that the quantity of the data processing pipelines to be powered is greater than a current quantity of the data processing pipelines powered for the processing unit (“In this embodiment, the number of processors allocated is increased when the input data rate increases,” Col. 9, ll. 14-17 and “if the performance level determined by controller 203 as a function of the average incoming data rate is less than the minimum performance, then a power enhancing mode may be invoked.” Col. 7, ll. 55-58).
Regarding claim 35, Peterson and Sabih teach the apparatus of claim 22. Sabih further teaches wherein the processing unit includes:
a monitor configured to determine the value of the parameter indicative of the incoming data rate of the data to the processing unit (“Data analyzer 204 is coupled to converter 202 to determine an input data rate in which data is being received from high-speed serial interfaces 201.” Col. 6, ll. 15-17) [the data analyzer corresponds to the monitor by determining the parameter for the incoming data rate]; and
a power controller configured to control powering of the data processing pipelines to support processing of the data (“controller 203 or data analyzer 204 may be configured to power down a portion, such as one or more, of data processors of data processors 206.” Col. 9, ll. 61-64) [the controller corresponds to the power controller that deactivates/ reducing power to specific pipelines based on the workload].
Regarding claim 39, Peterson and Sabih teach the apparatus of claim 35. Sabih further teaches wherein the power controller is configured to control powering of the data processing pipelines based on a power management bus connecting the power controller to each of the data processing pipelines (“data analyzer 204 may directly control performance level of data processors 206, as generally indicated by a dashed line to indicate a bus from data analyzer 204 to data processors 206.” Col. 8, ll. 55-59 and Figure 2) [dashed line from 204 to 206 corresponds to the bus connecting the controller to the pipelines].
Regarding claim 40, Peterson and Sabih teach the apparatus of claim 22. Sabih further teaches wherein the processing unit is a central processing unit (CPU), a graphics processing unit (GPU), or a network processing unit (NPU) (“Data processors 206 may be an array of DSPs 106 of FIG. 1. Alternatively, data processors 206 may be an array of embedded microprocessors, or microprocessors or microcontrollers instantiated in FPGA fabric, or a combination thereof.” Col. 5, ll. 34-38).
Regarding claim 43, Peterson teaches an apparatus, comprising:
a network processing unit including a plurality of data processing pipelines (Figure 1, processor unit 110 and RAM 120 and “Data processing elements include, for example, circuits such as an ASIC (Application Specific Integrated Circuit), portions or circuits of individual processor cores, entire processor cores,” par 0040 and paragraph 32 and Figure 8), wherein each of the data processing pipelines includes a respective plurality of processor cores arranged for serial processing of data packets provided to the respective data processing pipelines (“Data processing elements include, for example, circuits such as an ASIC (Application Specific Integrated Circuit), portions or circuits of individual processor cores, entire processor cores, individual processors, and/or programmable hardware devices such as a field programmable gate array (FPGA), as well as any combinations thereof.” Par 0040 and “Controller 132 may be configured to control the pipeline functionality described herein using ASICs (Application Specific Integrated Circuits), software or firmware executed on one or more processor cores, and/or programmable hardware devices such as a field programmable gate array (FPGA), as well as any combinations thereof.” Par 0032 and Figure 1, data pipelines 136), wherein the network processing unit is configured to receive data packets and control distribution of the data packets to the plurality of data processing pipelines (“packetizer 420 is configured to control MUX's 430A-N in order to direct data to pipelines 202A-N” par 0070 and paragraph 50 and Figure 4).
However, Peterson does not explicitly teach wherein the network processing unit is configured to: determine, based on an incoming packet rate of packets to the network processing unit and based on a maximum packet processing rate supported by each of the data processing pipelines, a quantity of the data processing pipelines to be powered; and control, based on the quantity of the data processing pipelines to be powered, powering of the data processing pipelines.
In the analogous art, Sabih teaches wherein the network processing unit is configured to:
determine, based on an incoming packet rate of packets to the network processing unit and based on a maximum packet processing rate supported by each of the data processing pipelines, a quantity of the data processing pipelines to be powered (“Because controller 203 is configured to track how many of data processors of data processors 206 are active or inactive, controller 203 effectively knows the amount of information handling capacity or performance level for data processors 206.” Col. 6, ll. 51-56 and “the number of processors allocated is increased when the input data rate increases, and the number of processors allocated is decreased when the output data rate decreases.” Col. 9, ll. 14-17 and “data analyzer 204 may … increase or decrease the number of active data processors of data processors 206, or a combination thereof.” Col. 8, ll. 61-67) [parameter indicative of incoming data rate corresponds to the average incoming data rate and maximum data processing rate corresponds to information handling capacity]; and
control, based on the quantity of the data processing pipelines to be powered, powering of the data processing pipelines (“Responsive to data analyzer 204 detecting a flag … an action may be taken such as, for example, activating or disabling one or more of data processors of data processors 206” col. 6, ll. 32-35 and “controller 203 or data analyzer 204 may be configured to power down a portion, such as one or more, of data processors of data processors 206.” Col. 9, ll. 61-64) [the processing unit controls the powering of the units based on the quantity necessary to support the workload].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Peterson and Sabih before him before the effective filing date of the claimed invention, to have modified Peterson to incorporate the teachings of Sabih regarding the control logic for parallel data processing to address the need for increased bandwidth and throughput and have the ability to dynamically maintain power consumption at an optimally reduced power consumption level. (Sabih, column 10)
Regarding claim 44, Peterson teaches network processor (Figures 1 and 8), comprising:
a plurality of data processing pipelines (Figure 1, data processing pipelines 136), wherein each of the data processing pipelines includes a respective plurality of processor cores arranged for serial processing of data packets provided to the respective data processing pipelines (“Write pipelines 202A-N may each include multiple data processing elements such as those described in conjunction with FIG. 2A.” par 0050 and “The concept of a “data processing pipeline” is well understood, and refers to the concept of splitting the “work” that a unit performs on data units into multiple stages… Data processing elements include, for example, circuits such as an ASIC (Application Specific Integrated Circuit) … entire processor cores,” par 0040);
a scatterer configured to receive data packets arriving at the network processor and control distribution of the data packets to the plurality of data processing pipelines (“packetizer 420 is configured to control MUX's 430A-N in order to direct data to pipelines 202A-N” par 0070 and paragraph 50 and Figure 4);
a gatherer configured to receive data packets output from the plurality of data processing pipelines and reorder the data packets output from the plurality of data processing pipelines for further propagation (“Adaptive fill unit 455, in one embodiment, is configured to sequence or order processed data units from pipelines 202A-N and write the data units to storage elements 485A-N.” par 0076) [the fill unit corresponds to the gatherer as it receives the output from the pipelines and reorders them into a correct sequence].
However, Peterson does not explicitly teach a monitor configured to determine a value of a parameter indicative of an incoming packet rate of the data packets arriving at the network processor; and a power controller configured to: determine, based on the value of the parameter indicative of incoming packet rate, a quantity of the plurality of data processing pipelines to be powered; and control, based on the quantity of the plurality of data processing pipelines to be powered and using a pipeline power management bus between the power controller and each of the plurality of data processing pipelines, powering of the data processing pipelines to support processing of the data packets arriving at the network processor.
In the analogous art, Sabih teaches a monitor configured to determine a value of a parameter indicative of an incoming packet rate of the data packets arriving at the network processor (“Data analyzer 204 is coupled to converter 202 to determine an input data rate in which data is being received from high-speed serial interfaces 201.” Col. 6, ll. 15-17) [the data analyzer corresponds to the monitor by determining the parameter for the incoming data rate]; and
a power controller (Figure 2, data analyzer 204 and controller 203) configured to:
determine, based on the value of the parameter indicative of incoming packet rate, a quantity of the plurality of data processing pipelines to be powered (“Because controller 203 is configured to track how many of data processors of data processors 206 are active or inactive, controller 203 effectively knows the amount of information handling capacity or performance level for data processors 206.” Col. 6, ll. 51-56 and “the number of processors allocated is increased when the input data rate increases, and the number of processors allocated is decreased when the output data rate decreases.” Col. 9, ll. 14-17 and “data analyzer 204 may … increase or decrease the number of active data processors of data processors 206, or a combination thereof.” Col. 8, ll. 61-67) [parameter indicative of incoming data rate corresponds to the average incoming data rate]; and
control, based on the quantity of the plurality of data processing pipelines to be powered and using a pipeline power management bus between the power controller and each of the plurality of data processing pipelines, powering of the data processing pipelines to support processing of the data packets arriving at the network processor (“Responsive to data analyzer 204 detecting a flag … an action may be taken such as, for example, activating or disabling one or more of data processors of data processors 206” col. 6, ll. 32-35 and “controller 203 or data analyzer 204 may be configured to power down a portion, such as one or more, of data processors of data processors 206.” Col. 9, ll. 61-64) [the processing unit controls the powering of the units based on the quantity necessary to support the workload] (“data analyzer 204 may directly control performance level of data processors 206, as generally indicated by a dashed line to indicate a bus from data analyzer 204 to data processors 206.” Col. 8, ll. 55-59 and Figure 2) [dashed line from 204 to 206 corresponds to the bus connecting the controller to the pipelines].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Peterson and Sabih before him before the effective filing date of the claimed invention, to have modified Peterson to incorporate the teachings of Sabih regarding the control logic for parallel data processing to address the need for increased bandwidth and throughput and have the ability to dynamically maintain power consumption at an optimally reduced power consumption level. (Sabih, column 10)
Claims 32 and 36 are rejected under 35 U.S.C. 103 as being unpatentable over Peterson and Sabih in view of Wang (US 2021/0224138 A1).
Regarding claim 32, Peterson and Sabih teach the apparatus of claim 22. However, Peterson and Sabih do not explicitly teach wherein, to determine the quantity of the data processing pipelines to be powered, the processing unit is configured to: determine, based on the value of the parameter indicative of the incoming data rate of the data to the processing unit, a minimum quantity of data processing pipelines to be powered; determine a buffer quantity of data processing pipelines to be powered; and determine the quantity of the data processing pipelines to be powered as a sum of the minimum quantity of data processing pipelines to be powered and the buffer quantity of data processing pipelines to be powered.
In the analogous art, Wang teaches wherein, to determine the quantity of the data processing pipelines to be powered, the processing unit is configured to:
determine, based on the value of the parameter indicative of the incoming data rate of the data to the processing unit, a minimum quantity of data processing pipelines to be powered (“For example, at 251-252 in FIG. 2, “first CPU cores” in the form of core-1 211 and core-2 212 may be identified to be over-utilized and require additional processing capability. In this case, to increase processing capability, block 362 may involve activating an increased-capability mode for core-i (i=1, 2) to increase one of the following: operating frequency, voltage, power and thermal budget.” Par 0029) [this identifies cores that require additional processing, indicating minimum quantity necessary for handling current load];
determine a buffer quantity of data processing pipelines to be powered (“The processing capability of a CPU core may also be unchanged (see 25N).” par 0030) [some cores maintain their current processing capability, meaning they remain powered and available as a buffer]; and
determine the quantity of the data processing pipelines to be powered as a sum of the minimum quantity of data processing pipelines to be powered and the buffer quantity of data processing pipelines to be powered (“At 450 and 460 in FIG. 4, host-A 110A may identify and adjust the processing capability of over-utilized CPU core(s) (denoted as core-i), as well as that of under-utilized CPU core(s) (denoted as core-j).” par 0045 and “ At 510-520 in FIG. 5, an increased-capability mode may be activated for over-utilized core-i (i=1, 2) based on the example in FIG. 2. The amount of increment may be the same for both CPU cores 211-212, or different (as shown in FIG. 2) based on their processing requirements. At 530, a power-saving mode may be activated for under-utilized core-j (j=3), such as to facilitate clock gating to save power. At 540, the processing capability of core-N (N=4) may be unchanged.” Par 0049) [the host adjusts the power (processing capability) for all relevant cores (under-utilized, over-utilized, and unchanged), corresponding to a total (sum) quantity of cores to be powered].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Peterson, Sabih and Wang before him before the effective filing date of the claimed invention, to have modified Peterson and Sabih to incorporate the teachings of Wang to determine the quantity of pipelines to be powered as a sum to accurately provide power to the required pipelines and ensure correct operation in the power saving mode. (Wang paragraphs 30, 31)
Regarding claim 36, Peterson and Sabih teach the apparatus of claim 35, However, Peterson and Sabih do not explicitly teach wherein the monitor is part of a scatterer configured to direct incoming data to a set of input data queues which store the incoming data while awaiting processing by the data processing pipelines.
In the analogous art, Wang teaches wherein the monitor is part of a scatterer configured to direct incoming data to a set of input data queues which store the incoming data while awaiting processing by the data processing pipelines (“Ingress packets (see 230) may be destined for various VMs supported by host-A 110A. Using RSS to achieve horizontal scaling, PNIC 124A may assign ingress packets 230 to different RX queues 221-22M to distribute packet processing among CPU cores 211-21N.” par 0025 and Figures 1 and 2) [the physical network interface controller corresponds to the scatterer; the RX queues may store incoming data; the host (monitor) contains the PNIC].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Peterson, Sabih and Wang before him before the effective filing date of the claimed invention, to have modified Peterson and Sabih to incorporate the teachings of Wang to have the monitor as part of a scatterer to have even distribution of packets to each queue. By spreading the workload over various cores, the queue length will be reduced and efficiency will be improved. (Wang, paragraph 25)
Claim 37 is rejected under 35 U.S.C. 103 as being unpatentable over Peterson and Sabih in view of Maiyuran et al. (US 2021/0150663 A1).
Regarding claim 37, Peterson and Sabih teach the apparatus of claim 35. However, Peterson and Sabih do not explicitly teach wherein the monitor is disposed between an entry point of the data to the processing unit and an element of the processing unit that is configured to direct incoming data to a set of input data queues which store the incoming data while awaiting processing by the data processing pipelines.
In the analogous art, Maiyuran teaches wherein the monitor is disposed between an entry point of the data to the processing unit and an element of the processing unit that is configured to direct incoming data to a set of input data queues which store the incoming data while awaiting processing by the data processing pipelines (“At block 2930, the processed portion of the unit of data is written by the media IP core to an intermediate streaming buffer (e.g., streaming buffer 2870 logically interposed between the media IP and the AI-specific core.” Par 0377 and “Signaling regarding the availability of data in the streaming buffer 2870 for processing by the consumer IP 2880 and signaling regarding consumption of the data by the consumer IP 2880 may involve the use of empty signal 2874 and full signal 2876 originated by the streaming buffer 2870” par 0373 and Figure 28D, 29, 30A, 30B) [the media IP may correspond to the entry point and the AI-specific core may correspond to the processing unit; the streaming buffer corresponds to the monitor interposed between these components which generated “full” and “empty” signals to monitor data flow/storage].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Peterson, Sabih and Maiyuran before him before the effective filing date of the claimed invention, to have modified Peterson and Sabih to incorporate the teachings of Maiyuran to add a monitor interposed between entry point of incoming data and a component to direct data flow because it would prevent data congestion and packet loss due to queue overfill.
Response to Arguments
Applicant’s arguments with respect to claim(s) 22 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
No additional arguments were presented as to the remaining claims. As such, the rejection is maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/AYMAN FATIMA/Examiner, Art Unit 2176
/JAWEED A ABBASZADEH/Supervisory Patent Examiner, Art Unit 2176