DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-7, 9-10, and 12-22 are pending in this application. Claims 1, 6, 16, 17, 20, and 22 have been amended. Claims 8 and 11 are canceled.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 04/05/24. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
Applicant’s amendments filed 0, have been fully considered. The amendment to claim 6 is sufficient to overcome the drawing objection, therefore the objection is withdrawn. In examining the claim set for allowability, examiner has realized new rejections/objections. See below.
Drawings
The drawings received on 03/16/26 are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the
“shared isolation barriers” of claim 1 and 20 – fig 2 completely omits isolation barriers (note, it is unclear what these elements are in any of the figures).
“common isolation boundary” of claim 4
must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
Reference numeral 2 of figure 2 is referred in par [0013] as “phase leg branch 2” and “switch module 2”. It is unclear what the limitation of block 2 in fig 2 is.
Appropriate correction is required.
Claim Objections
Claims 1, 16, and 20 are objected to because of the following informalities:
“DC” should be replaced with “direct current DC” as an abbreviation in any independent claim should be defined its first instance
Appropriate correction is required.
Claim Rejections - 35 USC § 112
Claims 1, 4, and 20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. See MPEP § 2172.01. The omitted elements are: what elements provide for the shared isolation barriers limitation in claim 1, what elements provide for the common isolation boundary limitation of claim 4, and the shared isolation barriers of claim 20.
The specification is silent on what element is responsible for and necessary to provide the shared isolation barriers and common isolation boundary.
An isolation barrier (or galvanic isolation barrier) is a structural and electrical separation within a circuit designed to prevent direct current DC and unwanted alternating current AC from flowing between two sections, while still allowing signals or power to be transferred. It separates high-voltage power stages (like the DC bus and inverter switches) from low-voltage control stages (like microcontrollers or digital signal processors) to protect sensitive equipment and human operators from electric shocks. The dashed box 2 switching module/phase leg branch has switches and the shunt resistor connected directly in series. This means they are on the same electrical potential and actively conduct the same phase leg current. Because a shunt resistor must be directly in the path of the current to measure the voltage drop across it, there is no electrical isolation between the resistor 4 and the adjacent switches 3a, 3b.
For the purpose of examination there is no galvanic isolation between the current sensors 4 and the adjacent power switches 3a, 3b inside the branch module 2 and therefore as best as can be understood from the disclosure, claim 1 is interpreted as in each phase leg, the current sensor and the pair of adjacent switches do not share or share isolation barriers. The shunt resistor 4 and the adjacent switches 3a, 3b are fully interconnected within the high-voltage AC phase leg branch. Within the diagram provided in figure 2 and the contents of the disclosure, no such boundary or barrier is shown or shared within module 2 therefore as best as can be understood from the disclosure, claim 4 is interpreted as in each phase leg, the current sensor and the pair of adjacent switches do not share or share a common isolation boundary. Claim 20 is interpreted as in each current sensor shares a power supply and shares or doesn’t share isolation barriers with switches.
Claims 2-7, 9-10, 12-19, and 21-22 are rejected for their dependency on claims 1 and 20.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9-10, 13-22 are rejected under 35 U.S.C. 103 as being unpatentable over He et al. (US 11119159 B2) and further in view of Abdoulin (US 20050012689 A1).
Regarding claim 1, He discloses a multilevel power converter (fig 2, Three-level T-Type NPC converter) comprising: a DC bus having a positive terminal (fig 2, Vdc + representing positive DC-bus voltage) and a negative terminal (fig 2, Vdc - representing negative DC-bus voltage); a plurality of switches for each of a plurality of phase legs of the power converter connected between the positive terminal and the negative terminal (fig 2, switches Sa1, Sb1, Sc1, Sa2, Sb2, Sc2, or each phase leg A, B, and C, all connected between Vdc+ and Vdc-), each phase leg having an output configured to provide a converted voltage output according to switching control of the plurality of switches (fig 2, V.sub.an, V.sub.bn, V.sub.cn voltage outputs for phases A,B, and C; col 6 lines 13-24 describe the operation of the power converter utilizing a controller to control the switches and operation of the converter); and a current sensor in each phase leg (fig 2, col 5 lines 64-67 “Phase leg current transducers in each of the phase legs can be used to measure the respective load currents (i.sub.a, i.sub.b, i.sub.c) in each of the Phase legs”).
He does not disclose current sensors connected in series between an adjacent pair of the plurality of switches and wherein, in each phase leg, the current sensor and the pair of adjacent switches do not share or share isolation barriers.
Abdoulin discloses a current sensing bi-directional switching circuit. Abdoulin discloses current sensors connected in series between a pair of adjacent switches (Fig 4A, resistor RS between switches 22; fig 6, series resistor between two adjacent switches BDS1 and BDS2) and wherein, in each phase leg, the current sensor and the pair of adjacent switches do not share or share isolation barriers (implicit).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of He and incorporate the current sensor between switching devices as taught by Abdoulin. The advantage of this design is to be able to sense current of the switch to determine if its normal or abnormal.
Regarding claim 2, He and Abdoulin disclose the multilevel power converter of claim 1, wherein the current sensor in each phase leg is a shunt resistor (Abdoulin par [0032] “A series resistor RS of approximately 10 milli ohms is used to sense the current in the switch”; although “shunt” is not disclosed, a 10 milliohm (10 mΩ) resistor is a very common value for a shunt resistor).
Regarding claim 3, He and Abdoulin disclose the multilevel power converter of claim 1, wherein, in each phase leg, the current sensor and the pair of adjacent switches share a common power supply (He fig 2 e.g. switch pairs Sa3 and Sa4 modified with Abdoulin’s current sensors all share a common power supply Vdc).
Regarding claim 4, He and Abdoulin disclose the multilevel power converter of claim 1, wherein, in each phase leg, the current sensor and the pair of adjacent switches share a common isolation boundary (He fig 2 e.g. switch pairs Sa3 and Sa4 modified with Abdoulin’s current sensors connected in series between neutral point of the DC link between C1 and C2; each branch of switches and sensor would share a common isolation boundary).
Regarding claim 5, He and Abdoulin disclose the multilevel power converter of claim 1, wherein the multilevel power converter is a T-type power converter (He fig 2; col 5 lines 57-58 “T-type topology converter”) having, for each phase leg, first and second switches connected in series between the positive terminal and the negative terminal (He fig 2, e.g. switch pair Sa3 and Sa4), a third switch connected between the series connected first and second switches and the positive terminal (He fig 2, e.g. switch Sa1), and a fourth switch connected between the series connected first and second switches and the negative terminal (He fig 2, e.g. switch Sa2).
Regarding claim 6, He and Abdoulin disclose the multilevel power converter of claim 1 wherein the multilevel power converter is a three-phase three-level T-type power converter (He fig 2 shows t-type 3 level power converter; col 5 lines 57-58 “T-type topology converter”).
Regarding claim 7, He and Abdoulin disclose the multilevel power converter of claim 1, wherein the multilevel power converter is a three-level power converter (He fig 2; col 4 lines 11-12 “FIG. 2 is a schematic diagram of a circuit topology of a Three-level T-Type NPC converter.”).
Regarding claim 9, He and Abdoulin disclose the multilevel power converter of claim 1, further comprising first and second capacitors connected in series across the positive and negative terminals (He fig 2, C1 and C2 series connected between Vdc+ and Vdc-), wherein the switches of all phase legs are connected to a mid-point between the first and second capacitors (He fig 2, mid-point between C1 and C2 connected to phase legs is a neutral point clamped configuration).
Regarding claim 10, He and Abdoulin disclose the multilevel power converter of claim 1, wherein each current sensor is configured to measure partial current based on a voltage drop across the current sensor to control switching of the plurality of switches (He’s fig 2 and claim 4, Three-level T-Type NPC converter modified with Abdoulin’s current sensor RS of fig. 4A; a single shunt resistor between two transistors would be implicit to one of ordinary skills in the art to be configured to measure partial current based on a voltage drop across the resistor).
Regarding claim 13, He and Abdoulin disclose the multilevel power converter of claim 9, wherein each current sensor directly measures current flowing through the first and second capacitors (He’s fig. 2, Three-level T-Type NPC converter modified with Abdoulin’s current sensor RS of fig. 4A; this configuration would allow each shunt resistor to sense the current that flows through the first and second capacitors).
Regarding claim 14, He and Abdoulin disclose the multilevel power converter of claim 1, wherein, in each phase leg, the current sensor and the pair of adjacent switches are configured to operate in a common source configuration (He’s fig. 2, Three-level T-Type NPC converter modified with Abdoulin’s current sensor RS of fig. 4A, the bi-directional switch 20 employs two common source, N channel MOSFETs 22).
Regarding claim 15, He and Abdoulin disclose the multilevel power converter of claim 1, wherein, in each phase leg, the current sensor and the pair of adjacent switches are configured to operate in a common emitter configuration (He discloses the switches of fig 2 may be implemented with various transistor types see col 6 lines 6-65; if implemented with IGBT it would be the common emitter type as the emitters both are connected to the current sensor resistor).
Regarding claim 16, He and Abdoulin disclose a multilevel power converter comprising: a DC bus having a positive terminal and a negative terminal; a plurality of switches for each of a plurality of phase legs of the power converter connected between the positive terminal and the negative terminal, each phase leg having an output configured to provide a converted voltage output according to switching control of the plurality of switches; and a current sensor in each phase leg connected in series between a pair of adjacent switches; wherein each current sensor is configured to reconstruct an output phase current by acting as a current sampler (it is obvious and implicit that He’s multilevel power converter modified to include Abdoulin’s shunt resistor current sensor between 2 switches in series would serve as a current sampler for phase current reconstruction).
Regarding claim 17, He and Abdoulin disclose the multilevel power converter of The multilevel power converter of wherein, in each phase leg, the current sensor and the pair of adjacent switches do not share or share isolation barriers (implicit, they either do or they don’t without mention).
Regarding claim 18, He and Abdoulin disclose the multilevel power converter of claim 1, wherein, for a positive voltage phase, a first switch is always on, a second switch and a third switch are switched on and off in a complementary fashion and a fourth switch is off, and wherein, for a negative voltage phase, the second switch is always on, the first switch and the fourth switch are switched on and off in a complementary fashion and the third switch is off (He’s fig. 2, Three-level T-Type NPC converter modified with Abdoulin’s current sensor RS of fig. 4A; for positive voltage phase, Sa2 is switched ON, Sa4 is OFF, while Sa3 and Sa1 alternate ON/OFF with each other. For negative voltage phase, Sa3 is ON and Sa1 is OFF while Sa3 and Sa4 alternate ON/OFF with each other).
Regarding claim 19, He and Abdoulin disclose the multilevel power converter of claim 1, wherein the current sensors are configured to detect whether a switching waveform is different from an expected waveform during normally controlled switching (see He col 12 lines 26-24, the abnormal variation of i.sub.np is different from what is expected during normal operation).
Regarding claim 20, He discloses a multilevel power converter (fig 2, Three-level T-Type NPC converter) comprising: a DC bus having a positive terminal (fig 2, Vdc + representing positive DC-bus voltage) and a negative terminal (fig 2, Vdc - representing negative DC-bus voltage); a first capacitor (fig 2, C1) and a second capacitor (fig 2, C2) connected in series across the positive terminal and the negative terminal (fig 2, see series connection across + and – Vdc); three phase legs connected between the positive terminal and the negative terminal (fig 2, each phase leg A, B, and C, all connected between Vdc+ and Vdc-), each phase leg comprising: a plurality of switches (fig 2, switches Sa1, Sb1, Sc1, Sa2, Sb2, Sc2); wherein a first terminal of a first switch of each phase leg is connected between the first and second capacitor (fig 2, see switches Sa3, Sb3, and Sc3 all connected between capacitors C1 and C2), and wherein each phase leg has an output configured to provide a converted voltage output according to switching control of the switches (fig 2, V.sub.an, V.sub.bn, V.sub.cn voltage outputs for phases A,B, and C; col 6 lines 13-24 describe the operation of the power converter utilizing a controller to control the switches and operation of the converter) and switches operating in a common source/emitter configuration (He fig. 2, Sa3 and Sa4 common source configuration).
He does not disclose a current sensor connected in series between a pair of adjacent switches wherein each current sensor shares a power supply and shares of doesn’t share isolation barriers with switches operating in a common source/emitter configuration.
Abdoulin discloses a current sensing bi-directional switching circuit. Abdoulin discloses current sensors connected in series between a pair of adjacent switches wherein each current sensor shares a power supply and shares of doesn’t share isolation barriers with switches operating in a common source/emitter configuration (fig 4A, resistor RS between switches 22; fig 6, series resistor between two adjacent switches BDS1 and BDS2; He’s converter modified with Abdoulin’s resistor sensors it would share a power supply and is implicit that is would/wouldn’t share isolation barriers).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of He and incorporate the current sensor between switching devices as taught by Abdoulin. The advantage of this design is to be able to sense current of the switch to determine if its normal or abnormal.
Regarding claim 21, He and Abdoulin disclose the multilevel power converter of claim 20, wherein each current sensor is configured to measure partial current based on a voltage drop across the current sensor to control switching of the plurality of switches (He’s fig 2 and claim 4, Three-level T-Type NPC converter modified with Abdoulin’s current sensor RS of fig. 4A; a single shunt resistor between two transistors is well known to one of ordinary skills in the art to be configured to measure partial current based on a voltage drop across the resistor), and wherein each current sensor is a shunt resistor (Abdoulin par [0032] “A series resistor RS of approximately 10 milli ohms is used to sense the current in the switch”; although “shunt” is not disclosed, a 10 milliohm (10 mΩ) resistor is a very common value for a shunt resistor).
Regarding claim 22, He and Abdoulin disclose the multilevel power converter of claim 20 wherein each current sensor is configured to reconstruct an output phase current by acting as a current sampler (implicit of a shunt resistor current sensor).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over He et al. (US 11119159 B2) and of Abdoulin (US 20050012689 A1) and further in view of Takizawa (US 20150003127 A1)
Regarding claim 12, He and Abdoulin disclose the multilevel power converter of claim 1.
He and Abdoulin fail to disclose wherein operation of the multilevel power converter is configured to be stopped based on an output of one of the current sensors when the respective current sensor detects a fault. Specifically He discloses the desire to identify the fault and utilize the controller to act in remediation mode to allow the converter to maintain operation. Although stopping the system does not appear to be desire of He’s converter system it would be obvious to one in the art to include this capability.
Takizawa discloses multilevel power conversion circuit. Takizawa discloses wherein operation of the multilevel power converter is configured to be stopped based on an output of one of the current sensors when the respective current sensor detects a fault (par [0052] “The control circuit CNT receives the information of the failure and instructs to immediately stop the whole system based on the information.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of He and Abdoulin and incorporate the controller function to stop the converter when a fault is detected as taught by Takizawa. The advantage of this design is to protect the converter components from excessive current beyond their ratings when a fault is detected.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
He et al. US 10658920 B2 - Fault-tolerant Topology For Multilevel T-type Converters
Arnedo et al US 20150303826 A1 - Neutral Point Clamped Multilevel Converter
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/LAUREN ASHLEY SHAW/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
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