DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 2-7 and 12-17 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Species I and Species II, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 10/20/2025.
Applicant's election with traverse of Species III in the reply filed on 10/20/2025 is acknowledged. The traversal is on the ground(s) that there would be no serious search and/or examination burden. This is not found persuasive because, as mentioned in the Election/Restriction Action, each of these Species are directed toward separate logical operations with differing physical layouts; these are clear, separate and non-obvious Species/inventions.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 8, 11, 18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ikeda (US 2017/0110453).
In regards to claim 1, Ikeda discloses of a logic gate circuit (10a in Fig 1A, 14 in Fig 6A), comprising: a signal output end (see Z); at least one signal input end (see A or B); a first voltage end (L1); a second voltage end (see L2); a pull-up network (N1), comprising a first N-channel field-effect transistor (NFET, N1), wherein the first NFET (N1) comprises: a first gate, wherein a first electrode of the first NFET (N1) and the first gate are connected to the first voltage end (L1, see Fig 1A); and a second gate, wherein a second electrode of the first NFET (N1) and the second gate are connected to the signal output end (at Z, see Fig 1A); and a pull-down network (see N2, N3 in Fig 1, or N5, N6 in Fig 6A), comprising a second NFET (N2, N3, or N5, N6), wherein the pull-down network is connected to the signal output end (at Z), the at least one signal input end (connected to A or B), and the second voltage end (L2), and wherein the pull-down network is configured to: control the second NFET (N2, N3 or N5, N6) based on a voltage of the at least one signal input end (A or B); and pull down a voltage of the signal output end by using a voltage of the second voltage end (L2, see Figs1A, 6A and Paragraphs 0071, 0119).
In regards to claim 8, Ikeda discloses of the logic gate circuit according to claim 1, wherein the logic gate circuit is a NAND gate circuit (see Paragraphs 0071, 0119), the NAND gate circuit comprises two signal input ends (A and B, see Figs 1A, 6A), and the two signal input ends are respectively a first signal input end and a second signal input end; the pull-down network further comprises a third NFET (N3, N6), the second NFET (N2, N5) comprises a first gate, and the third NFET (N3, N6) comprises a first gate; a first electrode of the third NFET (N3, N6) is connected to the second voltage end (L2, see Figs 1A, 6A), a second electrode of the third NFET (N3, N6) is connected to a first electrode of the second NFET (N2, N5), and a second electrode of the second NFET (N2, N5) is connected to the signal output end (Z); and the first signal input end (A) is connected to the first gate of the second NFET (N2, N5), and the second signal input end (B) is connected to the first gate of the third NFET (N3, N6, see Figs 1A, 6A and Paragraphs 0071, 0119).
In regards to claim 11, Ikeda discloses of an electronic device, comprising a printed circuit board and a chip, wherein the chip is electrically connected to the printed circuit board (see Figs 15-17), and the chip comprises: a digital logic circuit, wherein the digital logic circuit comprises at least one logic gate circuit (10a or 14, see Figs 1A, 6A), wherein the logic gate circuit comprises: a signal output end (at Z); at least one signal input end (at A or B); a first voltage end (L1); a second voltage end (L2); a pull-up network (N1), comprising a first N-channel field-effect transistor (NFET, N1), wherein the first NFET (N1) comprises: a first gate, wherein a first electrode of the first NFET (N1) and the first gate are connected to the first voltage end (L1); and a second gate, wherein a second electrode of the first NFET (N1) and the second gate are connected to the signal output end (at Z, see Fig 1A); and a pull-down network, comprising a second NFET (N2 of N3 in Fig 1A, N5 or N6 in Fig 6A), wherein the pull-down network is connected to the signal output end (at Z), the at least one signal input end (A or B), and the second voltage end (L2), and wherein the pull-down network is configured to: control the second NFET (L2, L3 or N5, N6) based on a voltage of the at least one signal input end (A, B); and pull down a voltage of the signal output end by using a voltage of the second voltage end (L2, see Fig 1A, 6A, 15-17 and Paragraphs 0071, 0119).
In regards to claim 18, Ikeda discloses of the electronic device according to claim 11, wherein the logic gate circuit (10a, 14) is a NAND gate circuit (see Paragraphs 0071, 0119) the NAND gate circuit comprises two signal input ends (A and B), and the two signal input ends are respectively a first signal input end (at A) and a second signal input end (at B); the pull-down network further comprises a third NFET (N3), the second NFET (N2 or N5) comprises a first gate, and the third NFET (N3 or N6) comprises a first gate; a first electrode of the third NFET (N3, N6) is connected to the second voltage end (L2), a second electrode of the third NFET (N3, N6) is connected to a first electrode of the second NFET (N2, N5), and a second electrode of the second NFET (N2, N5) is connected to the signal output end (Z, see Fig 1A); and the first signal input end (A) is connected to the first gate of the second NFET (N2, N5), and the second signal input end (B) is connected to the first gate of the third NFET (N3, N6, see Figs 1A, 6A and Paragraphs 0071, 0119).
In regards to claim 20, Ikeda discloses of the electronic device according to claim 11, wherein the logic gate circuit (10a, 14) is integrated in a back-end-of-line (for example see Figs 1A, 6A, 15-17).
Allowable Subject Matter
Claims 9-10 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
In regards to claim 9, the prior art does not disclose of the logic gate circuit according to claim 8, wherein the second NFET further comprises a second gate; and the second gate of the second NFET is connected to the first signal input end; or the second gate of the second NFET is connected to the second electrode of the third NFET, nor would it have been obvious to one of ordinary skill in the art to do so.
In regards to claim 10, the prior art does not disclose of the logic gate circuit according to claim 8, wherein the third NFET further comprises a second gate; and the second gate of the third NFET is connected to the second signal input end or the second voltage end, nor would it have been obvious to one of ordinary skill in the art to do so.
In regards to claim 19, the prior art does not disclose of the electronic device according to claim 18, wherein the second NFET further comprises a second gate; and the second gate of the second NFET is connected to the first signal input end; or the second gate of the second NFET is connected to the second electrode of the third NFET, nor would it have been obvious to one of ordinary skill in the art to do so.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason M Crawford whose telephone number is (571)272-6004. The examiner can normally be reached Mon-Fri 6:00am-3:00pm.
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/JASON M CRAWFORD/Primary Examiner, Art Unit 2844
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