DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-15 are pending and prosecuted.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5, 7, 8, 10-12, 14, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu et al., US Patent Publication 2016/0037095, henceforth known as Wu.
Regarding Claim 1, Wu et al., US Patent Publication 2016/0037095, discloses a charge sensor circuitry (Abstract; an active pixel sensor device) comprising:
a detector element configured to generate a charge signal at an internal node of the charge sensor circuitry, wherein the charge signal is representative of a physical property detected by the detector element (Figure 2; [0021-0026]; a photo detector PD that is connected to an “internal node” of the pixel. The photo detector stores a charge and after exposure to light, the amount of chargers in the photo detector decreases at rate with positive correlation to light intensity);
wherein the charge sensor circuitry is configured to operate in a first mode and a second mode for read-out of the charge signal from the charge sensor circuitry (Figure 2 and 6; [0021-0030]; [0034-0042]; an operation mode switching unit 41 controls the mode for which the pixel operates in, the pixel circuit being connected to VDD via switch SW1, or being connected to the second signal reading unit 42 via switch SW2),
wherein the charge sensor circuitry comprises a first transistor configured to be used in the first mode and the second mode and at least one second transistor configured to be used in the second mode (Figure 2 and 6; [0021-0030]; [0034-0042]; Transistor M11 is used in both modes);
wherein the first transistor comprises a drain, a source, and a gate, wherein one of the drain or source is connected to the internal node and another of the drain or source is connected for read-out from the charge sensor circuitry and wherein the gate is configured to receive a first control signal (Figure 2; [0021-0026]; transistor M1 comprises a drain, source, and a gate, where one of the source/drain is connected to the “internal node” and the other is connected to the node M (is connected for read-out from the charge sensor circuitry), and wherein the gate is connected to reset terminal R1-Rm (wherein the gate is configured to receive a first control signal)) ;
wherein the at least one second transistor comprises a first gate connected to the internal node and a second gate configured to receive a second control signal (Figure 2; [0021-0026]; transistors M12 comprises a gate connected to the “internal node” and transistor M13 comprises a gate configured to selection terminal S1-Sm (a second gate configured to receive a second control signal));
wherein the charge sensor circuitry is configured to, in the first mode, activate output of a first output signal through the first transistor based on the first control signal acting to select the first transistor for output (Figure 2 and 6; [0021-0030]; [0034-0042]; in the second operation mode, the transistor M11 is turned on and an output is provided to node M based on the reset terminal R1-Rm turning the transistor M11 on);
wherein the charge sensor circuitry is configured to, in the second mode, reset the internal node through the first transistor based on the first control signal and output a second output signal through the at least one second transistor based on the second control signal acting to select the at least one second transistor for output (Figure 2 and 6; [0021-0030]; [0034-0042]; in the first operation mode, transistor M11, the reset transistor, is turned on which resets the internal node, and an output is provided through transistors M12 and M13 based on the selection terminal S1-Sm turning transistor M13 on).
Regarding Claim 2, Wu discloses wherein a source or a drain of the at least one second transistor is connected to a constant bias (Figure 2 and 6; [0021-0030]; [0034-0042]; transistor M12 is connected to operating power Va).
Regarding Claim 3, Wu discloses wherein the at least one second transistor comprises an amplifier transistor and a select transistor, wherein the amplifier transistor comprises the first gate connected to the internal node and the select transistor comprises the second gate configured to receive the second control signal (Figure 2 and 6; [0021-0030]; [0034-0042]; transistor M12 is an amplifier transistor and transistor M13 is a select transistor. M12 has a gate connected to the “internal node” and the M13 has a gate connected to selection terminal S1-Sm).
Regarding Claim 5, Wu discloses wherein the detector element is a photodetector, a pyroelectric sensor, an ion-sensitive field-effect transistor or a bio-sensitive field-effect transistor (Figure 2 and 6; [0021-0030]; [0034-0042]; photo detectors PD).
Regarding Claim 7, Wu discloses wherein the first transistor is connected to a first output node and the at least one second transistor is connected to a second output node different from the first output node such that the charge sensor circuitry is configured to provide output in the first output node in the first mode and output in the second output node in the second mode (Figure 2 and 6; [0021-0030]; [0034-0042]; transistor M11 is connected to node M (first output node), and transistor M13 is connected toa different output node, such that the transistors provide output to the different nodes in the different operation modes).
Regarding Claim 8, Wu discloses a detector array comprising an array of charge sensor circuitries according to claim 1 (Figure 2 and 6; [0021-0030]; [0034-0042]; an active pixel sensing array 10),
a plurality of data lines connected to the charge sensor circuitries (Figure 2 and 6; [0021-0030]; [0034-0042]; the examiner considers the lines that connect transistor M11 of each pixel to node M are data lines, as well as the lines that connect the transistor M13 of each pixel to the first signal reading unit are also data lines),
a first set of first read-out circuitries connected to the data lines for read-out of output of the charge sensor circuitries in the first mode and a second set of second read-out circuitries connected to the data lines for read-out of output of the charge sensor circuitries in the second mode (Figure 2 and 6; [0021-0030]; [0034-0042]; a first signal reading unit 30 connected to the “data lines” for reading out the pixels in a first operation mode (a second set of second read-out circuitries connected to the data lines for read-out of output of the charge sensor circuitries in the second mode), and a second signal reading unit 42 used for reading out the “data lines” in the second operation mode (a first set of first read-out circuitries connected to the data lines for read-out of output of the charge sensor circuitries in the first mode) ).
Regarding Claim 10, Wu discloses wherein, in the charge sensor circuitries of the array, the first transistor is connected to a first output node and the at least one second transistor is connected to a second output node different from the first output node such that the charge sensor circuitry is configured to provide output in the first output node in the first mode and output in the second output node in the second mode (Figure 2 and 6; [0021-0030]; [0034-0042]; transistor M11 is connected to node M (first output node), and transistor M13 is connected to a different output node, such that the transistors provide output to the different nodes in the different operation modes),
wherein the detector array comprises a first set of first data lines connected to first output nodes of the charge sensor circuitries and a second set of second data lines connected to the second output nodes of the charge sensor circuitries (Figure 2 and 6; [0021-0030]; [0034-0042]; the examiner considers the “first set of data lines” to be lines connected between the pixels and the first signal reading unit 30, and considers the “Second set of data lines” to be the lines connected between the pixels and the second signal reading unit 42)
Regarding Claim 11, Wu discloses wherein the detector array is configured to bin output from a plurality of charge sensor circuitries as input to a single first read-out circuitry for read-out of output of the charge sensor circuitries in the first mode (Figure 2 and 6; [0021-0030]; [0034-0042]; the second signal reading unit connects to the measuring terminal M which connects to the power terminals S of all the sensing pixels, and converts the current sum Iout(sum) to an output voltage or an output current).
Regarding Claim 12, Wu discloses wherein the detector array is configured to selectively activate a sub-set of the second read-out circuitries for read-out of output of the charge sensor circuitries of a region of interest in the second mode (Figure 2 and 6; [0021-0030]; [0034-0042]; in the first operation mode, transistor M11, the reset transistor, is turned on which resets the internal node, and an output is provided through transistors M12 and M13 based on the selection terminal S1-Sm turning transistor M13 on. Thus each row connected to each selection terminal is outputted at the same time (activate a sub-set of the second read-out circuitries for read-out of output of the charge sensor circuitries of a region of interest in the second mode)) .
Regarding Claim 14, Wu discloses wherein the first read-out circuitries each comprise a charge-sensitive amplifier (Figure 2 and 6; [0021-0030]; [0034-0042]; the second signal reading unit 42 comprises of an operational amplifier and a resistor (charge-sensitive amplifier)).
Regarding Claim 15. Wu discloses a method for charge-based sensing (Abstract; an active pixel sensor device that performs the following method), said method comprising:
generating a charge signal at an internal node of a charge sensor circuitry, wherein the charge signal is representative of a physical property detected by the detector element (Figure 2; [0021-0026]; a photo detector PD that is connected to an “internal node” of the pixel. The photo detector stores a charge and after exposure to light, the amount of chargers in the photo detector decreases at rate with positive correlation to light intensity);
operating the charge sensor circuitry in a first mode for read-out of the charge signal (Figure 2 and 6; [0021-0030]; [0034-0042]; Transistor M11 is used in both modes. Where the “first mode” is the second operating mode), wherein operating the charge sensor circuitry in the first mode comprises:
receiving a first control signal at a gate of a first transistor further comprising a drain and a source, wherein one of the drain or source is connected to the internal node and another of the drain or source is connected for read-out from the charge sensor circuitry, wherein the first control signal acts to select the first transistor for output (Figure 2; [0021-0026]; transistor M1 comprises a drain, source, and a gate, where one of the source/drain is connected to the “internal node” and the other is connected to the node M (is connected for read-out from the charge sensor circuitry), and wherein the gate is connected to reset terminal R1-Rm (wherein the first control signal acts to select the first transistor for output). in the second operation mode, the transistor M11 is turned on and an output is provided to node M based on the reset terminal R1-Rm turning the transistor M11 on);
operating the charge sensor circuitry in a second mode for read-out of the charge signal (Figure 2 and 6; [0021-0030]; [0034-0042]; Transistor M11 is used in both modes. Where the “second mode” is the first operating mode), wherein operating the charge sensor circuitry in the second mode comprises:
resetting the internal node through the first transistor based on the first control signal acting as a reset signal; and receiving a second control signal at a second gate of at least one second transistor, wherein the at least one second transistor further comprises a first gate connected to the internal node, wherein the second control signal acts to select the at least one second transistor for output (Figure 2 and 6; [0021-0030]; [0034-0042]; in the first operation mode, transistor M11, the reset transistor, is turned on which resets the internal node, and an output is provided through transistors M12 and M13 based on the selection terminal S1-Sm turning transistor M13 on. transistors M12 comprises a gate connected to the “internal node” and transistor M13 comprises a gate configured to selection terminal S1-Sm (a second gate configured to receive a second control signal)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Karim et al., US Patent Publication 2009/0147118, henceforth known as Karim, and in further view of Shi et al., CN 110460786.
The examiner notes that the following rejections are used to address different dependent claims with a different interpretation of the claim language, while also addressing claims that are common between the two interpretationsa.
Regarding Claim 1, Karim discloses a charge sensor circuitry (Abstract; a active pixel sensor) comprising:
a detector element configured to generate a charge signal at an internal node of the charge sensor circuitry, wherein the charge signal is representative of a physical property detected by the detector element (Figure 4A; [0052]; [0056]; [0065]; [0068-0059]; a detector that generates a first signal in response to photons incident thereupon. The detector is coupled to a node that is connected to an electrode of capacitor Cc, a gate of transistor T1, and an electrode of a transistor T2);
wherein the charge sensor circuitry is configured to operate in a first mode and a second mode for read-out of the charge signal form the charge sensor circuitry, wherein the charge sensor circuitry comprises a first transistor configured to be used in the first mode and the second mode and at least one second transistor configured to be used in the second mode (Figure 4A, 4B, 4D, 4E, and 4F; [0030]; [0031]; [0051-0052]; [0056]; [0065]; [0068-0069]; the examiner considers the “first mode” the passive mode readout of the circuit as shown in Figure 4F, and the “second mode” as the active mode readout of the circuit as shown in Figure 4E. As seen in Figures 4F and 4E, the transistor T2 is used in both the “first mode” and the “second mode”, and the transistor T1 is used in the “second mode” );
wherein the first transistor comprises a drain, a source, and a gate, wherein one of the drain or source is connected to the internal node and another of the drain or source is connected for read-out from the charge sensor circuitry and wherein the gate is configured to receive a first control signal (Figure 4A; [0051-0052]; [0056]; [0065]; [0068-0059]; transistor T2 comprises of a drain, source and a gate, where one of the drain or source is connected to the “node”, and the other is connected to the output (for read-out from the charge sensor circuity) and the gate receives a RESET signal);
wherein the at least one second transistor comprises a first gate connected to the internal node (Figure 4A; [0051-0052]; [0056]; [0065]; [0068-0059]; transistor T1 comprises of a drain, source and a gate, wherein the gate is connected to the “node”);
wherein the charge sensor circuitry is configured to, in the first mode, activate output of a first output signal through the first transistor based on the first control signal acting to select the first transistor for output (Figure 4A, 4B, 4C, 4E, and 4F; [0030]; [0031]; [0051-0052]; [0056]; [0065]; [0068-0069]; the examiner considers the “first mode” as the passive mode readout of the circuit as shown in Figure 4F. As seen in Figure 4F , a Reset signal is applied to transistor T2, acting to select the transistor to connect to Output),
wherein the charge sensor circuitry is configured to, in the second mode, reset the internal node through the first transistor based on the first control signal and output a second output signal through the at least one second transistor (Figure 4A, 4B, 4C, 4E, and 4F; [0030]; [0031]; [0051-0052]; [0056]; [0065]; [0068-0069]; examiner considers the “second mode” as the active mode readout of the circuit as shown in Figure 4e. As seen in Figure 4e, there is a global reset, which resets the “node” based on the RESET signal being supplied to the transistor T2 (reset the internal node through the first transistor based on the first control signal), and a Read signal being supplied that activates the transistor T1 that selects transistor to connect to the Output (output a second output signal through the at least one second transistor)).
However, Karim doesn’t explicitly disclose
wherein the at least one second transistor comprises a first gate connected to the internal node and a second gate configured to receive a second control signal,
wherein the charge sensor circuitry is configured to, in the second mode, reset the internal node through the first transistor based on the first control signal and output a second output signal through the at least one second transistor based on the second control signal acting to select the at least one second transistor for output.
Shi et al., CN 110460786, discloses a pixel sensing circuit that utilizes a source follower transistor MSF which is a double-gate transistor. The source follower transistor has a first gate connected to the photodiode, a first electrode connected to VDD, a second electrode connected to the Pixel Out, and a second gate connected to Vbias1 (Figure 3; Pages 4 and 5; ).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the disclosure of Karim to further include the teachings of Shi such that the transistor T1 is replaced with a source follower transistor which is a double-gate transistor. The motivation to combine these arts is because Shi teaches improving the uniformity of different threshold voltages and improve the accuracy of the photoelectric detection (Shi: Pages 4 and 5).
Therefore, the combination of Karim and Shin teaches wherein the at least one second transistor comprises a first gate connected to the internal node and a second gate configured to receive a second control signal (Karim: Figure 4A and 4B; [0051-0052]; [0056]; [0065]; [0068-0059]; Shi: Figure 3; Pages 4 and 5; the source follower transistor has a first gate that is connected to the “node” and a second a gate connected to receive Vbias1),
wherein the charge sensor circuitry is configured to, in the second mode, output a second output signal through the at least one second transistor based on the second control signal acting to select the at least one second transistor for output (Karim: Figure 4A, 4B, 4C, 4E, and 4F; [0030]; [0031]; [0051-0052]; [0056]; [0065]; [0068-0069]; Shi: Figure 3; Pages 4 and 5; examiner considers the “second mode” as the active mode readout of the circuit as shown in Figure 4e. As seen in Figure 4e, there is a global reset, which resets the “node” based on the RESET signal being supplied to the transistor T2 (reset the internal node through the first transistor based on the first control signal), and a Read signal being supplied and Vbias1 (second control signal) that is supplied to the second gate of transistor T1 that activates the transistor T1 and selects it to connect to the Output (output a second output signal through the at least one second transistor based on the second control signal acting to select the at least one second transistor for output)).
Regarding Claim 2, The combination of Karim and Shin teaches wherein a source or a drain of the at least one second transistor is connected to a constant bias (Karim: Figure 4A and 4B; [0051-0052]; [0056]; [0065]; [0068-0059]; transistor T1 has an electrode connected to Vbias (constant bias)).
Regarding Claim 3, The combination of Karim and Shin teaches wherein the at least one second transistor comprises an amplifier transistor and a select transistor (Shi: Figure 3; Pages 4 and 5; the examiner considers the MSF transistor T1 to comprise of both an “amplifier transistor” and a “select transistor”),
wherein the amplifier transistor comprises the first gate connected to the internal node and the select transistor comprises the second gate configured to receive the second control signal (Karim: Figure 4A and 4B; [0051-0052]; [0056]; [0065]; [0068-0059]; Shi: Figure 3; Pages 4 and 5; the MSF transistor T1 has a first gate connected to the “node” and a second gate connected to receive Vbias1 (the second control signal)).
Regarding Claim 4, The combination of Karim and Shi teaches wherein the at least one second transistor comprises a single transistor (Shi: Figure 3; Pages 4 and 5; the MSF transistor T1 is a single transistor),
wherein the single transistor has a front gate forming the first gate connected to the internal node and a back gate forming the second gate configured to receive the second control signal (Karim: Figure 4A and 4B; [0051-0052]; [0056]; [0065]; [0068-0059]; Shi: Figure 3; Pages 4 and 5; the MSF transistor T1 has a first gate connected to the “node” and a second gate connected to receive Vbias1 (the second control signal)).
Regarding Claim 5, The combination of Karim and Shi teaches wherein the detector element is a photodetector, a pyroelectric sensor, an ion-sensitive field-effect transistor or a bio-sensitive field-effect transistor (Karim: Figure 4A and 4B; [0051-0052]; [0056]; [0065]; [0068-0059]; the detector may be any type of detector, for example, solid-state photodetectors such as a-Si:H, amorphous selenium or cadmium zinc telluride based detectors and photoconductors, or any other appropriate detector).
Regarding Claim 6, The combination of Karim and Shi teaches wherein the first transistor and the at least one second transistor are connected to a common output node such that the charge sensor circuitry is configured to provide output in the first mode and the second mode in the common output node (Karim: Figure 4A, 4B, 4C, 4E, and 4F; [0030]; [0031]; [0051-0052]; [0056]; [0065]; [0068-0069]; Shi: Figure 3; Pages 4 and 5; the transistors are connected to a “common output node” that allows the circuit to provide output in both modes).
Claims 8, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Karim et al., US Patent Publication 2009/0147118, henceforth known as Karim, and in further view of Shi et al., CN 110460786, and in further view of Wu.
Regarding Claim 8, The combination of Karim and Shi teaches a detector array comprising an array of charge sensor circuitries according to claim 1 (Karim: Figure 4A, 4B, 4C, 4E, and 4F; [0030]; [0031]; [0051-0052]; [0056]; [0065]; [0068-0069]; Shi: Figure 3; Pages 4 and 5; an imaging array as seen in Figure 4C),
a plurality of data lines connected to the charge sensor circuitries (Karim: Figure 4A, 4B, 4C, 4E, and 4F; [0030]; [0031]; [0051-0052]; [0056]; [0065]; [0068-0069]; Shi: Figure 3; Pages 4 and 5; a plurality of output lines).
However, Karim and Shi doesn’t explicitly teach a first set of first read-out circuitries connected to the data lines for read-out of output of the charge sensor circuitries in the first mode and a second set of second read-out circuitries connected to the data lines for read-out of output of the charge sensor circuitries in the second mode.
Wu discloses a first set of first read-out circuitries connected to the data lines for read-out of output of the charge sensor circuitries in the first mode and a second set of second read-out circuitries connected to the data lines for read-out of output of the charge sensor circuitries in the second mode (Figure 2 and 6; [0021-0030]; [0034-0042]; a first signal reading unit 30 connected to the “data lines” for reading out the pixels in a first operation mode (a second set of second read-out circuitries connected to the data lines for read-out of output of the charge sensor circuitries in the second mode), and a second signal reading unit 42 used for reading out the “data lines” in the second operation mode (a first set of first read-out circuitries connected to the data lines for read-out of output of the charge sensor circuitries in the first mode)).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the disclosure of Karim and Shi to further include the teachings of Wu such that the multimode output column circuit, as shown in Figure 4D of Karim, is replaced with the first and second signal reading units as described in Wu in order to provide a first set of first read-out circuitries connected to the data lines for read-out of output of the charge sensor circuitries in the first mode and a second set of second read-out circuitries connected to the data lines for read-out of output of the charge sensor circuitries in the second mode. The motivation to combine these analogous arts is because Wu teaches an alternative means of sensing the output of an array of sensors that are integrated passive and active pixel sensors capable of operating in two operation modes (Wu: [0004-0005]; [0020];)
Regarding Claim 9, The combination of Karim, Shi, and Wu teaches wherein, in the charge sensor circuitries of the array, the first transistor and the at least one second transistor are connected to a common output node such that the charge sensor circuitry is configured to provide output in the first mode and the second mode in the common output node (Karim: Figure 4A, 4B, 4C, 4E, and 4F; [0030]; [0031]; [0051-0052]; [0056]; [0065]; [0068-0069]; Shi: Figure 3; Pages 4 and 5; the transistors are connected to a “common output node” that allows the circuit to provide output in both modes),
wherein the detector array comprises first switches and second switches for selecting whether output of charge sensor circuitries on the data lines is transferred to first or second read-out circuitries (Wu: Figure 2 and 6; [0021-0030]; [0034-0042]; an operation mode switching unit 41 controls the mode for which the pixel operates in, the pixel circuit being connected to VDD via switch SW1, or being connected to the second signal reading unit 42 via switch SW2).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Wu in further view of Shi et al., US Patent Publication 2013/0287274, henceforth known as Shi.
Regarding Claim 13, Wu doesn’t explicitly disclose wherein the detector array is configured to be controlled for double delta sampling or correlated double sampling in read-out of output of the charge sensor circuitries.
However, Shi et al., US Patent Publication 2013/0287274, discloses a charge amplifier can use additional circuitry for offset compensation. For example, a charge amplifier can use correlated double sampling technology for offset compensation. ([0102];).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the disclosure of Wu to further include the teachings of Shi in order to provide wherein the detector array is configured to be controlled for double delta sampling or correlated double sampling in read-out of output of the charge sensor circuitries. The motivation to combine these arts is because Shi teaches the use of correlated double sampling technology for offset compensation (Shi: [0102];).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wakabayashi, US Patent 9319610, discloses an image pickup device with a similar sensor circuit and two switches, ADSW1 and ADSW2, to switch the paths of the read-out signal to the ADC 113.
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/PATRICK F MARINELLI/Primary Examiner, Art Unit 2699