DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
For Examiner’s Interview fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html).
Status of claim(s) to be treated in this office action:
Independent: 1, 12 and 17.
Pending: 1-20.
Withdrawn: 4-5 and 18-20.
Information Disclosure Statement
Applicant’s IDS(s) submitted on 4/8/2024 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have considered by the examiner and made of record.
Specification
The disclosure is objected to because of the following informalities:
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE HAVING MULTIPLE MAGNETIC MEMORY REGIONS WITH DIFFERENT STORAGE CAPACITIES AND OPERATING SPEEDS.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Kashiwagi et al., US PG pub. 20150074489 A1.
Re: Independent Claim 1, Kashiwagi discloses a logic region (AREG, fig. 11) comprising a circuit;
a first memory region (MCA1, fig. 11; ¶0066) controlled by the logic region (AREG, fig. 11) and having a first storage capacity (user data and work data, fig. 11), the first memory region (MCA1, fig. 11; ¶0066) comprising a plurality of first memory cells (as shown in figure 9 the MRAM chip include multiple memory cells MC); and
a second memory region (MCA2, fig. 11) controlled by the logic region (AREG, fig. 11) and having a second storage capacity (boot program, table, kernel, fig. 11) greater than the first storage capacity (user data and work data, fig. 11), the second memory region (MCA2, fig. 11) comprising a plurality of second memory cells (as shown in figure 9 the MRAM chip include multiple memory cells MC),
wherein each of the plurality of first memory cells (as shown in figure 9 the MRAM chip include multiple memory cells MC) and each of the plurality of second memory cells (as shown in figure 9 the MRAM chip include multiple memory cells MC) comprises a magnetic memory element, and
wherein an operating speed of the first memory region (MCA1, fig. 11; ¶0066; “reading data from the work memory (the first memory region MCA1) for which a higher priority is given to the performance”) is faster than an operating speed of the second memory region (MCA2, fig. 11).
Re: Claim 2, Kashiwagi disclose(s) all the limitations of claim 1 on which this claim depends. Kashiwagi further discloses: wherein the logic region (AREG, fig. 11), the first memory region (MCA1, fig. 11; ¶0066), and the second memory region (MCA2, fig. 11) are included in a single chip (1, fig. 11).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kashiwagi et al., US PG pub. 20150074489 A1; in view of Laurent US patent 10157643 B2.
Re: Claim 3, Kashiwagi discloses all the limitations of claim 1 on which this claim depends. Kashiwagi is silent regarding: a package substrate, at least one chip including the logic region (AREG, fig. 11), the first memory region (MCA1, fig. 11; ¶0066), and the second memory region (MCA2, fig. 11) being on the package substrate.
Laurent teaches in figure 3 and figure 7 a memory cell (105-b) can have a package substrate (315 and 505), wherein a logic region, first and second memory (430, 415) can be on a substrate (315 and 505).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a package substrate where memory device can formed on since a package substrate is a mechanical and electrical framework that enables the chip to function reliably and efficiently.
Claim(s) 6 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kashiwagi et al., US PG pub. 20150074489 A1; in view of Lee et al., US PG pub. 20230022115 A1.
Re: Claim 6, Kashiwagi discloses all the limitations of claim 1 on which this claim depends. Kashiwagi is silent regarding: wherein the logic region (AREG, fig. 11) comprises: a front end of line (FEOL) region comprising semiconductor elements on a semiconductor substrate; and
a back end of line (BEOL) region comprising wiring patterns connecting at least some of the semiconductor elements to each other,
wherein the logic region (AREG, fig. 11) comprises a first region and a second region in different locations in a direction parallel to an upper surface of the semiconductor substrate, wherein a density of the wiring patterns in the BEOL region of the first region is higher than a density of the wiring patterns in the BEOL region of the second region, and wherein the first region is closer to the second memory region (MCA2, fig. 11) than the first memory region (MCA1, fig. 11; ¶0066).
Lee teaches wherein the logic region (1200, fig. 12) comprises: a front end of line (FEOL) region (1220, fig. 12) comprising semiconductor elements on a semiconductor substrate (1210, fig. 12); and a back end of line (BEOL) region (1242, fig. 12) comprising wiring patterns (Mn, fig. 12) connecting at least some of the semiconductor elements to each other, wherein the logic region (1200, fig. 12) comprises a first region (region from 1240 to 1250, fig. 12) and a second region (region 1230, fig. 12) in different locations in a direction parallel to an upper surface of the semiconductor substrate (1210, fig. 12), wherein a density of the wiring patterns (Mn, fig. 12) in the BEOL region of the first region (region from 1240 to 1250, fig. 12) is higher than a density of the wiring patterns (Mn, fig. 12) in the BEOL region of the second region (region 1230, fig. 12), and wherein the first region (region from 1240 to 1250, fig. 12) is closer to the second memory region (BEOL memory, fig. 12) than the first memory region (FEOL include memory device;¶0024).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use BEOL and FEOL stacks as the memory device since memory devices use FEOL and BEOL stacks because FEOL builds the storage elements and BEOL provides the high-density, multi-layer interconnects needed to link them efficiently. Stacking these layers vertically is essential for high density, performance, and 3D integration, while keeping FEOL and BEOL processes separate allows optimal control over device and interconnect characteristics.
Claim(s) 7 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kashiwagi et al., US PG pub. 20150074489 A1; in view of Lee et al., US PG pub. 20230022115 A1; further in view of Fryman et al., US patent 12438618 B2.
Re: Claim 7, Kashiwagi and Lee discloses all the limitations of claim 6 on which this claim depends. Kashiwagi and Lee is silent regarding: wherein at least one of a central processing unit (CPU), a graphics processing unit (GPU), and a neural processor is in the first region, and at least one of an input/output circuit and a power circuit is in the second region.
Fryman teaches wherein at least one of a central processing unit (CPU), a graphics processing unit (GPU), and a neural processor is in the first region (1420, fig. 14), and at least one of an input/output circuit and a power circuit is in the second region (1414, fig. 14).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a CPU GPU and neural processor since memory devices need CPUs, GPUs, and NPUs together because each have strengths in different types of computation, CPUs can control and coordination, GPUs can parallel data crunching, and NPUs have AI-specific math and combining them ensures optimal speed, efficiency, and versatility in computing.
Claim(s) 10-11 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kashiwagi et al., US PG pub. 20150074489 A1; in view of Wu et al., US PG pub. 20230064289 A1(cited in IDS dated 4/8/2024).
Re: Claim 10, Kashiwagi discloses all the limitations of claim 1 on which this claim depends. Kashiwagi is silent regarding: wherein each of the plurality of first memory cells (as shown in figure 9 the MRAM chip include multiple memory cells MC) is a spin orbit torque (SOT)-MRAM cell, and each of the plurality of second memory cells (as shown in figure 9 the MRAM chip include multiple memory cells MC) is an STT-MRAM cell.
Wu teaches using Spin-Transfer Torque (STT) and Spin-Orbit Torque (SOT) MRAM together in a hybrid design (as shown in figure 1).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include STT-MRAM and SOT-MRAM hybrid design since STT-MRAM suffers from wear on the tunnel barrier because read and write currents share the same path. Adding SOT paths helps decouple write mechanisms, preserving long-term device reliability.
Re: Claim 11, Kashiwagi discloses all the limitations of claim 1 on which this claim depends. Kashiwagi is silent regarding: wherein each of the plurality of first memory cells (as shown in figure 9 the MRAM chip include multiple memory cells MC) is an STT-MRAM cell or an SOT-MRAM cell, and each of the plurality of second memory cells (as shown in figure 9 the MRAM chip include multiple memory cells MC) is a racetrack memory cell.
Wu teaches using Spin-Transfer Torque (STT) and Spin-Orbit Torque (SOT) MRAM together in a hybrid design (as shown in figure 1).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include STT-MRAM and SOT-MRAM hybrid design since STT-MRAM suffers from wear on the tunnel barrier because read and write currents share the same path. Adding SOT paths helps decouple write mechanisms, preserving long-term device reliability.
Claim(s) 12-16 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kashiwagi et al., US PG pub. 20150074489 A1; in view of Lee et al., US PG pub. 20230022115 A1.
Re: Independent Claim 12, Kashiwagi discloses a first memory region (MCA1, fig. 11; ¶0066) comprising a plurality of first memory cells (as shown in figure 9 the MRAM chip include multiple memory cells MC); and
a second memory region (MCA2, fig. 11) comprising a plurality of second memory cells (as shown in figure 9 the MRAM chip include multiple memory cells MC) different from the plurality of first memory cells (as shown in figure 9 the MRAM chip include multiple memory cells MC),
Kashiwagi is silent regarding: a logic region (AREG, fig. 11) comprising a semiconductor substrate, a front end of line (FEOL) region comprising semiconductor elements on the semiconductor substrate, and a back end of line (BEOL) region comprising wiring patterns connecting at least some of the semiconductor elements to each other; wherein the logic region (AREG, fig. 11) comprising a first region and a second region in different locations in a direction parallel to an upper surface of the semiconductor substrate, wherein a density of the wiring patterns in the BEOL region in the first region is higher than a density of the wiring patterns in the BEOL region in the second region, and wherein the first region is closer to the first memory region (MCA1, fig. 11; ¶0066) than the second memory region (MCA2, fig. 11).
Lee teaches wherein the logic region (1200, fig. 12) comprises a first region (region from 1240 to 1250, fig. 12) and a second region (region 1230, fig. 12) in different locations in a direction parallel to an upper surface of the semiconductor substrate (1210, fig. 12), wherein a density of the wiring patterns (Mn, fig. 12) in the BEOL region of the first region (region from 1240 to 1250, fig. 12) is higher than a density of the wiring patterns (Mn, fig. 12) in the BEOL region of the second region (region 1230, fig. 12), and wherein the first region (region from 1240 to 1250, fig. 12) is closer to the second memory region (BEOL memory, fig. 12) than the first memory region (FEOL include memory device;¶0024).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use BEOL and FEOL stacks as the memory device since memory devices use FEOL and BEOL stacks because FEOL builds the storage elements and BEOL provides the high-density, multi-layer interconnects needed to link them efficiently. Stacking these layers vertically is essential for high density, performance, and 3D integration, while keeping FEOL and BEOL processes separate allows optimal control over device and interconnect characteristics.
Re: Claim 13, Kashiwagi and Lee discloses all the limitations of claim 12 on which this claim depends. Kashiwagi further discloses: wherein a structure of the plurality of first memory cells (as shown in figure 9 the MRAM chip include multiple memory cells MC) is the same as a structure of the plurality of second memory cells (as shown in figure 9 the MRAM chip include multiple memory cells MC), and a size of each of the plurality of first memory cells (as shown in figure 9 the MRAM chip include multiple memory cells MC) is smaller than a size of each of the plurality of second memory cells (as shown in figure 9 the MRAM chip include multiple memory cells MC).
Re: Claim 14, Kashiwagi and Lee discloses all the limitations of claim 12 on which this claim depends. Kashiwagi further discloses: wherein a structure of the plurality of first memory cells (as shown in figure 9 the MRAM chip include multiple memory cells MC) have a structure is different from a structure of the plurality of second memory cells (as shown in figure 9 the MRAM chip include multiple memory cells MC).
Re: Claim 15, Kashiwagi and Lee discloses all the limitations of claim 14 on which this claim depends. Kashiwagi further discloses: wherein each of the plurality of first memory cells (as shown in figure 9 the MRAM chip include multiple memory cells MC) comprises a switch element and a first magnetic memory element, and wherein each of the plurality of second memory cells (as shown in figure 9 the MRAM chip include multiple memory cells MC) comprises a second magnetic memory element.
Re: Claim 16, Kashiwagi and Lee discloses all the limitations of claim 12 on which this claim depends. Kashiwagi further discloses: wherein an integration density of the first memory region (MCA1, fig. 11; ¶0066) is lower than an integration density of the second memory region (MCA2, fig. 11).
Claim(s) 17 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kashiwagi et al., US PG pub. 20150074489 A1.
Re: Independent Claim 17, Kashiwagi discloses a logic region (AREG, fig. 11) comprising a plurality of cache memories (RAM in SoC, fig. 11; a cache process role that temporary copy of code closer to processor) a first memory region (MCA1, fig. 11; ¶0066) being a dynamic memory; and a second memory region (MCA2, fig. 11) being a storage and having a storage capacity (boot program, table, kernel, fig. 11) greater than a storage capacity (user data and work data, fig. 11) of the first memory region (MCA1, fig. 11; ¶0066), and wherein the first memory region (MCA1, fig. 11; ¶0066) and the second memory region (MCA2, fig. 11) are a magnetic memory device.
Kashiwagi is silent regarding process of the memory device that the logic region comprising a core that comprises a plurality of intellectual property (IP) blocks, and a plurality of cache memories; wherein the plurality of cache memories comprise an L1 cache, an L2 cache, and an L3 cache, and the L3 cache.
However, according to the MPEP, Section 2113, "Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process”.
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
* (“Kang US patent 9977610 B2”) Discloses a data storage device includes a first multi-chip set which includes a first volatile memory, a first non-volatile memory, and a first core configured to control the first volatile memory and the first non-volatile memory, a second multi-chip set which includes a second volatile memory, a second non-volatile memory, and a second core configured to control the second volatile memory and the second non-volatile memory. A controller is connected to the first multi-chip set and the second multi-chip set and configured to swap a first logical address of a first storage region of the first non-volatile memory with a second logical address of a second storage region of the second non-volatile memory.
* (“Yi et al., US PG pub. 20160291869 A1”) discloses a data storage device includes a first scale-out controller configured to control a first non-volatile memory and a first volatile memory, a second scale-out controller configured to control a second non-volatile memory and a second volatile memory, and a controller configured to set a first memory management policy for the first non-volatile memory to be different from a second memory management policy for the second non-volatile memory.
* (“Kim et al., US PG pub. 20130311717 A1”) discloses a magnetic random access memory (MRAM), and a memory module, memory system including the same, and method for controlling the same are disclosed. The MRAM includes magnetic memory cells configured to change between at least two states according to a magnetization direction, and a mode register supporting a plurality of operational modes.
* (“Lee et al., US Patent 11360695 B2”) discloses an apparatus may include a first memory circuit having a first characteristic and a second memory circuit having a second characteristic. Contact pads of the first and second memory circuits may be connected in parallel and to a common interface configured to communicate data between the apparatus and an external device.
* (“Retter et al., US patent 10713169 B2”) discloses a first coherency domain of a memory access request originating from a master in a second coherency domain and excluding from its scope a third coherency domain, coherence participants in the first coherency domain provide partial responses, and one of the coherence participants speculatively provides, to the master, data from a target memory block. The data includes a memory domain indicator indicating whether the memory block is cached, if at all, only within the first coherency domain. Based on the partial responses a combined response is generated representing a systemwide coherence response to the memory access request. In response to the combined response indicating success and the memory domain indicator indicating that a valid copy of the memory block may be cached outside the first coherence domain, the master discards the speculatively provided data and reissues the memory access request with a larger broadcast scope.
* (“Hassan US PG pub. 20160328169 A1”) discloses computer-readable storage mediums for receiving source code of an application, providing intermediate code based on the source code, the intermediate code including at least one instruction for profiling at least one object of the application, providing a statistics file by processing the intermediate code based on a memory profiling library, processing the statistics file based on a plurality of models to provide a list of objects, the list of objects identifying types of memory respective objects should be stored to in a hybrid main memory system, and storing modified source code that is provided based on the source code and the list of objects.
Allowable Subject Matter
Claim(s) 8-9 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Re: Claim 8 (and its dependent claim(s) 9), the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: wherein each of the plurality of first memory cells is a first spin transfer torque (STT)-magnetoresistive random-access memory (MRAM) cell comprising a first magnetic memory element, and each of the plurality of second memory cells is a second STT MRAM cell comprising a second magnetic memory element, and wherein a perpendicular magnetic anisotropy of the first magnetic memory element is lower than a perpendicular magnetic anisotropy of the second magnetic memory element.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached on 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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