DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
However, should applicant desire to obtain the benefit of foreign priority under 35
U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of
the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and
41.202(e).
Failure to provide a certified translation may result in no benefit being accorded
for the non-English application.
Information Disclosure Statement
The information disclosure statement (IDS) filed on April 8th, 2024, is being
considered by the examiner.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because:
reference character "16” has been used to designate both “gate protrusion 16” and “gate recess 16” in paragraph [0014].
reference character “241” has been used to designate both “processing target side electrode 241” in paragraph [0024] and “object-side electrode 241” in paragraph [0024].
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 1, Claim 1 recites the limitations “the mutually opposing first side surface and second side surface of the protrusion” in line 15. There is insufficient antecedent basis for this limitation in the claim.
While “a first side surface” and “a second side surface” are introduced, it is unclear what side surfaces—side surfaces of the wafer or the recess, or the process chamber, or the protrusion?
For examination purposes, claim 1 has been interpreted as follows:
Claim 1: A method for manufacturing a semiconductor member, the method comprising: preparing a processing target comprising a wafer composed of a conductive semiconductor and a mask disposed on a top surface of the wafer; and photoelectrochemically etching the wafer by immersing the processing target in an etching solution and irradiating light from a top surface side of the wafer, wherein in the photoelectrochemical etching of the wafer, an outer portion of the mask of the wafer is etched to form a protrusion under the mask, and a first side surface of the protrusion and a second side surface of the protrusion opposite of the first side surface of the protrusion are etched until an entire width between the mutually opposing first side surface and second side surface of the protrusion is depleted, to automatically stop the etching of the first side surface and the second side surface.
Further, Claim 1 recites the limitation “depleted” where it is unclear what, exactly, is the scope of such a limitation as written. It is unclear what is meant by “the protrusion is depleted” and the scope is unclear—is the material of the protrusion itself being fully removed and used up, as in the plain language definition of “deplete”? Is the carrier concentration, such as the concentration of the n-type impurity Si disclosed in the specification, being depleted? Is this related to some sort of depletion layer, even though such would not exist in the protrusion under the light-blocking mask and far away from anything that could be considered a PN, or similar, junction?
The claim as written remains unclear and introduces uncertainty on what is meant by “depleted” in the context of the protrusion and so, therefore, the claim is rejected for being of indefinite scope.
Regarding Claims 2-4, as Claims 2, 3, and 4 all depend directly from independent Claim 1 and do not resolve the identified indefinite issues, they too are rejected for the same reasons as Claim 1 due to their dependence therefrom.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Hirikiri et al., US PGPub 2021/0351030 A1 (hereinafter referred to as “Hirikiri”), in view of Kajitani et al., US Patent No. 8253220 B2 (hereinafter referred to as “Kajitani”).
Regarding Claim 1, Hirikiri discloses a method for manufacturing a semiconductor member ([0009-0021]), the method comprising:
preparing a processing target comprising a wafer composed of a conductive semiconductor (FIG. 24D, wafer 100, GaN material 100; [0169]) and a mask disposed on a top surface of the wafer (FIG. 24D, light-blocking mask 41; [0169-0170]);
and photoelectrochemically etching the wafer by immersing the processing target in an etching solution (FIG. 24D, wafer 100, etching liquid 420; [0169-0170, 0174]) and irradiating light from a top surface side of the wafer (FIG. 24D, UV light 431; [0169-0170, 0174]),
wherein in the photoelectrochemical etching of the wafer, an outer portion of the mask of the wafer is etched to form a protrusion under the mask (see FIG. 24D below, etching areas 111, 112, 113; protrusions thereby formed between adjacent etching areas as indicated by red dashed box annotation below, [0174]),
and a first side surface and a second side surface are etched until an entire width between the mutually opposing first side surface and second side surface of the protrusion is depleted (see FIG. 24D below, sides of etching areas 111, 112, 113 are by necessity different side surfaces of the protrusion thereby formed between adjacent etching areas (see purple and red dashed arrow annotations below); [0174]),
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Hirikiri does not explicitly disclose to automatically stop the etching of the first side surface and the second side surface.
However, Kajitani, which is directed to a similar method of manufacturing semiconductor devices (such as nitride semiconductors) using photoelectrochemical etching, teaches that a highly selective etch can be achieved using photoelectrochemical etching and careful consideration of the basic principles thereof, such as using a layer with high defect density which will essentially function as an etch stop layer to enable, for example, automatic control and stopping of an etch (FIGs. 5A-5B, defect induced layer 108, current blocking layer 109, current injection portion 110; Col 2 lines 34-53, Col 6 lines 43-53, Col 7 lines 11-28).
This is expressly beneficial, particularly with respect to photoelectrochemical etching of conducting semiconductors such as GaN, for improving “fabrication accuracy and reproducibility” (Col 3 lines 52-61).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Hirikiri with the teachings of Kajitani to take advantage of the basic principles of photoelectrochemical etching of conductive semiconductors and to automatically stop the etching of the first side surface and the second side surface (FIGs. 5A-5B, defect induced layer 108, current blocking layer 109, current injection portion 110; Col 2 lines 34-53, Col 6 lines 43-53, Col 7 lines 11-28) by using different semiconductor layers, such as a layer of a conductive semiconductor with high defect density and one of a same conductive semiconductor without such, and apply such to, for example, the side surfaces of a protrusion under a mask (i.e., areas wherein etch control is paramount and desired) for the benefit of improving “fabrication accuracy and reproducibility” (Col 3 lines 52-61).
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Hirikiri in view of Kajitani (Hirikiri/Kajitani) as applied to claim 1 above, and further in view of Koike et al., US PGPub 2003/0134446 A1 (hereinafter referred to as “Koike”).
Regarding Claim 2, Hirikiri/Kajitani disclose the method for manufacturing a semiconductor member according to claim 1, as discussed above.
Neither Hirikiri nor Kajitani explicitly disclose wherein the mask includes a linear portion, and in the photoelectrochemical etching of the wafer, the protrusion including the linear portion having a width of 200 nm or more and 2000 nm or less at a narrowest portion is formed.
However, Koike, which is directed to similar semiconductor devices (such as GaN devices) with similar protrusions (mesas), teaches using grid-like mask shapes ([0165]) and reactive ion etching (RIE), or other etching techniques, for forming protrusions (i.e., mesas of GaN layer 31, [0177]) having a width of 1 μm for the benefit of reducing dislocation and strain at mask edges in subsequent process steps ([0005-0009]).
As taught by Hirikiri, not only does photoelectrochemical etching deliver results similar to other etching techniques applied to nitrides like GaN, such as dry etching like RIE, but it does so with the explicit advantages of causing “less damage compared to ordinary dry etching and also because the device used in the etching is more simple compared to special dry etching techniques that are designed to cause less damage” (Hirikiri [0003]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Hirikiri with the mask and width teachings of Koike wherein the mask includes a linear portion (grid-like mask shapes, [0165]), and in the photoelectrochemical etching of the wafer, the protrusion including the linear portion having a width of 200nm or more and 2000 nm or less at a narrowest portion is formed (mesas of GaN layer 31 of width of 1 μm which is more than 200nm and less than 2000nm, [0177]) for the benefit of reducing dislocation and strain at mask edges in subsequent process steps ([0005-0009]).
Regarding Claim 3, Hirikiri/Kajitani disclose the method for manufacturing a semiconductor member according to claim 1, as discussed above.
Neither Hirikiri nor Kajitani explicitly disclose wherein the mask includes an island-shaped portion, and in the photoelectrochemical etching of the wafer, the protrusion including the island-like portion having a width of 200 nm or more and 2000 nm or less at a narrowest portion is formed.
However, Koike, which is directed to similar semiconductor devices (such as GaN devices) with similar protrusions (mesas) and the method of manufacture thereof, teaches using island-like mask shapes ([0165]) and reactive ion etching (RIE), or other etching techniques, for forming protrusions (i.e., mesas of GaN layer 31, [0177]) having a width of 1 μm, for the benefit of reducing dislocation and strain at mask edges in subsequent process steps ([0005-0009]).
As taught by Hirikiri, not only does photoelectrochemical etching deliver results similar to other etching techniques applied to nitrides like GaN, such as dry etching like RIE, but it does so with the explicit advantages of causing “less damage compared to ordinary dry etching and also because the device used in the etching is more simple compared to special dry etching techniques that are designed to cause less damage” (Hirikiri [0003]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Hirikiri with the mask and width teachings of Koike disclose wherein the mask includes an island-shaped portion (grid-like mask shapes, [0165]), , and in the photoelectrochemical etching of the wafer, the protrusion including the island-like portion having a width of 200 nm or more and 2000 nm or less at a narrowest portion is formed (mesas of GaN layer 31 of width of 1 μm which is more than 200nm and less than 2000nm, [0177]) for the benefit of reducing dislocation and strain at mask edges in subsequent process steps ([0005-0009]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Hirikiri/Kajitani as applied to claim 1 above, and further in view of Hoshi et al., US PGPub 2017/0365665 A1 (hereinafter referred to as “Hoshi”).
Regarding Claim 4, Hirikiri/Kajitani disclose the method for manufacturing a semiconductor member according to claim 1, as discussed above.
Neither Hirikiri nor Kajitani explicitly disclose the method further comprising: forming a gate electrode that applies a gate voltage to a side surface of the protrusion, a source electrode disposed on one side of the protrusion in a vertical direction, and a drain electrode disposed on the other side of the protrusion in the vertical direction.
However, Hoshi, which is directed to semiconductor devices such as power MOSFET devices containing similar protrusions of similar materials as suggested in Hirikiri, Kajitani, and the instant specification, teaches gate electrodes for applying gate voltage to side surfaces of protrusions, a top source electrode, and a bottom drain electrode. Hoshi teaches that “power MOSFETs have low current density compared to bipolar transistors and IGBTs…but can be switched at high speeds up to about several MHz” ([0004]) and that it is possible to overcome the low current density deficiency of conventional power MOSFETs by using wide bandgap semiconductors “such as gallium nitride (GaN),” ([0006]) a similar material as used in Hirikiri and Kajitani, to achieve “a high-voltage semiconductor device” to satisfy “a strong demand in the market for a power semiconductor device that achieves both large current and high speed” ([0005-0006]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Hiriki/Kajitani with the electrode placement teachings of Hoshi for forming a gate electrode that applies a gate voltage to a side surface of the protrusion (FIG. 1, gate electrode 8 filling trench 6 and thus providing voltages to side surfaces of a protrusion, i.e., width w1 or mesa portion between adjacent trenches 6; [0031-0034]), a source electrode disposed on one side of the protrusion in a vertical direction (FIG. 1, front electrode 13; [0035]), and a drain electrode disposed on the other side of the protrusion in the vertical direction (FIG. 1, rear electrode 15 functioning as a drain electrode; [0037]) for the benefit of achieving “a high-voltage semiconductor device” to satisfy “a strong demand in the market for a power semiconductor device that achieves both large current and high speed” ([0005-0009]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Horikiri et al., US PGPub 2022/0148883 A1, which is similarly directed to a method of manufacturing a semiconductor structure using photoelectrochemical etching with a light-blocking mask and thus formed protrusions.
Horikiri et al., US PGPub 2022/0028737 A1, which is similarly directed to a method of manufacturing a semiconductor structure using photoelectrochemical etching of GaN and other such materials, with a light-blocking mask to pattern recesses and resultant protrusions.
Tamura et al., US PGPub 2008/0144684, which is directed to a method of manufacturing III-V multi-layer structures such as diodes and high electron mobility transistors using, at least, photoelectrochemical etching.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Austin T. Woodard whose telephone number is (571)270-1958. The examiner can normally be reached M-F, 8am to 5pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Austin T Woodard/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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