Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office action is in response to Applicant' s communication filed 7/15/2026 in response to the Office action dated 4/21/2026. No claims have been amended, added, or removed. Claims 1-19 and 21 are pending in this application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, and 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Cariello et al. (US 20200371702 A1), hereinafter Cariello (‘702), in view of Dover (US 20180276146 A1), and further in view of Mizuno (US 20070136606 A1).
Regarding claim 1, Cariello (‘702) teaches an apparatus comprising: a non-volatile memory configured to store a set of state values (Paragraph 17, descriptors [set of state values] are stored in non-volatile memory);
processor circuitry coupled to the non-volatile memory and configured to store data to the non-volatile memory (Paragraphs 2, 19, and 21; Fig. 1, host processor 106 configured to store data in storage system 110 containing non-volatile memory 113);
and security manager circuitry coupled to the non-volatile memory and configured to: access the set of state values (Paragraph 46; Fig. 3, step 302, host device [security manager circuitry] reads the device descriptors [state values] stored in the storage system) and;
determine a state of the non-volatile memory based on the set of state values (Paragraph 47; Fig. 3, element 303, determining a device is in a safe mode [state] based off an indication stored in a descriptor [state values]);
The Examiner notes that Cariello (‘702) teaches a request to enter a diagnostic mode. (Paragraph 12, device may enter a restricted operation mode such as a diagnostic mode which limits read/write access)
Cariello (‘702) does not explicitly teach responsive to obtaining a request to enter a diagnostic mode, authenticate credentials corresponding to the request (emphasis added), access circuitry coupled between the non-volatile memory and the processor circuitry, and control the access circuitry to couple the processor circuitry to the non-volatile memory based on determining that the state indicates that the non-volatile memory does not store a security key or to decouple the processor circuitry from the non-volatile memory based on determining that the state indicates that the non-volatile memory stores a security key.
However, Dover teaches responsive to obtaining a request to enter a diagnostic mode (Paragraphs 14, 27-28; Fig. 2, receiving control register management command/request which specifies the value of control registers that restrict access to memory (diagnostic mode similar to the one noted in Cariello (‘702) above)), and
authenticate credentials corresponding to the request (Paragraph 29; Fig. 2, step 2030, the memory system verifies the requester’s authorization via cryptographic signature [credentials]).
Cariello (‘702) and Dover are analogous art because they are in the same field of endeavor, that being memory access management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Cariello (‘702) to further include the authenticating of credentials corresponding to a mode request according to the teachings of Dover. The motivation for doing so would have been to protect sensitive information against attacks and unauthorized memory accesses (Dover, Paragraphs 11-12, 34).
Cariello (‘702) in view of Dover does not explicitly teach access circuitry coupled between the non-volatile memory and the processor circuitry, and control the access circuitry to couple the processor circuitry to the non-volatile memory based on determining that the state indicates that the non-volatile memory does not store a security key or to decouple the processor circuitry from the non-volatile memory based on determining that the state indicates that the non-volatile memory stores a security key.
However, Mizuno teaches access circuitry coupled between the non-volatile memory and the processor circuitry (Paragraphs 23, 26, 36; Fig. 1, storage controllers 15A,B are connected between host computers 10A,B (including processors 101) and storage device 20 [non-volatile memory]), and
control the access circuitry to couple the processor circuitry to the non-volatile memory based on determining that the state indicates that the non-volatile memory does not store a security key or to decouple the processor circuitry from the non-volatile memory based on determining that the state indicates that the non-volatile memory stores a security key (Paragraphs 37, 57, 60, 64-65; Figs. 1-2, allowing [coupling] host computer 10 to access storage volume 70 (of storage device 20) when determining that the volume does not store an encryption key [state] (state 205 indicated as SHARED/UNSHARED) and preventing access [decoupling] when determining that the volume is judged to be encryption key management volume 75 which stores an encryption key [state] (state 205 indicated as KEY STORED)).
Cariello (‘702), Dover, and Mizuno are analogous art because they are in the same field of endeavor, that being memory access management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Cariello (‘702) in view of Dover to further include the access circuitry and coupling/decoupling based on determining the state according to the teachings of Mizuno. The motivation for doing so would have been to prevent data leakage caused by unauthorized access of encryption keys (Mizuno, Paragraph 121).
Regarding claim 2, Cariello (‘702) in view of Dover, further in view of Mizuno teaches the apparatus of claim 1, wherein the credentials include manufacturer credentials and device credentials (Dover, Paragraph 19, authentication is performed with pre-installed public keys [device credentials] that have been issued by a trusted manufacturer [manufacturer credentials])
Regarding claim 3, Cariello (‘702) in view of Dover, further in view of Mizuno teaches the apparatus of claim 1, wherein the processor circuitry is configured to cause the set of state values to be stored based on the storing of the data to the non-volatile memory (Cariello (‘702), Paragraph 35; Fig. 2, descriptor field 200 [state value] stores information on how many reserved blocks have been consumed [data stored]).
Regarding claim 5, Cariello (‘702) in view of Dover, further in view of Mizuno teaches the apparatus of claim 1, wherein the state of the non-volatile memory corresponds to a key provisioned state, a code provisioned state, or a non-volatile memory failure state (Cariello (‘702), Paragraph 12, in response to detecting a threshold number of blocks have failed [memory failure], the device is placed in a safe mode [memory failure state]).
Regarding claim 6, Cariello (‘702) in view of Dover teaches the apparatus of claim 5 and the security manager circuitry is configured to determine the state (Cariello (‘702), Paragraphs 46-48; Fig. 3, elements 302-303, 305-306, host device [security manager circuitry] reads descriptors which indicate whether or not a memory system is in a restricted operation mode, wherein write/read access is restricted).
Cariello (‘702) in view of Dover does not explicitly teach to control the access circuitry to decouple the processor circuitry from the non-volatile memory based on determining that the state corresponds to the key provisioned state or the code provisioned state.
However, Mizuno teaches to control the access circuitry to decouple the processor circuitry from the non-volatile memory based on determining that the state corresponds to the key provisioned state or the code provisioned state (Paragraphs 23, 57, 60, 64-65; Figs. 1-2, storage controllers 15A,B prevents [decouples] host computer 10 from accessing a storage volume upon judging that the volume is encryption key management volume 75 which holds an encryption key [key provisioned state] (state 205 indicated as KEY STORED)).
Cariello (‘702), Dover, and Mizuno are analogous art because they are in the same field of endeavor, that being memory access management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Cariello (‘702) in view of Dover to further include the access circuitry and coupling/decoupling based on determining the key-provisioned state according to the teachings of Mizuno. The motivation for doing so would have been to prevent data leakage caused by unauthorized access of encryption keys (Mizuno, Paragraph 121).
Regarding claim 7, Cariello (‘702) in view of Dover, further in view of Mizuno teaches the apparatus of claim 1, wherein the security manager circuitry is configured to transition to the diagnostic mode based on the authentication of the credentials (Dover, Paragraphs 14, 28-29, 31; Fig. 2, steps 2030 and 2070, after authenticating the requester’s cryptographic signature [credentials], the value of the control registers may be extended, limiting memory access (diagnostic mode similar to the one noted in Cariello (‘702) above)).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Cariello (‘702) in view of Dover, further in view of Mizuno as applied to claim 1 above, and further in view of Park et al. (US 20180196949 A1), hereinafter Park.
Regarding claim 4, Cariello (‘702) in view of Dover, further in view of Mizuno teaches the apparatus of claim 1, and wherein the security manager circuitry (Cariello (‘702), Paragraph 19; Fig. 1, host device 105 [security manager circuitry]) is configured to:
control the access circuitry to couple the processor circuitry to the non-volatile memory based on determining the state (Mizuno, Paragraphs 23, 57, 60, 64-65; Figs. 1-2, storage controllers 15A,B allows [couples] host computer 10 to access storage volume 70 based on determining whether the volume does not store an encryption key [state]).
Cariello (‘702) in view of Dover, further in view of Mizuno does not explicitly teach wherein the state corresponds to a non-volatile memory failure.
However, Park teaches wherein the state corresponds to a non-volatile memory failure (Paragraphs 60, 64; Figs. 3B, 3C, operations 3, 5, in response to detecting a system failure, access controller 150 unsecures memory area B to allow a ramdump of the entire external memory 200).
Cariello (‘702), Dover, Mizuno, and Park are in the same field of endeavor, that being memory access management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Cariello (‘702) in view of Dover, further in view of Mizuno to further include the determining the state of non-volatile memory failure according to the teachings of Park. The motivation for doing so would have been to recover from a memory failure via analysis and debugging (Park, Paragraphs 3-4).
Claims 8-9 and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Cariello (‘702) in view of Dover, and further in view of Mizuno and Cariello et al. (US 20230046313 A1), hereinafter Cariello (‘313).
Regarding claim 8, Cariello (‘702) teaches a method comprising: accessing state values stored in non-volatile memory (Paragraphs 17 and 46; Fig. 3, step 302, reading the device descriptors [state values] stored in non-volatile memory),
the state values corresponding to a state of the non-volatile memory (Paragraph 17, descriptors indicate the configuration/health/protection state of a storage device) and;
determining the state of the non-volatile memory based on the state values (Paragraph 47; Fig. 3, element 303, determining a device is in a safe mode [state] based off an indication stored in a descriptor [state values]).
The Examiner notes that Cariello (‘702) teaches a request to enter a diagnostic mode. (Paragraph 12, device may enter a restricted operation mode such as a diagnostic mode which limits read/write access)
Cariello (‘702) does not explicitly teach responsive to obtaining a request to enter a diagnostic mode, authenticate credentials corresponding to the request (emphasis added), and determining whether to control access circuitry to couple the non-volatile memory to a bus or to decouple the non-volatile memory from the bus based on the determined state, including decoupling the non-volatile memory based on determining that the state indicates that the non-volatile memory stores a security key.
However, Dover does teach responsive to obtaining a request to enter a diagnostic mode (Paragraphs 14, 27-28; Fig. 2, receiving control register management command/request which specifies the value of control registers that restrict access to memory (diagnostic mode similar to the one noted in Cariello (‘702) above)), and
authenticate credentials corresponding to the request (Paragraph 29; Fig. 2, step 2030, the memory system verifies the requester’s authorization via cryptographic signature [credentials]).
Cariello (‘702) and Dover are analogous art because they are in the same field of endeavor, that being memory access management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Cariello (‘702) to further include the authenticating of credentials corresponding to a mode request according to the teachings of Dover. The motivation for doing so would have been to protect sensitive information against attacks and unauthorized memory accesses (Dover, Paragraphs 11-12, 34).
Cariello (‘702) in view of Dover does not explicitly teach determining whether to control access circuitry to couple the non-volatile memory to a bus or to decouple the non-volatile memory from the bus based on the determined state, including decoupling the non-volatile memory based on determining that the state indicates that the non-volatile memory stores a security key.
However, Cariello (‘313) teaches determining whether to control access circuitry to couple the non-volatile memory to a bus or to decouple the non-volatile memory from the bus based on the determined state (Paragraph 39; Fig. 2, controller 215 [access circuitry] couples or decouples memory device 230 from data bus 205 based on the chip enable state).
Cariello (‘702), Dover, and Cariello (‘313) are analogous art because they are in the same field of endeavor, that being memory access management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Cariello (‘702) in view of Dover to further include the access circuitry and buses according to the teachings of Cariello (‘313). The motivation for doing so would have been to reduce system latency (Cariello (‘313), Paragraph 34).
Cariello (‘702) in view of Dover, further in view of Cariello (‘313) does not explicitly teach including decoupling the non-volatile memory based on determining that the state indicates that the non-volatile memory stores a security key.
However, Mizuno teaches including decoupling the non-volatile memory based on determining that the state indicates that the non-volatile memory stores a security key (Paragraphs 57, 60, 64-65; Figs. 1-2, preventing access to [decoupling] a storage volume based on judging that the volume is encryption key management volume 75 which stores an encryption key [state] (state 205 indicated as KEY STORED)).
Cariello (‘702), Dover, Cariello (‘313) and Mizuno are analogous art because they are in the same field of endeavor, that being memory access management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Cariello (‘702) in view of Dover, further in view of Cariello (‘313) to further include decoupling the non-volatile memory based on determining that the state indicates that it stores a security key according to the teachings of Mizuno. The motivation for doing so would have been to prevent data leakage caused by unauthorized access of encryption keys (Mizuno, Paragraph 121).
Regarding claim 9, this is a method version of the claimed apparatus discussed above (claim 2, respectively), wherein all claim limitations also have been addressed and/or covered in the cited areas as set forth above. Thus, accordingly, this claim is also obvious over Cariello (‘702) in view of Dover, further in view of Cariello (‘313) and Mizuno.
Regarding claim 12, this is a method version of the claimed apparatus discussed above (claim 5, respectively), wherein all claim limitations also have been addressed and/or covered in the cited areas as set forth above. Thus, accordingly, this claim is also obvious over Cariello (‘702) in view of Dover, further in view of Cariello (‘313) and Mizuno.
Regarding claim 13, Cariello (‘702) in view of Dover, further in view of Cariello (‘313) and Mizuno teaches the method of claim 12, wherein determining to decouple the non-volatile memory from the bus is performed (Cariello (‘313), Paragraph 39; Fig. 2, controller 215 [access circuitry] decouples memory device 230 from data bus 205 based on the chip enable state)
based on determining that the state corresponds to the key provisioned state or the code provisioned state (Mizuno, Paragraphs 57, 60, 64-65; Figs. 1-2, preventing access to [decoupling] a storage volume based on judging that the volume is encryption key management volume 75 which stores an encryption key [key-provisioned state]).
Regarding claim 14, this is a method version of the claimed apparatus discussed above (claim 7, respectively), wherein all claim limitations also have been addressed and/or covered in the cited areas as set forth above. Thus, accordingly, this claim is also obvious over Cariello (‘702) in view of Dover, further in view of Cariello (‘313) and Mizuno.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Cariello (‘702) in view of Dover, further in view of Cariello (‘313) and Mizuno as applied to claim 8 above, and further in view of Klapman (US 20230004290 A1).
Regarding claim 10, Cariello (‘702) in view of Dover, further in view of Cariello (‘313) and Mizuno teaches the method of claim 8, but does not explicitly teach wherein a user defines the state.
However, Klapman teaches wherein a user defines the state (Paragraph 62, the user operates to change the data access state of the device).
Cariello (‘702), Dover, Cariello (‘313), Mizuno and Klapman are in the same field of endeavor, that being memory access management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Cariello (‘702) in view of Dover, further in view of Cariello (‘313) and Mizuno to further include the user defining the state according to the teachings of Klapman. The motivation for doing so would have been to allow selectively securing stored data against unauthorized access (Klapman, Paragraph 47).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Cariello (‘702) in view of Dover, further in view of Cariello (‘313) and Mizuno as applied to claim 8 above, and further in view of Park.
Regarding claim 11, Cariello (‘702) in view of Dover, further in view of Cariello (‘313) and Mizuno teaches the method of claim 8, wherein determining to control the access circuitry to couple the non-volatile memory to the bus is performed based on determining the state (Cariello (‘313), Paragraph 39; Fig. 2, controller 215 [access circuitry] couples memory device 230 to data bus 205 based on the chip enable state).
Cariello (‘702) in view of Dover, further in view of Cariello (‘313) and Mizuno does not explicitly teach wherein the state corresponds to a non-volatile memory failure.
However, Park teaches wherein the state corresponds to a non-volatile memory failure. (Paragraphs 60, 64; Figs. 3B, 3C, operations 3, 5, in response to detecting a system failure, access controller 150 unsecures memory area B to allow a ramdump of the entire external memory 200).
Cariello (‘702), Dover, Cariello (‘313), Mizuno, and Park are in the same field of endeavor, that being memory access management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Cariello (‘702) in view of Dover, further in view of Cariello (‘313) and Mizuno to further include the determining the state of non-volatile memory failure according to the teachings of Park. The motivation for doing so would have been to recover from a memory failure via analysis and debugging (Park, Paragraphs 3-4).
Claims 15-17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Cariello (‘702) in view of Mizuno.
Regarding claim 15, Cariello (‘702) teaches a device comprising: a non-volatile memory that includes a memory bank configured to store a set of state values (Paragraph 46; Fig. 3, step 302, host device reads the device descriptors [state values] stored in the storage system)
corresponding to a state of the non-volatile memory (Paragraphs 17 and 21, descriptors indicate the configuration/health/protection state of a non-volatile storage device);
and a memory controller coupled to the non-volatile memory (Paragraph 21; Fig. 1, memory controller 111 coupled with non-volatile memory 112)
and configured to write the set of state values to the memory bank based on the state of the non-volatile memory (Paragraphs 26, 40-41; Fig. 1, memory controller 111 updates the device descriptors of non-volatile memory device 112),
wherein a first state of the non-volatile memory indicates a fault in the non-volatile memory (Paragraph 12, recognizing a fault in the memory device and placing the device in a safe mode [first state] in response), and
the memory controller enables access to the non-volatile memory in the first state of the non-volatile memory (Paragraphs 30, 41-42; Fig. 1, the memory device activates safe mode, which enables read command access to the non-volatile memory 112).
Cariello (‘702) does not explicitly teach wherein a second state indicates that the non-volatile memory stores a security key, and the memory controller is configured to disable access to the non-volatile memory in the second state of the non-volatile memory.
However, Mizuno teaches wherein a second state indicates that the non-volatile memory stores a security key, and the memory controller is configured to disable access to the non-volatile memory in the second state of the non-volatile memory (Paragraphs 23, 36-37, 57, 60, 64-65; Figs. 1-2, storage controllers 15A,B prevent access a storage volume [non-volatile memory] upon determining that the volume is encryption key management volume 75 which stores an encryption key [second state] (state 205 indicated as KEY STORED))
Cariello (‘702) and Mizuno are analogous art because they are in the same field of endeavor, that being memory access management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the non-volatile memory of Cariello (‘702) to further include the access prevention in response to determining that the non-volatile memory stores a security key according to the teachings of Mizuno. The motivation for doing so would have been to prevent data leakage caused by unauthorized access of encryption keys (Mizuno, Paragraph 121).
Regarding claim 16, Cariello (‘702) in view of Mizuno teaches the non-volatile memory of claim 15, wherein the memory bank includes three memory cells that store data corresponding to the state of the non-volatile memory (Cariello (‘702), Paragraphs 17 and 30; Fig. 5, descriptors [data corresponding to the state] are stored in non-volatile memory 112 which are composed of a plurality of memory cells).
Regarding claim 17, Cariello (‘702) in view of Mizuno teaches the non-volatile memory of claim 15, wherein the state of the non-volatile memory corresponds to a key provisioned state, a code provisioned state, or a non-volatile memory failure state (Cariello (‘702), Paragraph 12, in response to detecting a threshold number of blocks have failed [memory failure], the device is placed in a safe mode [memory failure state]).
Regarding claim 19, Cariello (‘702) in view of Mizuno teaches the non-volatile memory of claim 15, wherein the memory controller is configured to prevent the set of state values from being written to the memory bank when the set of state values correspond to an unused state (Cariello (‘702), Paragraphs 13, 36-37; Fig. 2, when descriptor 200 [state values] indicate a permanent write protect mode (a previously unused state), data (interpreted to include descriptor data) is prevented from being written to memory).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Cariello (‘702) in view of Mizuno as applied to claim 15 above, and further in view of Dover.
Regarding claim 18, Cariello (‘702) in view of Mizuno teaches the non-volatile memory of claim 15 and the state values (Paragraph 17, descriptors).
Cariello (‘702) in view of Mizuno does not explicitly teach further including a direct access memory controller to cause the set of values to be stored in a register of security manager circuitry.
However, Dover teaches further including a direct access memory controller to cause the set of values to be stored in a register of security manager circuitry (Paragraph 25; Fig. 1, controller 1050 [direct access memory controller] sets [stores] values in control registers 1080-1100 in volatile memory 1070 [security manager circuitry]).
Cariello (‘702), Mizuno, and Dover are analogous art because they are in the same field of endeavor, that being memory access management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the non-volatile memory of Cariello (‘702) in view of Mizuno to further include the direct access memory controller storing values in security manager circuitry according to the teachings of Dover. The motivation for doing so would have been to allow faster access of state values by storing them in volatile memory (Dover, Paragraphs 35-36).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Cariello (‘702) in view of Dover, further in view of Mizuno as applied to claim 1 above, and further in view of Gale et al. (US 20210191479 A1), hereinafter Gale.
Regarding claim 21, Cariello (‘702) in view of Dover, further in view of Mizuno teaches the apparatus of claim 1, but does not explicitly teach wherein the diagnostic mode is entered after the apparatus has been deployed and then returned to the manufacturer.
However, Gale teaches wherein the diagnostic mode is entered after the apparatus has been deployed and then returned to the manufacturer (Paragraphs 58-59, after determining a data storage requires servicing, initiating a service [diagnostic] mode to allow a technician or other personnel to service the storage).
Cariello (‘702), Dover, Mizuno, and Gale are in the same field of endeavor, that being data storage protection. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Cariello (‘702) in view of Dover, further in view of Mizuno to further include the entering a diagnostic mode after deployment and return according to the teachings of Gale. The motivation for doing so would have been to protect the data storage during servicing (Gale, Paragraphs 58-59).
Response to Arguments
Applicant’s arguments (see pages 1-4 of the remarks) filed 7/15/2026, with respect to the rejections of claims 1-3, 5-9, 12-17, and 19 under 35 U.S.C 103 have been fully considered, but are not persuasive.
The Applicant argues that Mizuno does not teach or suggest the limitations: “control the access circuitry to couple the processor circuitry to the non-volatile memory based on determining that the state indicates that the non-volatile memory does not store a security key or to decouple the processor circuitry from the non-volatile memory based on determining that the state indicates that the non-volatile memory stores a security key” in claim 1, similarly “decoupling the non-volatile memory based on determining that the state indicates that the non-volatile memory stores a security key” in claim 8, and “wherein a second state indicates that the non-volatile memory stores a security key, and the memory controller is configured to disable access to the non-volatile memory in the second state of the non-volatile memory” in claim 15. The Applicant argues that Mizuno fails to teach or suggest the limitations above since the state value of Mizuno’s volume management table is not employed by the storage controllers when selectively limiting access to the various storage volumes.
Upon further examination, the Examiner agrees with the Applicant’s sentiment that the state value of Mizuno is merely indicative rather than causal to the access restriction of volumes. However, Mizuno is still configured to allow access based on determining that the storage volume does not hold a key (Paragraphs 37, 57, 65; Fig. 1, authorizing access to a storage volume 70 based on determining that the volume stores data and not an encryption key) and to disallow access based on determining that the storage volume does hold a key (Paragraphs 37, 57, 60, 65; Fig. 1, preventing access to a storage volume 75 based on determining that the volume is encryption key management volume 75, which stores an encryption key), wherein the “state” of the storage volume is now based on whether or not the volume stores a key rather than a logical representation on a table.
Thus, the Examiner argues that the newly cited areas of Mizuno practically teach the contested limitations, and further notes any other arguments in regard to claims 1-3, 5-9, 12-17, and 19 are consummate in scope with the argument above. Thus, the Examiner maintains the rejection.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason Pinga whose telephone number is (571) 272-2620. The examiner can normally be reached on M-F 8:30am-6pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla, can be reached on (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/J.M.P./Examiner, Art Unit 2137
/TRACY A WARREN/Primary Examiner, Art Unit 2137
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