DETAILED ACTION Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The RCE filed 04/29/2026 has been entered. Claims 1-15 and 17-20 are pending in the application.
The Applicant’s amendment overcomes the 35 U.S.C. 112(b) rejections from the previously filed Office Action.
Response to Arguments
Applicant’s arguments in the remarks filed on 04/29/2026 with respect to independent claims 1,10 and 15 have been fully considered but they are not persuasive.
The Applicant argues on page 2 of the remarks filed on 04/29/2026:
“FIG. 6 of Wu shows a memory 670, a machine learning accelerator 640, a system interconnect 615, and a sensor 622 connected to the system interconnect 615 via input/output (I/O) devices 620. Wu (e.g., Par. [0042]) suggests that the sensor 622 can include "a camera, radar, or LiDAR sensor". Thus, since the entire "radar" (e.g., 622) as suggested in Wu (e.g., Par. [0042]) is represented by a single black box 622 labeled "Sensor", a person of ordinary skill in relevant fields would recognize that the memory 670 and the machine learning accelerator 640 are part of the host system to which the "radar" (e.g., 622) is connected via one of the input/output (I/O) devices 620.”
The Examiner respectfully disagrees. The “a radar portion” in the claims can be defined as any portion of the device including a radar and any additional components based on the broadest reasonable interpretation of “a radar portion”. Therefore, the Examiner has defined the “a radar portion” to include all system 600 components excluding the network 630 and central compute server 635. The “radar” is element 622, however, this radar coupled to the memory and processors of Fig. 6 and all other components excluding the network 630 and central compute server 635 is indeed the “a radar portion”. Furthermore, the Applicant is arguing that the memory 670 and machine learning accelerator 640 are integral parts to the central compute server. Nothing in the disclosure or Figures of Wu suggests this. In fact, Fig. 6 clearly shows that the central compute server (i.e. a host system) is connected to the rest of the system of Fig. 6 via only a network 630 (i.e. a host interface). Therefore, this central compute server is need “separated” from the “a radar portion” via the network 630. Furthermore, paragraph 0038 recites, “FIG. 5B illustrates a sensor fusion system architecture having uni-modal sensors (e.g., cameras) each having a separate, but overlapping, field of view. Edge sensors 520 perform preprocessing and feature extraction and the extracted features from each sensor module are transported over network 525 to central compute server 530. The central compute server performs composite blending of the three separate, overlapping fields of view feature maps to generate a wide field of view feature map” and paragraph 0041 recites, “FIGS. 5A-5D illustrate examples of how various portions of the sensor fusion processing can be distributed between the edge sensor and network gateway nodes prior to the data arriving at a central compute server for processing.”. These paragraphs clearly show that the pre-processed data and extracted feature are transported via the network and then arrive at the central compute server. Therefore, this central compute server is indeed separate from the memory and machine learning accelerator and the other components of Fig. 6.
The Applicant further argues on page 3 of the remarks:
“On the other hand, the memory 670 and the machine learning accelerator 640 of Wu are external components to which the sensor/radar (e.g., 622) is interconnected via a system interconnect 615. The system interconnect 615 connects the sensor/radar (e.g., 622) to typical components of a computer system, such as "processor cores" 610, network ports 625, peripherals 650, etc. Since the entire sensor/radar 622 in FIG. 6 of Wu is represented by a single black box, the computing system 600 of Wu does not have a section that corresponds to the specific structures of "radar portion" recited in claim 1.”.
Again, the Examiner finds this argument to be unpersuasive. The Applicant is interpreting “a radar portion” as just element 622, where the broadest reasonable interpretation of “a radar portion” is as any portion of the device including a radar and any additional components. The Examiner has defined the “a radar portion” to include all system 600 components excluding the network 630 and central compute server 635. The “radar” is element 622, however, this radar coupled to the memory and processors of Fig. 6 and all other components excluding the network 630 and central compute server 635 is indeed the “a radar portion”.
Therefore the Examiner asserts that Wu (US 20210406674 A1) in view of Tremblay et al. (US 20210125036 A1) does indeed disclose the claimed limitations of claim 1. The same arguments apply to independent claims 10 and 15.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-13,15,17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 20210406674 A1) in view of Tremblay et al. (US 20210125036 A1), hereinafter Tremblay.
Regarding claim 1, Wu discloses [Note: what Wu fails to disclose is strike-through]
An apparatus (see apparatus of Fig. 6), comprising:
a radar portion (see Fig. 6, where “a radar portion” is defined to include all apparatus 600 components excluding the network 630 and central compute server 635.”), having:
a transceiver configured to transmit radar waves and receive reflections of the radar waves (Fig. 6, sensor devices 622; Paragraph 0042, “Further coupled to the system interconnect are input/output devices 620, including sensor devices 622 (e.g., a camera, radar, or LiDAR sensor), along with other associated controllers.”);
a circuit (Paragraph 0043, Machine learning accelerator 940) configured to generate data representative of a radar image based on the reflections of the radar waves received in the transceiver (Paragraph 0043, “A machine learning accelerator 640 is also communicatively coupled to processor cores 910, along with a signal processor 645…Through the system interconnect, any of the processor cores can provide instructions to the machine learning accelerator. Similarly, the signal processor can communicate with the processor cores, the machine learning accelerator, and the I/O devices and is configured to process image/radar/LiDAR signals from the sensors depending upon the application.”);
at least one processing unit configured to execute instructions implementing matrix computation of an artificial neural network (Paragraph 0051, “In a further aspect, the sensor device further includes a memory coupled to the feature extraction processor and storing one or more filter matrices used for performing the convolution layer analysis.”, where the convolution analysis is performed by the neural network in central compute server),
memory (Fig. 6, memory 670; Paragraph 0051, “In a further aspect, the sensor device further includes a memory coupled to the feature extraction processor and storing one or more filter matrices used for performing the convolution layer analysis.”) configured to store data representative of matrices of the artificial neural network (Paragraph 0051, “In a further aspect, the sensor device further includes a memory coupled to the feature extraction processor and storing one or more filter matrices used for performing the convolution layer analysis.”) and instructions executable by the at least one processing unit (Paragraph 0043, “A machine learning accelerator 640 is also communicatively coupled to processor cores 910, along with a signal processor 645. Machine learning accelerator 940 is circuitry dedicated to performing machine learning tasks associated with feature extraction, as discussed above, including, for example, the convolution and pooling layers of a convolutional neural network. Through the system interconnect, any of the processor cores can provide instructions to the machine learning accelerator.”) to generate an output of the artificial neural network having the radar image as an input, wherein the artificial neural network is configured to identify features in the radar image in the output (Fig. 6, feature extraction system 675 extracts features from the radar data input to the machine learning model; Paragraph 0045, “Feature extraction system 675 performs the tasks described above with regard to preprocessing and generating a feature map from data provided by sensor 622 associated with the applications processor.”); and
a host interface (Fig. 6, network 630) coupled between, and operatable to provide a wired or wireless connection between the radar portion and a host system (implicit all data transfer is either wired or wireless, further see Fig. 6, the central compute server 635 is “a host system” to which the network 630 (i.e. host interface) is coupled between “the radar portion” and the host system (i.e. central compute server 635); Note: the apparatus of Fig. 6 excluding the host system 635 and network 630 is defined as “the radar portion” as it includes a radar sensors and processing units), separated by the host interface from the radar portion (see Fig. 6, where the network 630 separates the “a radar portion” from the central compute server 635), wherein the radar portion is configured to transmit, via the wired or wireless connection to the host system (Fig. 6, Central compute server 635 is the “host system” which receives the transmitted data), data representative of a description of the features identified via the artificial neural network from the radar image (see paragraph 0043, “A machine learning accelerator 640 is also communicatively coupled to processor cores 910, along with a signal processor 645. Machine learning accelerator 940 is circuitry dedicated to performing machine learning tasks associated with feature extraction, as discussed above, including, for example, the convolution and pooling layers of a convolutional neural network. Through the system interconnect, any of the processor cores can provide instructions to the machine learning accelerator. “ further see paragraph 0049, “Once the feature extraction has been performed, the extracted feature maps can be transmitted to a network coupled to the edge sensor (740). As discussed above, the extracted feature map may be transmitted to a central compute server or additional computation on the extracted feature map may be performed at, for example, a gateway node to the network. In some embodiments, multiple network nodes between the edge sensor and the central compute server can perform computation on extracted feature map prior to sending the information to the central compute server.”, where the extracted feature map is “data representative of a description of the features identified via the artificial neural network from the radar image”; further see Fig. 3 and paragraph 0031 for support).
Tremblay discloses,
wherein the at least one processing unit includes a matrix-matrix unit configured to operate on two matrix operands of an instruction (Paragraph 0142, “In at least one embodiment, inference and/or training logic 2915 may include, without limitation, one or more arithmetic logic unit(s) (“ALU(s)”) 2910, including integer and/or floating point units, to perform logical and/or mathematical operations based, at least in part on, or indicated by, training and/or inference code (e.g., graph code), a result of which may produce activations (e.g., output values from layers or neurons within a neural network) stored in an activation storage 2920 that are functions of input/output and/or weight parameter data stored in code and/or data storage 2901 and/or code and/or data storage 2905. In at least one embodiment, activations stored in activation storage 2920 are generated according to linear algebraic and or matrix-based mathematics performed by ALU(s) 2910 in response to performing instructions or other code, wherein weight values stored in code and/or data storage 2905 and/or data 2901 are used as operands along with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and/or data storage 2905 or code and/or data storage 2901 or another storage on or off-chip.”, where the parallel processing in Fig. 42A implements matrix-matrix unit configured to operate on two matrix operands of an instruction.”, further see, Fig. 42A, parallel processing unit; Paragraph 0353, “In at least one embodiment, inference and/or training logic 2915 may be used in system FIG. 4100 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. In at least one embodiment, a neural network that determines an orientation of an object from an image is implemented with a parallel processor as described below.”; Paragraph 0354, “In at least one embodiment, illustrated parallel processor 4200 is a variant of one or more parallel processor(s) 4112 shown in FIG. 41 according to an exemplary embodiment.”);
It would have been obvious to someone in the art prior to the effective filing date of the claimed invention to modify Wu with Tremblay to incorporate the features of mentioned above. Both Wu and Tremblay are considered analogous arts as they both disclose systems and methods utilizing radar technology to recognize and identify objects by the use of machine learning accelerators. The combination of Wu and Tremblay would be obvious with a reasonable expectation of success in order to provide a fast and efficient transfer, storage and processing of the data for the deep machine learning system (see paragraphs 0187 and 0194 of Tremblay).
Regarding claim 2, Wu discloses [Note: what Wu fails to disclose is strike-through]
The apparatus of claim 1 (see apparatus of Fig. 6), wherein the radar portion further comprises: an image sensor (Fig. 6, sensor devices 622; Paragraph 0042, “Further coupled to the system interconnect are input/output devices 620, including sensor devices 622 (e.g., a camera, radar, or LiDAR sensor), along with other associated controllers.”) configured to generate data representative of an optical image of a scene corresponding to the radar image (Paragraph 0037, “FIGS. 5A-5D are simplified block diagrams illustrating configuration examples of distributed sensor fusion architectures incorporating embodiments of the present invention. FIG. 5A illustrates a sensor fusion system architecture having multi-modal sensors (R=radar, C=camera, L=LiDAR) each having a same field of view.”), wherein the memory (Paragraph 0051, “In a further aspect, the sensor device further includes a memory coupled to the feature extraction processor and storing one or more filter matrices used for performing the convolution layer analysis. In yet another aspect, the sensor includes one or more of a camera, a radar, and a lidar.”).
Tremblay discloses,
wherein the memory comprises random access memory (Fig. 42A; Paragraph 0363, “In at least one embodiment, memory units 4224A-4224N can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.”).
It would have been obvious to someone in the art prior to the effective filing date of the claimed invention to modify Wu with Tremblay to incorporate the features of: wherein the memory comprises random access memory. Both Wu and Tremblay are considered analogous arts as they both disclose systems and methods utilizing radar technology to recognize and identify objects by the use of machine learning accelerators. However, Wu fails to specifically disclose the feature of, wherein the memory comprises random access memory. Tremblay discloses such a feature in its computing apparatus in 42A. Furthermore, Tremblay discloses that all the elements in Fig. 42A can be located on a single integrated circuit in paragraph 0352, “In at least embodiment, components of computing system 4100 may be integrated with one or more other system elements on a single integrated circuit.”. The combination of Wu and Tremblay would be obvious with a reasonable expectation of success in order to provide a well-known type of computer memory which can be read and changed in any order to increase system performance within system memory constraints (see paragraph 0139 of Tremblay).
Regarding claim 3, Wu further discloses
The apparatus of claim 4, wherein the at least one processing unit is formed on an integrated circuit die as a field-programmable gate array (FPGA) or application specific integrated circuit (ASIC) (Paragraph 0030, “In order to perform these tasks, vision, radar, and LiDAR processing chipsets can include feature extraction processing, such as special purpose ASICs and the like.”); the random access memory is formed on one or more integrated circuit dies (Paragraph 0063, “Also for example, in one embodiment, the illustrated elements of system 600 are circuitry located on a single integrated circuit or within a same device.); and the at least one processing unit and the random access memory are packaged in the same integrated circuit device (Paragraph 0063, “Also for example, in one embodiment, the illustrated elements of system 600 are circuitry located on a single integrated circuit or within a same device.”).
Regarding claim 4, Wu further discloses
The apparatus of claim 2, wherein the image sensor is formed on an integrated circuit die and packaged in a same integrated circuit device that contains the random access memory (Paragraph 0063, “Also for example, in one embodiment, the illustrated elements of system 600 are circuitry located on a single integrated circuit or within a same device.”).
Regarding claim 5, Wu further discloses
The apparatus of claim 4, wherein at least a portion of the circuit configured to generate the data representative of the radar image is packaged within the same integrated circuit device that contains the random access memory (Paragraph 0063, “Also for example, in one embodiment, the illustrated elements of system 600 are circuitry located on a single integrated circuit or within a same device.”).
Regarding claim 6, Wu further discloses
The apparatus of claim 5, wherein the data representative of the radar image and the data representative of the optical image are generated and consumed within the same integrated circuit device as the input to the artificial neural network (Paragraph 0063, “Also for example, in one embodiment, the illustrated elements of system 600 are circuitry located on a single integrated circuit or within a same device.”).
Regarding claim 7, Wu further discloses [Note: what Wu fails to disclose is strike-through]
The apparatus of claim 3, wherein the image sensor and the circuit configured to generate the data representative of the radar image to have separate connections to write image data into the random access memory (Paragraph 0024, “As illustrated in FIG. 1, the various sensors are placed around the vehicle and provide network connections to several gateway nodes. The gateway nodes can be smart switches that gather the data from the various sensors [i.e. camera, radar, etc.] and provide that information to a central processor 110.”, where “gathering data” implies the writing of the data into memory and is done through different gateway nodes (i.e. separate connections))
Tremblay discloses,
the circuit configured to write image data into the random access memory concurrently (Fig 42A, Paragraph 0359, “In at least one embodiment, during processing, transferred data can be stored to on-chip memory (e.g., parallel processor memory 4222) during processing, then written back to system memory.”, where the “transferred data” is indicated of data obtained from various sensors and a parallel processor memory stores this data concurrently).
It would have been obvious to someone in the art prior to the effective filing date of the claimed invention to modify Wu with Tremblay to incorporate the features mentioned above. Both Wu and Tremblay are considered analogous arts as they both disclose systems and methods utilizing radar technology to recognize and identify objects by the use of machine learning accelerators. However, Wu fails to specifically disclose the feature of where the data obtained from these sensors is stored into a memory concurrently. Tremblay discloses such a feature in its computing apparatus in 42A where the parallel processing memory stores transferred data concurrently into memory. Furthermore, Tremblay discloses that all the elements in Fig. 42A can be located on a single integrated circuit in paragraph 0352, “In at least embodiment, components of computing system 4100 may be integrated with one or more other system elements on a single integrated circuit.”. The combination of Wu and Tremblay would be obvious with a reasonable expectation of success in order provide to a fast an efficient transfer and storage of data for the machine learning system (see paragraphs 0139 and 0191 of Tremblay).
Regarding claim 8, Wu further discloses
The apparatus of claim 3, wherein the field-programmable gate array (FPGA) or application specific integrated circuit (ASIC) implements a deep learning accelerator (Fig. 6, machine learning accelerator, 640 is an ASIC; Paragraph 0015, “Embodiments enhance efficiency of these tasks by providing a specialized processor or accelerator (e.g., ASICs) to perform the machine learning associated tasks at the edge nodes and also reduce the amount of data transferred in the network.”) the deep learning accelerator comprising the at least one processing unit, and a control unit configured to load the instructions from the random access memory for execution (Fig. 6; Paragraph 0043, “A machine learning accelerator 640 is also communicatively coupled to processor cores 910, along with a signal processor 645. Machine learning accelerator 940 is circuitry dedicated to performing machine learning tasks associated with feature extraction, as discussed above, including, for example, the convolution and pooling layers of a convolutional neural network. Through the system interconnect, any of the processor cores can provide instructions to the machine learning accelerator. Similarly, the signal processor can communicate with the processor cores, the machine learning accelerator, and the I/O devices and is configured to process image/radar/LiDAR signals from the sensors depending upon the application.”; Paragraph 0042, “Further coupled to the system interconnect are input/output devices 620, including sensor devices 622 (e.g., a camera, radar, or LiDAR sensor), along with other associated controllers.”).
Regarding claim 9, the combination of Wu and Tremblay [Note: what Wu fails to disclose is strike-through]
The apparatus of claim 8,
Tremblay discloses,
wherein the matrix-matrix unit includes a plurality of matrix-vector units (see paragraph citations 0349 and 0501 below);
wherein each of the plurality of matrix-vector units includes a plurality of vector-vector units configured to operate in parallel (Paragraph 0349, “In at least one embodiment, one or more parallel processor(s) 4112 form a computationally focused parallel or vector processing system that can include a large number of processing cores and/or processing clusters, such as a many integrated core (MIC) processor.”); and
wherein each of the plurality of vector-vector units includes a plurality of multiply-accumulate units configured to operate in parallel (Paragraph 0501, “Tensor cores are configured to perform matrix operations in accordance with at least one embodiment. In at least one embodiment, one or more tensor cores are included in processing cores 5710. In at least one embodiment, tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inferencing. In at least one embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiply and accumulate operation D=A×B+C, where A, B, C, and D are 4×4 matrices.”).
It would have been obvious to someone in the art prior to the effective filing date of the claimed invention to modify Wu with Tremblay to incorporate the features of mentioned above. Both Wu and Tremblay are considered analogous arts as they both disclose systems and methods utilizing radar technology to recognize and identify objects by the use of machine learning accelerators. However, Wu fails to specifically disclose the feature of where the data obtained from these sensors is stored into a memory concurrently. Tremblay discloses such a feature in its computing apparatus in 42A where the parallel processing memory stores transferred data concurrently into memory. Furthermore, Tremblay discloses that all the elements in Fig. 42A can be located on a single integrated circuit in paragraph 0352, “In at least embodiment, components of computing system 4100 may be integrated with one or more other system elements on a single integrated circuit.”. The combination of Wu and Tremblay would be obvious with a reasonable expectation of success in order to provide a fast and efficient transfer, storage and processing of the data for the deep machine learning system (see paragraphs 0187 and 0194 of Tremblay).
Regarding claim 10, the same cited section and rationale as claim 1 is applied.
Regarding claim 11, Wu further discloses
The method of claim 10, wherein the description includes an identifier of a feature, a classification of the feature, a portion extracted from the radar image showing the feature, an orientation of an object represented by the feature, a position of the object, or a speed of the object, or any combination therein (Paragraph 0049, “As discussed above, the extracted feature map may be transmitted to a central compute server or additional computation on the extracted feature map may be performed at, for example, a gateway node to the network. In some embodiments, multiple network nodes between the edge sensor and the central compute server can perform computation on extracted feature map prior to sending the information to the central compute server. The stored filters in the convolutional layer are trained offline to reuse the same features for multiple applications using transfer learning.”).
Regarding claim 12, Wu further discloses
The method of claim 11, further comprising: capturing, by an image sensor configured in the radar portion, an optical image of a scene corresponding to the radar image (Paragraph 0037, “FIG. 5A illustrates a sensor fusion system architecture having multi-modal sensors (R=radar, C=camera, L=LiDAR) each having a same field of view.”, where the camera is configured “in the radar portion”); and writing, by the image sensor, data representative of the optical image into random access memory of the radar portion as part of the input to the artificial neural network (Paragraph 0024, “As illustrated in FIG. 1, the various sensors are placed around the vehicle and provide network connections to several gateway nodes. The gateway nodes can be smart switches that gather the data from the various sensors [i.e. camera, radar, etc.] and provide that information to a central processor 110.”, where “gathering data” implies the writing of the data into memory and is done through different gateway nodes (i.e. separate connections); Paragraph 0045, “Applications processor 600 further includes a system memory 670, which is interconnected to the foregoing by system interconnect 615 via a memory controller 660. System memory 970 further comprises an operating system 672 and in various embodiments also comprises feature extraction system 675. Feature extraction system 675 performs the tasks described above with regard to preprocessing and generating a feature map from data provided by sensor 622 associated with the applications processor.”).
Regarding claim 13, the same cited section and rationale as claim 7 is applied.
Regarding claim 15, the same cited section and rational as claim 1 is applied where the combination of Wu and Tremblay discloses the claims invention. Wu further discloses,
wherein the device is configured within a single integrated circuit package (Paragraph 0063, “Also for example, in one embodiment, the illustrated elements of system 600 are circuitry located on a single integrated circuit or within a same device.”).
Regarding claim 17, Wu further discloses
The device of claim 15, further comprising: an image sensor image (Fig. 6, sensor devices 622; Paragraph 0042, “Further coupled to the system interconnect are input/output devices 620, including sensor devices 622 (e.g., a camera, radar, or LiDAR sensor), along with other associated controllers.”) connected in the single integrated circuit package (Paragraph 0063, “Also for example, in one embodiment, the illustrated elements of system 600 are circuitry located on a single integrated circuit or within a same device.”, where the sensors devices 622 are part of this single integrated circuit) and configured to generate data representative of an optical image of a scene corresponding to the radar image (Paragraph 0037, “FIG. 5A illustrates a sensor fusion system architecture having multi-modal sensors (R=radar, C=camera, L=LiDAR) each having a same field of view.”) and to write the data representative of the optical image into the random access memory as part of the input to the artificial neural network (Paragraph 0046, “FIG. 6 is an example of an edge sensor applications processor. Other examples can provide the circuitry to perform the feature extraction in a separate SoC or ASIC from the sensor applications processor. In either case, feature extraction filters are precomputed and stored in memory accessible to the feature extraction circuitry (e.g., memory 670 or a memory directly coupled to the feature extraction circuitry).
Regarding claim 18, Wu further discloses
The device of claim 17, wherein the artificial neural network is configured to identify a classification of an feature, a portion extracted from the radar image showing the feature, or an orientation of an item represented by the feature, or any combination therein (Paragraph 0033, “The feature combiner determines how and which features should be combined based on various characteristics such as field of view overlap, spatial correlation, sensor modality, and the like.”, therefore the “features” have a description which indicates characteristics such as field of view).
Regarding claim 19, Wu further discloses
The device of claim 17, further comprising: a first connection between the random access memory and the image sensor (Fig. 6, a “first connection” between memory 670 and sensor 622); and a second connection between the random access memory and the circuit configured to generate the data representative of the radar image (Fig. 6, “second connection” between memory 670 and signal processor 645).
Regarding claim 20, Wu further discloses
The device of claim 19, further comprising: a third connection between the random access memory and the field-programmable gate array (FPGA) or application specific integrated circuit (ASIC) (FIG. 6 depicts a third connection between memory 670 and machine learning accelerator 640 (i.e. ASIC)).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 20210406674 A1) in view of Tremblay (US 20210125036 A1) further in view of LIU et al. (US 20200026720 A1), hereinafter LIU.
Regarding claim 14, the combination of Wu and Tremblay discloses [Note: what the combination of Wu and Tremblay fails to disclose is strike-though],
The method of claim 13,
LIU discloses,
further comprising: storing the input in the radar portion for a predetermined period of time after the transmitting of the data representative of the description to the host system; receiving, within the predetermined period of time, a request from the host system; transmitting the input to the host system; and erasing the input from the radar portion after the predetermined period of time (Paragraph 0090, “On the other hand, sensor data can be analyzed as soon as it becomes available, as soon as it reaches a predetermined size, or according to a predetermined schedule [i.e. predetermined time]. As one example, with a limited storage capacity, a UAV may need to frequently analyze the sensor data, send the resulting elevation data to the central server, and delete the analyzed sensor data [i.e. erase after predetermined time]. As another example, in response to a request from the central server for elevation data before a certain deadline, the UAV would want to complete analyzing available sensor data as soon as possible.” [i.e. after receiving request from the host system]).
It would have been obvious to someone in the art prior to the effective filing date of the claimed invention to modify Wu with Tremblay and further with LIU to incorporate the features mentioned above. All three references are considered analogous arts as they all disclose systems and methods utilizing radar technology to recognize and identify objects. However, the combination of Wu and Tremblay fails to specifically disclose the features mentioned above. The combination of Wu and Tremblay and LIU would be obvious with a reasonable expectation of success in order to provide a deep machine learning accelerator within a sensor fusion system to efficiently store, retrieve and erase data. The incorporation of the limitations in claim 14 would lead to a more efficient system which utilizes sensor data and deletes sensor data once it has been used to limit system memory use (see paragraphs 0060 and 0096 of LIU).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NAZRA N. WAHEED whose telephone number is (571)272-6713. The examiner can normally be reached M-F (8 AM - 4:30 PM).
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/NAZRA NUR WAHEED/Examiner, Art Unit 3648
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