DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kitamura (US 2019/0334534).
Claim 1: Kitamura discloses A radar sensor, comprising:
at least one transmitting antenna configured to radiate a transmitted radio frequency (RF) signal (fig 1 element 3);
at least one receiving antenna configured to receive a reflected RF signal from a target (fig 1 element 4); and
a frontend circuit configured to calculate a distance between the target and the radar sensor by measuring a characteristic shift between the transmitted RF signal and the reflected RF signal (fig 1 elements 2, 5, 6, para 0041, 0042), and comprising:
a crystal-less signal synthesizer configured to generate the transmitted RF signal without using a crystal (fig 1 elements 6, 7, “PLL Circuit”, para 0044-0050); and
a mixer configured to provide an intermediate frequency (IF)-band signal associated with the characteristic shift between the transmitted RF signal and the reflected RF signal by mixing the reflected RF signal and the transmitted RF signal (fig 1 element 18, para 0040-0042)
Claim 2: Kitamura discloses the mixer is coupled to the at least one receiving antenna for receiving the reflected RF signal and coupled to the crystal-less signal synthesizer for receiving the transmitted RF signal (para 0040-0042)
Claim 3: Kitamura discloses a first amplifier coupled between the crystal-less signal synthesizer and the at least one transmitting antenna for amplifying the transmitted RF signal (fig 1 element 15, para 0037); and a second amplifier coupled between the at least one receiving antenna and the mixer for amplifying the reflected RF signal (fig 1 element 16, para 0040, 0041)
Claim 6: Kitamura discloses the crystal-less signal synthesizer is implemented as a phase locked loop (PLL) (fig 2, para 0044-0050) which includes:
a reference clock configured to generate a reference signal of a specific frequency without using any crystal (fig 2 “reference clock”); a phase frequency detector configured to compare a phase of the reference signal with a phase of a feedback signal which is associated with the transmitted RF signal, thereby producing an error signal proportional to a phase difference between the reference signal and the feedback signal (fig 2 element 26); a loop filter configured to remove a predetermined frequency component of the error signal (fig 2 element 27); a voltage-controlled oscillator (VCO) configured to generate the transmitted RF signal according to the error signal (fig 2 element 23); and a clock divider configured to generate the feedback signal according to the transmitted RF signal (fig 2 element 24, 25)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 4, 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kitamura (US 2019/0334534) as applied to claim 1 above, and further in view of Choi (US 2026/0258790)
Claim 4: Kitamura discloses an analog-to-digital converter configured to convert the filtered IF-band signal into a digital signal (fig 1 element 20); and a digital signal processor configured to construct a feature map associated with the characteristic shift between the transmitted RF signal and the reflected RF signal based on the digital signal for calculating the distance between the target and the radar sensor (fig 1 element 5, para 0040, 0041).
Kitamura fails to specifically disclose a base-band signal processing chain configured to suppress an undesired sideband or an undesired frequency in the IF-band signal, thereby providing a filtered IF-band signal.
In the same field of endeavor, Choi discloses a vehicular radar sensor for detecting the position of obstacles by mixing a received signal with the transmitted signal to generate a difference frequency from which range and velocity may be determined (fig 4, para 0006), further comprising a base-band signal processing chain configured to suppress an undesired sideband or an undesired frequency in the IF-band signal, thereby providing a filtered IF-band signal (para 0080, 0081).
It would have been obvious to modify the invention such that it comprised the above limitations, as taught by Choi, in order to remove unwanted noise from the received signals (Choi para 0080, 0081)
Claim 5: Kitamura discloses the characteristic shift includes a frequency shift, a phase shift and/or a magnitude shift between the transmitted RF signal and the reflected RF signal (para 0040-0042)
Choi also discloses the characteristic shift includes a frequency shift, a phase shift and/or a magnitude shift between the transmitted RF signal and the reflected RF signal (para 0082)
Claim(s) 9-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kitamura (US 2019/0334534) as applied to claim 6 above, and further in view of Mangravati (Mangraviti, Giovanni et al. “Injection Locking Techniques for CMOS-Based mm-Wave Frequency Synthesis.”, (2015), 194 pages).
Claim 9: Kitamura does not specifically disclose the structure of the reference clock (fig 1 element 6, “Reference Clock”)
In a similar field of endeavor, Mangravati provides a detailed overview of injection locking techniques for mmWave frequency signal synthesis including the reference clock is implemented with a ring oscillator which comprises a first through an Mth amplifiers coupled in series, an output signal of the Mth amplifier is fed back to an input of the first amplifier, and M is an integer larger than 1 (pages 31, 32, 34, fig 3.4 showing a three stage ring oscillator and corresponding circuit diagram for respective stages, fig 3.6 showing a four stage ring oscillator and corresponding circuit diagram for respective stages)
It would have been obvious to modify the invention of Kitamura such that it comprised the above limitations, as taught by Mangravati, in order to provide a stable input reference clock to a PLL for frequency synthesis (Mangravati pages 31, 32)
Claim 10: Mangravati discloses each amplifier in the reference clock comprises: a positive input end and a negative input end; a positive output end and a negative output end; a first resistor including: a first end coupled to a first bias voltage; and a second end coupled to the positive output end; a second resistor including: a first end coupled to the first bias voltage; and a second end coupled to the negative output end; a first transistor including: a first end coupled to the second end of the first resistor; a second end; and a control end coupled to the positive input end; a second transistor including: a first end coupled to the second end of the second resistor; a second end coupled to the second end of the first transistor; and a control end coupled to the negative input end; and a variable current source including: a first end coupled to the second end of the first transistor and the second end of the second transistor; and a second end coupled to a second bias voltage (pages 31, 32, 34, fig 3.4 showing a three stage ring oscillator and corresponding circuit diagram for respective stages, fig 3.6 showing a four stage ring oscillator and corresponding circuit diagram for respective stages)
Claim 11: Mangravati discloses a positive output end and a negative output end of an mth amplifier among the first through the Mth amplifiers are respectively coupled to a negative input end and a positive input end of an (m+1)th amplifier among the first through the Mth amplifiers when m is a positive integer smaller than M; a positive output end and a negative output end of the Mth amplifier are respectively coupled to a positive input end and a negative input end of the first amplifier; and M is an even integer (pages 31, 32, 34, fig 3.4 showing a three stage ring oscillator and corresponding circuit diagram for respective stages, fig 3.6 showing a four stage ring oscillator and corresponding circuit diagram for respective stages)
Claim 12: Mangravati discloses a positive output end and a negative output end of an mth amplifier among the first through the Mth amplifiers are respectively coupled to a negative input end and a positive input end of an (m+1)th amplifier among the first through the Mth amplifiers when m is a positive integer smaller than M; the positive output end and the negative output end of the Mth amplifier are respectively coupled to a negative input end and a positive input end of the first amplifier; and M is an odd integer (pages 31, 32, 34, fig 3.4 showing a three stage ring oscillator and corresponding circuit diagram for respective stages, fig 3.6 showing a four stage ring oscillator and corresponding circuit diagram for respective stages)
Allowable Subject Matter
Claims 7, 8, 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 7 recites a specific structure for an LC oscillator reference clock. While LC oscillators, in general, are known in the art for providing reference clock signals, the specific structure as claimed is found to be novel.
Claim 8 depends from claim 7 and would be allowable for its dependence upon a claim indicated as comprising alloable subject matter.
Claim 13 recites a specific structure for an RC oscillator reference clock. While RC oscillators, in general, are known in the art for providing reference clock signals, the specific structure as claimed is found to be novel.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M BYTHROW whose telephone number is (571)270-1468. The examiner can normally be reached on Monday-Friday 830am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Resha Desai can be reached at (571) 270-7792. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER M BYTHROW/Primary Examiner, Art Unit 3648
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