DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 1, 2026 has been entered.
Response to Amendment
The amendment filed June 1, 2026 has been entered. Claims 1-6 remain pending in the application.
Response to Arguments
Applicant’s arguments, see Remarks on Page 5, filed June 1, 2026, with respect to the rejection(s) of claim(s) 1-6 under 35 USC 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Yu (KR 100238045 B1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4, and 6 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Yu (KR 100238045 B1) in view of Hones et al. (US 20210165244 A1), hereinafter Yu and Hones respectively.
Regarding claim 1, Yu teaches a method for generating a dot pattern applicable to a computer device (Paragraph 4 on Page 3, Paragraph 3-5 on Page 14 – “the halftone processing method according to the present invention may classify the grayscale group up and down around one of the grayscale values of the entire grayscale range, and then, A database generation step (S100) of generating a binary database composed of respective dot profiles generated by inverting the dots so as to include the number of white dots proportional to each gray value based on the binary reference pattern…The most prominent feature of the present invention is that it provides a software solution for real-time implementation of digital halftone processing. However, the present invention can reduce the software workload by implementing in hardware through a single chip, thereby increasing the processing speed. The monochromatic halftone processing method can be easily implemented through a small gate array including 31.75 Kilo-Bytes internal programmable read only memory (PROM)”; Note: the method generates dot profiles, which are dot patterns. Also, the method is implied to be applicable to a computer device since it is implemented on a hardware chip with software code and storage), the method for generating a dot pattern comprising:
generating a grayscale value weight based on a reference image (Paragraph 9 and 12 on Page 3 – “the database indexing step (S200) comprises a dot profile indexing step (S210) of indexing the corresponding dot profile with the grayscale value of the original image from the binary database…as shown in FIG. 8, data for generating a binary database composed of respective dot profiles including the number of white dots to be proportional to each grayscale value is shown”; Note: the grayscale value is equivalent to the grayscale value weight, and it is based on an original/reference image. It is implied to be generated since it could not be used in the method otherwise);
inputting a plurality of conversion parameters including a total number of the dots and a number of times of iterative operation (Paragraph 3 and 9 on Page 11 – “The final binary reference pattern is generated by iterating until the derivative value for the defined visual cost function is less than or equal to the predetermined value… If black dots already exist in the two-dimensional space, another random number is repeatedly generated until a given number of black dots is filled”; Note: there are parameters, including a number of iterations (represented by a value that needs to be reached until iterations stop) and a given number of dots. It would be obvious that they are inputted since they are given or predetermined values);
generating a plurality of initial random coordinates corresponding to the plurality of dots through a random operation based on the grayscale value weight and the total number of the dots (Paragraph 15 on Page 6, Paragraph 5-6 and 8 on Page 11 – “all dot profiles are independently generated from a random pattern composed of as many black dots as the gray level values…The binary seed pattern is generated by a random pattern generator and a pattern distributer. The random pattern generator creates an initial binary pattern…two random numbers are generated to indicate the two-dimensional position of the black dot, where the two random numbers represent horizontal and vertical coordinates in the binary reference pattern, respectively. These two random numbers are scaled to the maximum size of the binary pattern”; Note: initial random coordinates are generated for dots through a random pattern generator operation. The operation is based on gray level values/weight and number of black dots);
and performing dot distribution processing on the dots based on the number of times of iterative operation, the grayscale value weight, and the initial random coordinates to generate a plurality of iterative random coordinates from the plurality of initial random coordinates (Paragraph 3, 5-6, 8, and 13 on Page 11 – “in the CSF filtering step (S113), the random pattern is generated. After CSF filtering the binary reference pattern generated by the CSF filter, the operation of inverting the maximum value and the minimum value is respectively performed as a mean square error (MSE) between the gray value of the original image and the pixel value of the CSF filtered binary reference pattern. The final binary reference pattern is generated by iterating until the derivative value for the defined visual cost function is less than or equal to the predetermined value…The binary seed pattern is generated by a random pattern generator and a pattern distributer. The random pattern generator creates an initial binary pattern, and the pattern distributor distributes the initial binary pattern so that the pattern is optimally distributed in terms of human vision… two random numbers are generated to indicate the two-dimensional position of the black dot, where the two random numbers represent horizontal and vertical coordinates in the binary reference pattern… In the binary pattern determined from the random pattern generator, black pixels may be clustered or spaced at some positions. Such unwanted clustered pixels should be visually appropriately distributed using the daily CSF”; Note: the pattern distributor performs dot distribution using CSF filtering, which is iterative and leads to iterative random coordinates, by iterating over the initial random coordinates. The distribution is also based on grayscale values/weight and a number of iterations (iterates until a certain value is reached)),
and generating a dot pattern representing the reference image (Paragraph 3 on Page 11, Paragraph 8 and 13 on Page 12 – “in the CSF filtering step (S113), the random pattern is generated. After CSF filtering the binary reference pattern generated by the CSF filter, the operation of inverting the maximum value and the minimum value is respectively performed as a mean square error (MSE) between the gray value of the original image and the pixel value of the CSF filtered binary reference pattern. The final binary reference pattern is generated by iterating until the derivative value for the defined visual cost function is less than or equal to the predetermined value… After the binary reference pattern generation step (S110) is completed, the binary reference pattern is set as the reference dot profile”; Note: the final binary reference pattern or dot profile is equivalent to the generated dot pattern. It represents the reference/original image since it is generated based on the gray value of the original image) through the iterative random coordinates (Paragraph, 5-6, and 8 on Page 11 – “in the CSF filtering step (S113), the random pattern is generated. After CSF filtering the binary reference pattern generated by the CSF filter, the operation of inverting the maximum value and the minimum value is respectively performed as a mean square error (MSE) between the gray value of the original image and the pixel value of the CSF filtered binary reference pattern. The final binary reference pattern is generated by iterating until the derivative value for the defined visual cost function is less than or equal to the predetermined value…The binary seed pattern is generated by a random pattern generator and a pattern distributer. The random pattern generator creates an initial binary pattern…two random numbers are generated to indicate the two-dimensional position of the black dot, where the two random numbers represent horizontal and vertical coordinates in the binary reference pattern, respectively. These two random numbers are scaled to the maximum size of the binary pattern”; Note: the dot pattern is generated by first generating initial random coordinates and then iterating over them to get iterative random coordinates that are processed to obtain the final dot pattern), wherein the dot pattern comprises the dots (Paragraph 8 and 13 on Page 12 – “After the binary reference pattern generation step (S110) is completed, the binary reference pattern is set as the reference dot profile… All dot profiles are correlated and each profile distributes black dots and white dots appropriately so that they are visually optimized”; Note: the generated dot profile is a dot pattern comprising dots).
Yu does not teach a “size range of the dots” in the limitations: “inputting a plurality of conversion parameters including a size range of dots, a total number of the dots, and a number of times of iterative operation; generating a plurality of initial random coordinates corresponding to the plurality of dots through a random operation based on the grayscale value weight, the size range of the dots, and the total number of the dots”. However, Hones teaches a size range of the dots (Paragraph 0084-0085 – “Design parameters of the dot pattern can be varied in order to increase or decrease certain spatial frequencies as desired…For example, the dots can have a dimension (as measured in the x-y plane) in a range from about 0.001 mm or more…to about 1 mm or less”; Note: there is a parameter including a size range of the dots). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yu to incorporate the teachings of Hones to have a size range of the dots because “dot patterns can be designed based on optimization of a modulation transfer function, which refers to the spatial frequency response of the human visual system. For instance, the size, shape, and spacing of the scattering centers can be varied to smoothen attenuation of a range of spatial frequencies… The aforementioned metrics can be used to evaluate dot patterns based on the size and/or shape of the dots, both of which can be varied as desired” (Hones: Paragraph 0084-0085). In other words, varying the size of the dots is beneficial for spatial frequency. Additionally, it can help depict details better, and knowing the size range can help with preventing overlapping dots during dot generation.
Regarding claim 3, Yu in view of Hones teaches the method for generating a dot pattern according to claim 1. Yu does not teach wherein the size range of the dots is 0.001-1 mm. However, Hones teaches wherein the size range of the dots is 0.001-1 mm (Paragraph 0085 – “For example, the dots can have a dimension (as measured in the x-y plane) in a range from about 0.001 mm or more…to about 1 mm or less”). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yu to incorporate the teachings of Hones to have the size range of the dots be between 0.001-1mm because “dot patterns can be designed based on optimization of a modulation transfer function, which refers to the spatial frequency response of the human visual system. For instance, the size, shape, and spacing of the scattering centers can be varied to smoothen attenuation of a range of spatial frequencies… The aforementioned metrics can be used to evaluate dot patterns based on the size and/or shape of the dots, both of which can be varied as desired” (Hones: Paragraph 0084-0085). In other words, varying the size of the dots is beneficial for spatial frequency.
Regarding claim 4, Yu in view of Hones teaches the method for generating a dot pattern according to claim 1. Yu does not teach wherein the total number of the dots ranges from 10 to 10,000. However, Hones teaches wherein the total number of the dots ranges from 10 to 10,000 (Paragraph 0065 – “FIG. 6B shows an exemplary lens having a graded dot pattern with varying dot size”; Note: the figure shows a dot pattern with a total number of dots that is within a range between 10 and 10,000; see screenshot of Fig. 6B below).
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Screenshot of Fig. 6B (taken from Hones)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yu to incorporate the teachings of Hones to have the number of dots range from 10 to 10,000 because having too little dots would not produce a clear representation of the original image, and having too many dots would be inefficient, slow, or redundant to generate. Therefore, limiting the number of dots to a minimum and maximum would help to create an optimal dot pattern.
Regarding claim 6, Yu in view of Hones teaches the method for generating a dot pattern according to any one of claims 1 and 3-4. Yu further teaches a computer-readable medium storing a program code which is executed by a processing unit, wherein the program code comprises the method for generating a dot pattern (Paragraph 3-5, 12, and 15-18 on Page 14 – “The most prominent feature of the present invention is that it provides a software solution for real-time implementation of digital halftone processing. However, the present invention can reduce the software workload by implementing in hardware through a single chip, thereby increasing the processing speed. The monochromatic halftone processing method can be easily implemented through a small gate array including 31.75 Kilo-Bytes internal programmable read only memory (PROM)… 7 illustrates a hardware block diagram of an embodiment of a halftone processing method according to the present invention…The addressing circuit 20a constituted by the counter selects the lower address of the PROM 10a as the position of the pixel. The lower address represents the byte position of the bit to be processed and is incremented sequentially. The multiplexing circuit 20b performs a data latch and multiplexing function to select one bit from one byte output of the PROM 10a. The eight-input OR / AND logic 20c detects an input zero gradation value or a 255 gradation value and outputs a strobe signal to the multiplexing circuit 20b. The clock control circuit 20d generates clock signals CLOCK_in and CLOCK_out for synchronizing the input / output synchronization”; Note: the PROM is equivalent to the computer-readable storage medium storing the code for the method. The method is executed by the circuits, which is equivalent to the processing unit).
Claim 2 and 6 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Yu in view of Hones and Isaka (DE 4042644 C2), hereinafter Isaka.
Regarding claim 2, Yu in view of Hones teaches the method for generating a dot pattern according to claim 1. Yu does not teach storing the dot pattern in a vector image format. However, Isaka teaches storing the dot pattern in a vector image format (Paragraph 0023 – “Fig. 5 shows an example in which the letter "A" stored in the form shown in Fig. 3 is converted into the printable dot image, which is stored in the read/write memory 11 by the microprocessor 13. On the other hand, the microprocessor 13 can arbitrarily select the size of the image pattern, which has been converted into the dot pattern shown in Fig. 5.…On the other hand, it is also possible to convert the vector data into the point data and also to save data in advance for a size-appropriate correction of the line width”; Note: the dot pattern image is stored as vector data). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yu to incorporate the teachings of Isaka to store the dot pattern in a vector image format because vector image formats generally have better scalability and are easier to edit than raster files.
Regarding claim 6, Yu in view of Hones and Isaka teaches the method for generating a dot pattern according to claim 2. Yu further teaches a computer-readable medium storing a program code which is executed by a processing unit, wherein the program code comprises the method for generating a dot pattern (Paragraph 3-5, 12, and 15-18 on Page 14 – “The most prominent feature of the present invention is that it provides a software solution for real-time implementation of digital halftone processing. However, the present invention can reduce the software workload by implementing in hardware through a single chip, thereby increasing the processing speed. The monochromatic halftone processing method can be easily implemented through a small gate array including 31.75 Kilo-Bytes internal programmable read only memory (PROM)… 7 illustrates a hardware block diagram of an embodiment of a halftone processing method according to the present invention…The addressing circuit 20a constituted by the counter selects the lower address of the PROM 10a as the position of the pixel. The lower address represents the byte position of the bit to be processed and is incremented sequentially. The multiplexing circuit 20b performs a data latch and multiplexing function to select one bit from one byte output of the PROM 10a. The eight-input OR / AND logic 20c detects an input zero gradation value or a 255 gradation value and outputs a strobe signal to the multiplexing circuit 20b. The clock control circuit 20d generates clock signals CLOCK_in and CLOCK_out for synchronizing the input / output synchronization”; Note: the PROM is equivalent to the computer-readable storage medium storing the code for the method. The method is executed by the circuits, which is equivalent to the processing unit).
Claim 5 and 6 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Yu in view of Hones and Jeon et al. (KR 20170142784 A), hereinafter Jeon.
Regarding claim 5, Yu in view of Hones teaches the method for generating a dot pattern according to claim 1. Yu does not teach wherein the number of times of iterative operation ranges from 0 to 1,000. However, Jeon teaches wherein the number of times of iterative operation ranges from 0 to 1,000 (Paragraph 0022, 0024, 0028 – “As a result of the judgment in step 3 (S30), if the point overlaps the boundary of the processing area, the process returns to step 2 (S20), the center coordinates of the point are randomly regenerated, and step 3 (S30) is repeated…Step 6 (S60) is a step for comparing the number of points with confirmed center coordinates with the number of point patterns set in Step 1 (S10). If the number of points with confirmed center coordinates is less than the number of point patterns set in Step 1 (S10), the process returns to Step 2 (S20). In the second step (S20), the center coordinates of the second point are randomly generated…Steps 2 to 6 (S20, S30, S40, S50, S60) are repeated from the third point to the nth point, and the center coordinates of all points from the first point to the nth point are determined. Here, n represents the number of point patterns set in the first step (S10)”; Note: the process of properly distributing the dots within the processing area occurs iteratively, and it occurs between 3 to n times. This range has an overlapping portion with the range 0 to 1000, and it would been prima facie obvious to have selected the overlapping portion of the range). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yu to incorporate the teachings of Jeon to perform the iterative operation between the overlapping portion of the ranges because depending on user preferences and the desired output, performing a certain number of operations would help produce the target output dot pattern. Meanwhile, performing an excess of operations would be too time-consuming or redundant, making it important to have a bound on the number of operations. But barely or not performing the operation at all would contradict Jeon’s goal of being able to control the randomness. Therefore, it would have been obvious to have selected the overlapping portion of the ranges, between 3 and 1000.
Regarding claim 6, Yu in view of Hones and Jeon teaches the method for generating a dot pattern according to claim 5. Yu further teaches a computer-readable medium storing a program code which is executed by a processing unit, wherein the program code comprises the method for generating a dot pattern (Paragraph 3-5, 12, and 15-18 on Page 14 – “The most prominent feature of the present invention is that it provides a software solution for real-time implementation of digital halftone processing. However, the present invention can reduce the software workload by implementing in hardware through a single chip, thereby increasing the processing speed. The monochromatic halftone processing method can be easily implemented through a small gate array including 31.75 Kilo-Bytes internal programmable read only memory (PROM)… 7 illustrates a hardware block diagram of an embodiment of a halftone processing method according to the present invention…The addressing circuit 20a constituted by the counter selects the lower address of the PROM 10a as the position of the pixel. The lower address represents the byte position of the bit to be processed and is incremented sequentially. The multiplexing circuit 20b performs a data latch and multiplexing function to select one bit from one byte output of the PROM 10a. The eight-input OR / AND logic 20c detects an input zero gradation value or a 255 gradation value and outputs a strobe signal to the multiplexing circuit 20b. The clock control circuit 20d generates clock signals CLOCK_in and CLOCK_out for synchronizing the input / output synchronization”; Note: the PROM is equivalent to the computer-readable storage medium storing the code for the method. The method is executed by the circuits, which is equivalent to the processing unit).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Sugizaki (US 6975431 B1) teaches a method of generating image data of dot patterns containing halftone dots based on image pixel data. Samworth (US 6445465 B1) teaches a method of generating a halftone screen of dots with varying sizes and shades of gray.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHELLE HAU MA whose telephone number is (571)272-2187. The examiner can normally be reached M-Th 7-5:30.
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/MICHELLE HAU MA/Examiner, Art Unit 2617 /KING Y POON/Supervisory Patent Examiner, Art Unit 2617
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