DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 11 & 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Martin (US 2008/0316663).
With regard to claims 1-5, 11 & 13, Martin, in Figure 5, discloses a linear power converter circuit (paragraph 0004) with a surge protection circuit (Abstract teaches that the device protects against ESD which is a surge voltage), comprising: an output transistor (120), a gate of which is controlled by an error amplification signal (via 110, paragraph 0004), wherein the output transistor is configured to operably convert an input voltage and generate an output voltage (paragraph 0004); an error amplification circuit (110), which is configured to operably amplify a difference between a reference voltage (111) and a feedback voltage (112) to generate the error amplification signal, thereby regulating the output voltage to a predetermined level, wherein the feedback voltage is related to the output voltage; and a first surge protection circuit (M, R & C), which is configured to operably clamp a gate-source voltage of the output transistor when a conversion rate of the input voltage exceeds a threshold (RC time constant set of resistor R and capacitor C), to limit a current of the output transistor not to exceed a predetermined upper limit (paragraph 0010 teaches that without the surge protection the current through the transistor can destroy it and further teaches that when the surge protection operates that the current through the transistor drops to near zero such that the upper limit is the current which would destroy the transistor) (re claim 1), wherein the first surge protection circuit includes: a first clamping transistor (M); and a first filter (R & C), which is configured to operably filter the input voltage to generate a first clamping control signal (RC operates as a low pass filter), for controlling the first clamping transistor, thereby, when the conversion rate of the input voltage exceeds the threshold, turning ON the first clamping transistor, and thereby clamping the gate-source voltage of the output transistor to limit the current of the output transistor not to exceed the predetermined upper limit (paragraph 0026-0028) (re claim 2), wherein the output transistor and the first clamping transistor are both P-type transistors (as seen in Fig. 5) (re claim 3), wherein the first filter is a low-pass filter (as seen in Fig. 5) (re claim 4), wherein the low-pass filter comprises a first filtering resistor (R) and a first filtering capacitor (C), wherein the first filtering resistor and the first filtering capacitor are serially connected and coupled between the input voltage and a ground potential (through 110 & R2), and the first filtering resistor and the first filtering capacitor are coupled to the first clamping transistor (M) (re claim 5), wherein the gate of the output transistor has a first equivalent capacitor, and there is a first equivalent resistor between the gate of the output transistor and the input voltage (the transistor 120 would necessarily comprise of these parasitic capacitors and resistors), wherein a bandwidth of the low-pass filter is lower than a bandwidth corresponding to a product of the resistance of the first equivalent resistor and the capacitance of the first equivalent capacitor to a degree, such that when the conversion rate of the input voltage exceeds the threshold, the first clamping transistor is turned ON by the first clamping control signal, thereby clamping the gate-source voltage of the output transistor to limit the current of the output transistor not to exceed the predetermined upper limit (paragraphs 0026-0028) (re claim 11), wherein a bandwidth of the low-pass filter is lower than an input bandwidth to a degree, such that when the conversion rate of the input voltage exceeds the threshold, the first clamping transistor is turned ON by the first clamping control signal, thereby clamping the gate-source voltage of the output transistor to limit the current of the output transistor not to exceed the predetermined upper limit, wherein the input bandwidth corresponds to a bandwidth associated with a product of an inverse of the conversion rate of the input voltage and the input voltage (paragraphs 0026-0028) (re claim 13).
Allowable Subject Matter
Claims 6-10, 12, 14 & 15 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 6 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record does not teach or fairly suggest a linear power converter comprising all the features as recited in the claims and in combination with the error amplification circuit including an amplifier and an amplifying transistor; wherein the linear power converter circuit further comprises a second surge protection circuit for clamping the gate-source voltage of the amplifying transistor when the conversion rate of the input voltage exceeds the threshold, to limit the current of the amplifying transistor not to exceed a predetermined upper limit.
Claims 7-10, 12, 14 & 15 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because they depend on claim 6 which would also be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Bansal (US 6,952,091, Inoue (US 2009/0273331), Kurozo (US 2016/0211751), Wei (US 2016/0363945) and Asano (US 2023/0032031) all teach linear converters with protection coupled to the output of the error amplifier and the gate of a regulator transistor.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT BAUER whose telephone number is (571)272-5986. The examiner can normally be reached M-F 12pm - 8pm EST.
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/Scott Bauer/Primary Examiner, Art Unit 2838