Prosecution Insights
Last updated: April 19, 2026
Application No. 18/630,020

TEMPERATURE-SENSITIVE SAMPLING

Non-Final OA §102§103§112
Filed
Apr 09, 2024
Examiner
YOUSSEF, MENATOALLAH M
Art Unit
2849
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
2 (Non-Final)
76%
Grant Probability
Favorable
2-3
OA Rounds
2y 7m
To Grant
96%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allow Rate
155 granted / 203 resolved
+8.4% vs TC avg
Strong +20% interview lift
Without
With
+19.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
13 currently pending
Career history
216
Total Applications
across all art units

Statute-Specific Performance

§101
12.2%
-27.8% vs TC avg
§103
40.6%
+0.6% vs TC avg
§102
19.4%
-20.6% vs TC avg
§112
22.2%
-17.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 203 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 14-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 14 recites the limitation "the elevated temperature detector" in line 7. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this limitation, this limitation will be interpreted as is consistent with “a temperature detector”, as recited in Claim 14, line 6. Claims 15 and 16 are rejected for depending from Claim 14. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 2, and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Van Brocklin et al. (US 10,124,582 B2). Regarding Claim 1, Van Brocklin et al. teaches in Figures 1 and 3 an apparatus, comprising: a logic circuit having an output and first and second inputs (34, 36); a pulse generator having an output coupled to the first input of the logic circuit (18, which outputs to input of 34); a detector circuit including: a temperature sensor having an output (14); and a comparator (16) having a first input coupled to the output of the temperature sensor (from 14), a reference input (as connected to 12), and an output coupled to the second input of the logic circuit (as connected to 34); and a switch having a control terminal coupled to the output of the logic circuit (38). Regarding Claim 2, Van Brocklin et al. further teaches the apparatus, further comprising circuitry having an output coupled to a terminal of the switch (35, through 36). Regarding Claim 18, Van Brocklin et al. further teaches the apparatus, further comprising a voltage regulator having an input coupled to a first terminal of the switch as connected through 33) and a voltage reference coupled to a second terminal of the switch (as connected to ground). Claim(s) 8, 9, 14, and 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Terasawa (US 8,680,933 B2). Regarding Claim 8, Terasawa teaches in Figure 1 an apparatus comprising: a sample and hold circuit (28, as further detailed in Figure 3) including: a switch having first and second terminals and a control terminal, the first terminal coupled to an input signal terminal (30, as connected to input, output and SW2); and a hold element coupled to the second terminal of the switch (32); a control circuit coupled to the control terminal of the switch, the control circuit configurable to close the switch in a first mode, and alternate between opening and closing the switch in a second mode (36, which generates SW2 and further detailed in Figure 4). Regarding Claim 9, Terasawa further teaches the apparatus, wherein the control circuit includes a detector circuit, the detector circuit including: a temperature sensor capable of indicating the temperature in the apparatus (20); and a comparator having a first input coupled to the temperature sensor (86, which inputs based on 20), the comparator configurable to generate, at an output of the comparator circuit (V4), a signal indicating whether the temperature in the apparatus exceeds the temperature threshold (based on 38 and 54); and wherein the control circuit is configurable to provide the signal having a first state to close the switch in the first mode (based on SW2 generated). Regarding Claim 14, Terasawa teaches in Figure 1 an apparatus comprising: a reference circuit having a reference output (22; Figure 3: input); a sample-and-hold circuit having a reference input coupled to the reference output (28, as connected to 22 and input), the sample-and-hold circuit (as further detailed in Figure 3) including a switch (30) and a hold element (32), the switch coupled between the hold element and the reference input (30 is connected between input node and 32); and an temperature detector including a temperature sensor capable of providing a temperature signal (20), the temperature detector capable of providing a mode selection signal to control an operational mode of the sample-and-hold circuit responsive to the temperature signal and a reference voltage (based on SW2, as generated by 36, and based on SW1 and 22); wherein the sample-and-hold circuit is capable of coupling the reference input to the hold element responsive to the mode selection signal having an asserted value (based on SW2). Regarding Claim 16, Terasawa further teaches the apparatus, wherein the sample-and-hold circuit is capable of, responsive to the mode selection signal having an asserted value, disabling a pulsed mode (based on SW2). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 3-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Van Brocklin et al. (US 10,124,582 B2) as applied to claim 1 above, and further in view of Horug et al. (US 2022/0364936 A1). Regarding Claim 3, Van Brocklin et al. teaches all the limitations of the present invention, but does not explicitly teach the details of the temperature sensor. Horug et al. teaches in Figure 1A the temperature sensor includes a proportional to absolute temperature (PTAT) current source (122, 132, 152, 162). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the temperature sensor detailed configuration with the temperature sensor of Van Brocklin et al. for the purpose of reducing temperature errors. Horug et al., [0002]. Regarding Claim 4, Van Brocklin et al. teaches all the limitations of the present invention, but does not explicitly teach the details of the temperature sensor. Horug et al. teaches in Figure 1A the temperature sensor includes a diode having a cathode coupled to a ground terminal (124, 134, 154, and 164 are diode-connected transistors, where the cathode are coupled to ground). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the temperature sensor detailed configuration with the temperature sensor of Van Brocklin et al. for the purpose of reducing temperature errors. Horug et al., [0002]. Regarding Claim 5, Van Brocklin et al. teaches all the limitations of the present invention, but does not explicitly teach the details of the temperature sensor. Horug et al. teaches in Figure 1A the temperature sensor includes a field-effect transistor (FET) having a gate coupled to a reference voltage terminal (124, 134, 154, and 164 have gates coupled to ground). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the temperature sensor detailed configuration with the temperature sensor of Van Brocklin et al. for the purpose of reducing temperature errors. Horug et al., [0002]. Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Terasawa (US 8680933 B2) as applied to claim 14 above, and further in view of Horug et al. (US 2022/0364936 A1). Regarding Claim 15, Terasawa teaches all the limitations of the present invention, but does not explicitly teach the details of the temperature sensor. Horug et al. teaches in Figure 1A the temperature sensor includes a field-effect transistor (FET) having a threshold voltage that exceeds the reference voltage (124, 134, 154, and 164). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the temperature sensor detailed configuration with the temperature sensor of Terasawa for the purpose of reducing temperature errors. Horug et al., [0002]. Allowable Subject Matter Claims 6, 7, 10-13 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 6, the prior art does not disclose, teach or suggest the apparatus, wherein the switch is a first switch, and the circuitry includes a voltage reference circuit coupled to the output of the circuitry, and the apparatus further comprising a second switch coupled between a terminal of the voltage reference circuit and a supply voltage terminal, and a control terminal coupled to the output of the logic circuit; in combination with all the other claimed limitations. Claim 7 is objected to for depending from Claim 6. Regarding Claim 10, the prior art does not disclose, teach or suggest the apparatus, wherein the signal is a first signal, and the control circuit further includes comprising: wherein the control circuit is configurable to provide the second signal to alternate between opening and closing the switch in the second mode, responsive to the first signal having a second state; in combination with all the other claimed limitations. Claims 11-13 are objected to for depending from Claim 10. Regarding Claim 17, the prior art does not disclose, teach or suggest the apparatus, further comprising a hold element coupled to the switch, in which the switch and the hold element are part of a sample-and-hold circuit; in combination with all the other claimed limitations. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Diana J Cheng whose telephone number is (571)270-1197. The examiner can normally be reached Monday - Friday 9 am - 5:30 pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at (571)270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DIANA J. CHENG/Primary Examiner, Art Unit 2849
Read full office action

Prosecution Timeline

Apr 09, 2024
Application Filed
Apr 14, 2025
Non-Final Rejection — §102, §103, §112
Jul 17, 2025
Response Filed
Jan 28, 2026
Request for Continued Examination
Feb 04, 2026
Response after Non-Final Action
Mar 17, 2026
Non-Final Rejection — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
76%
Grant Probability
96%
With Interview (+19.5%)
2y 7m
Median Time to Grant
Moderate
PTA Risk
Based on 203 resolved cases by this examiner. Grant probability derived from career allow rate.

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