Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 11-20 in the reply filed on 8/26/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The limitation “a plurality of second trenches” as recited in line 10 of claim 6, a plurality of the second trenches” as recited in lines 5, 8 and 12 of claim 10, and “the plurality of second trenches as recited in line 8 of claim 11 are unclear whether these limitations are related to the “second trench” in claim 1.
Allowable Subject Matter
Claims 1-5 are allowed.
Reason for indicating Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or suggest, singularly or in combination at least the limitation “a first gate electrode formed at an upper portion of the first trench inside the first trench and electrically isolated from the semiconductor substrate and the field plate electrode; a second trench formed in the semiconductor substrate so as to reach a predetermined depth from the upper surface of the semiconductor substrate; and a second gate electrode formed inside the second trench and electrically isolated from the semiconductor substrate, wherein a depth of the first trench is greater than a depth of the second trench; wherein the first trench extends in a first direction in plan view; wherein the second trench extends in a second direction intersecting the first direction in plan view; wherein the first trench and the second trench communicate with each other; and wherein the first gate electrode and the second gate electrode are integrated with each other” as recited in claim 1 is the major difference between the prior art and the claimed invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL A GEBREMARIAM whose telephone number is (571)272-1653. The examiner can normally be reached 8:30-4PM.
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/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
