DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to claims filed on 04/09/2024.
Claims 1-22 are pending.
Claim Objections
Claim 7 is objected to because of the following informalities: “and stores the identification code of each core in the system memory,” should read “and storing the identification code of each core in the system memory,”. Appropriate correction is required.
Claims 8-11 depend, directly or indirectly, from rejected claims and do not resolve the deficiencies thereof and are therefore rejected for at least the same reasons.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 2-6 and 13-17 are rejected under 35 U.S.C. 101 because the claimed invention recites a judicial exception, is directed to that judicial exception, an abstract idea, as it has not been integrated into practical application and the claims further do not recite significantly more than the judicial exception. Examiner has evaluated the claims under the framework provided in the 2019 Patent Eligibility Guidance published in the Federal Register 01/07/2019 and has provided such analysis below. Claims 2-6 depend on claim 1, thus the limitations of claim 1 will be analyzed as additional elements. Claims 13-17 depend on claim 12, thus the limitations of claim 12 will be analyzed as additional elements.
Step 1: Claims 2-6 are directed to a computer system and fall within the statutory category of machine. Claims 13-17 are directed to method and fall within the statutory category of process. Therefore, “Are the claims to a process, machine, manufacture or composition of matter?” Yes.
In order to evaluate the Step 2A inquiry “Is the claim directed to a law of nature, a natural phenomenon or an abstract idea?” we must determine, at Step 2A Prong 1, whether the claim recites a law of nature, a natural phenomenon or an abstract idea and further whether the claim recites additional elements that integrate the judicial exception into a practical application.
Step 2A Prong 1:
Claims 2, 4, 13, and 15: The limitations of “the first exception handler determines whether a first target instruction causing the undefined instruction exception is one of the special instructions;” and “the second exception handler determines whether a second target instruction causing the general-purpose exception is one of the special instructions;”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can observe a first target instruction and, based on these observations, can mentally determine if the first target instruction is one of the special instructions. Further, the limitations of “and in response to the first target instruction being one of the special instructions, the first exception handler calls an operating system scheduler to relate the application with the second-type core and schedule the second-type core to run the application” and “and in response to the second target instruction being one of the special instructions, the second exception handler calls an operating system scheduler to relate the application with the second-type core and schedule the second-type core to run the application”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can, in response to a determination that a first target instruction is one of the special instructions, mentally relate an application with a second-type core and can mentally generate a schedule of the second-type core to run the application. This may also be done with pen and paper.
Claims 3 and 14: The limitations of “and in response to the undefined instruction exception, the first exception handler searches the special instruction table for an opcode of the first target instruction and, if the opcode of the first target instruction is listed in the special instruction table, the first exception handler determines that the first target instruction is one of the special instructions”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can, in response to an undefined instruction exception, observe a special instruction table and a first target instruction and, based on these observations, can mentally search the special instruction table for an opcode of the first target instruction, and can mentally determine that the first target instruction is one of the special instructions if the opcode of the first target instruction is listed in the special instruction table by using mental comparison. This may also be done with pen and paper.
Claims 5 and 16: The limitations of “according to an exception code of the general-purpose exception, the second exception handler determines whether the second target instruction is one of the special instructions”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can observe an exception code of a general-purpose exception and, based on these observations, can mentally determine if a second target instruction is one of the special instructions.
Claims 6 and 17: The limitations of “according to an opcode of the second target instruction as well as an exception code of the general-purpose exception, the second exception handler determines whether the second target instruction is one of the special instructions”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can observe an opcode of a second target instruction and an exception code of a general-purpose exception and, based on these observations, can mentally determine if the second target instruction is one of the special instructions.
Therefore, Yes, claims 2-6 and 13-17 recite a judicial exception.
Step 2A Prong 2:
Claims 2-6 and 13-17 depend from one or more of claims 1 and 12. Thus, the limitations of claim 1 and 12 are present in the claims which depend therefrom and are considered as additional elements under Step 2A Prong 2 in consideration of whether the recited abstract ideas of the claims that depend therefrom are integrated into practical application.
Claims 1 and 12: The judicial exception is not integrated into a practical application. In particular, the claims recite the following additional elements – “A computer system, comprising: a hybrid architecture processor, including a first-type core and a second-type core;” and “A method for application compatible execution, comprising: providing a hybrid architecture processor that has a first-type core and a second-type core,” which are merely recitations of generic computing components (see MPEP § 2106.05(f)) which does not integrate a judicial exception into practical application. Further, the claims recite the following additional elements – “wherein the second-type core uses special instructions not supported by the first-type core, or supported by the first-type core in a semantically changed manner;” which are merely recitations of technological environment/field of use (see MPEP § 2106.05(h)) which does not integrate a judicial exception into practical application. Further, the claims recite the following additional elements – “and in response to the first-type core executing an application that has any of the special instructions, migrating the application to the second-type core for execution” which are merely recitations of data transmission which is insignificant extra solution activity (see MPEP §2106.05(g)) which does not integrate a judicial exception into practical application.
Claims 2, 4, 13, and 15: The judicial exception is not integrated into a practical application. In particular, the claims recite additional element recitations of “in response to an undefined instruction exception, the first-type core runs a first exception handler;” and “in response to a general-purpose exception, the first-type core runs a second exception handler;”, which are merely recitations of generic computing components and functions (see MPEP § 2106.05(f)) which does not integrate a judicial exception into practical application.
Claims 3 and 14: The judicial exception is not integrated into a practical application. In particular, the claims recite additional element recitations of “the first exception handler manages a special instruction table to list opcodes of the special instructions;”, which are merely recitations of technological environment/field of use (see MPEP § 2106.05(h)) which does not integrate a judicial exception into practical application.
Claims 5, 6, 16, and 17: The judicial exception is not integrated into a practical application. In particular, the claims do not recite further additional elements.
Therefore, “Do the claims recite additional elements that integrate the judicial exception into a practical application? No, these additional elements do not integrate the abstract idea into a practical application and they do not impose any meaningful limits on practicing the abstract idea. The claims are directed to an abstract idea.
After having evaluated the inquires set forth in Steps 2A Prong 1 and 2, it has been concluded that claims 2-6 and 13-17 not only recite a judicial exception but that the claims are directed to the judicial exception as the judicial exception has not been integrated into practical application.
Step 2B:
Claims 2-6 and 13-17 depend from one or more of claims 1 and 12. Thus, the limitations of claim 1 and 12 are present in the claims which depend therefrom and are considered as additional elements under Step 2B in consideration of whether the recited additional elements of the claims that depend therefrom amount to significantly more than any recited judicial exception.
Claims 1-6 and 12-17: The claims do not include additional elements, alone or in combination, that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract ideas into a practical application, the additional elements amount to no more than generic computing components, field of use/technological environment, and insignificant extra solution activity which do not amount to significantly more than the abstract idea. Further, the insignificant extra solution activity is well-understood, routine, and conventional in the art. “The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. i. Receiving or transmitting data over a network…iv. Storing and retrieving information in memory” [MPEP§ 2106.05(d)(II)].
Therefore, “Do the claims recite additional elements that amount to significantly more than the judicial exception? No, these additional elements, alone or in combination, do not amount to significantly more than the judicial exception.
Having concluded analysis within the provided framework, Claims 2-6 and 13-17 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Therefore, Claims 2-6 and 13-17 do not recite patent eligible subject matter under U.S.C. §101.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jahagirdar et al. US 2014/0026146 A1 (hereafter Jahagirdar).
With regard to claim 1, Jahagirdar teaches:
A computer system, comprising: a hybrid architecture processor, including a first-type core and a second-type core; “The technologies described herein generally relate to a processor with asymmetric multiple cores. The processor is asymmetric because one or more cores of the multiple cores of the processor have at least one characteristic that is different from the other cores of the processor” [Jahagirdar ¶ 12].
wherein: the second-type core uses special instructions not supported by the first-type core, or supported by the first-type core in a semantically changed manner; “For example, the one or more cores may differ from the other cores based on an operating frequency, a power usage, a thermal characteristic, an instruction set, another core characteristic, or any combination thereof … As another illustration, the one or more cores may be capable of executing at least one multimedia instruction (special instruction) that the other cores are incapable of executing” [Jahagirdar ¶ 12]. “To illustrate, a processor in a mobile device, such as a wireless phone or tablet computing device, may include at least a first core and a second core. Compared to the second core, the first core may run at a different (e.g., slower) operating frequency, have a different (e.g., smaller) instruction set, have a different (e.g., lower) throughput, have a different (e.g., lower) power usage, or any combination thereof” [Jahagirdar ¶ 14].
and in response to the first-type core executing an application that has any of the special instructions, the application is migrated to the second-type core for execution. “The processor may determine that the threads scheduled for execution by the first core include particular instructions that are not supported by the first core or that the second core would execute faster than the first core. In response to the determination, the processor may migrate the threads from the first core to the second core” [Jahagirdar ¶ 14]. “The processor 102 may determine (e.g., by examining an instruction cache of the core 104) that the first core 104 is incapable of executing one or more of the instructions 154 and that the second core 106 is capable of executing the instructions 154. For example, the processor 102 may determine that at least one of the instructions 154 is excluded from the first instruction set 120 associated with the first core 104 and is included in the second instruction set 130 associated with the second core 106. The processor 102 may determine that a migration policy 134, such as the first migration policy 136, applies. The migration policy 134 may instruct the processor 102 to migrate 156 the threads 104 from the first core 104 to the second core 106 when the threads 152 that are scheduled for execution by the first core 104 include the particular instructions 154 that are included in the second instruction set 130 but excluded from the first instruction set 120” [Jahagirdar ¶ 28].
With regard to claim 12, it is a method type claim having similar limitations as claim 1 above. Therefore, it is rejected under the same rationale.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jahagirdar et al. US 2014/0026146 A1 (hereafter Jahagirdar) in view of Griffen et al. US 2008/0126747 A1 (hereafter Griffen).
With regard to claim 2, Jahagirdar teaches:
The computer system as claimed in claim 1, as referenced above.
wherein: in response to an undefined instruction exception, the first-type core runs a first (interrupt) exception handler; “The processor 102 may determine that the first core 104 is incapable of executing at least one of the instructions 154 (e.g., the first instruction set 120 does not include at least one of the instructions 154) and generate the interrupt 220. An interrupt handler 222 associated with the operating system 148 may receive the interrupt 220 generated by the processor 102” [Jahagirdar ¶ 38].
the first (interrupt) exception handler determines whether a first target instruction causing the undefined instruction exception is one of the special instructions; “If the instructions 154 include specialized instructions, such as multimedia instructions, the interrupt handler 222 may instruct the interrupt handler 222 to migrate the threads 152 to a multimedia type of core” [Jahagirdar ¶ 39]. “The threads 152 may include specialized instructions (e.g., multimedia instructions) that the cores 104 and 106 are incapable of executing. When the specialized instructions of the threads 152 are scheduled for execution by the second core, the processor 102 or the operating system 148 may migrate 158 the threads 152 from the second core 106 to a specialized core (e.g., the third core 402) that is capable of executing the specialized instructions” [Jahagirdar ¶ 53].
and in response to the first target instruction being one of the special instructions, the first (interrupt) exception handler calls an operating system scheduler to relate the application with the second-type core and schedule the second-type core to run the application. “In some instances, the interrupt 220 may instruct the interrupt handler 222 to migrate the threads 152 to a particular type of core. For example, if the instructions 154 are computationally intensive, the interrupt 220 may instruct the interrupt handler 222 to migrate the threads 152 to a core that is faster or more powerful (e.g., greater throughput). If the instructions 154 include specialized instructions, such as multimedia instructions, the interrupt handler 222 may instruct the interrupt handler 222 to migrate the threads 152 to a multimedia type of core” [Jahagirdar ¶ 39].
Jahagirdar fails to explicitly teach an undefined instruction exception … a first exception handler.
However, Griffen teaches an undefined instruction exception … a first exception handler “For example, a first arithmetic offloader 202 includes only the exception handler 220 that identifies and directs instructions that are undefined by and/or for the cores 120, 121 to the embedded partition 126 for execution” [Griffen ¶ 22].
Griffen is considered to be analogous to the claimed invention because it is in the same field of exception handling. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jahagirdar to incorporate the teachings of Griffen and include: an undefined instruction exception … a first exception handler. Doing so would allow for the handling of undefined instruction exceptions. “For example, if none of the cores 120,121 of the main partition supports SSE or VSSE instructions, a software agent executed by and/or on the example main OS 130 can trap an undefined exception fault and then re-direct the call to the embedded partition 126” [Griffen ¶ 11].
With regard to claim 13, it is a method type claim having similar limitations as claim 2 above. Therefore, it is rejected under the same rationale.
Claim(s) 3 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jahagirdar et al. US 2014/0026146 A1 (hereafter Jahagirdar) in view of Griffen et al. US 2008/0126747 A1 (hereafter Griffen) in view of Shafi et al. US 2025/0005157 A1 (hereafter Shafi).
With regard to claim 3, Jahagirdar teaches:
wherein: the first (interrupt) exception handler manages a special instruction(s) table “If the instructions 154 include specialized instructions, such as multimedia instructions, the interrupt handler 222 may instruct the interrupt handler 222 to migrate the threads 152 to a multimedia type of core” [Jahagirdar ¶ 39].
the special instructions; “For example, the second core 106 may be a specialized processor with a specialized instruction set, such as a graphics processor, a multimedia processor, a mathematics processor (e.g., to perform floating point operations), another type of specialized processor, or any combination thereof” [Jahagirdar ¶ 19].
and in response to the undefined instruction (interrupt) exception, the first (interrupt) exception handler searches the special instruction(s) table for an opcode of the first target instruction “If the instructions 154 include specialized instructions, such as multimedia instructions, the interrupt handler 222 may instruct the interrupt handler 222 to migrate the threads 152 to a multimedia type of core” [Jahagirdar ¶ 39]. “The processor 102 may determine (e.g., by examining an instruction cache of the core 104) that the first core 104 is incapable of executing one or more of the instructions 154 and that the second core 106 is capable of executing the instructions 154. For example, the processor 102 may determine that at least one of the instructions 154 is excluded from the first instruction set 120 associated with the first core 104 and is included in the second instruction set 130 associated with the second core 106” [Jahagirdar ¶ 28].
the first exception handler determines that the first target instruction is one of the special instructions. “The processor may determine that the threads scheduled for execution by the first core include particular instructions that are not supported by the first core or that the second core would execute faster than the first core” [Jahagirdar ¶ 14]. “If the instructions 154 include specialized instructions, such as multimedia instructions, the interrupt handler 222 may instruct the interrupt handler 222 to migrate the threads 152 to a multimedia type of core” [Jahagirdar ¶ 39].
Jahagirdar fails to explicitly teach the undefined instruction exception … the first exception handler.
However, Griffen teaches the undefined instruction exception … the first exception handler “For example, a first arithmetic offloader 202 includes only the exception handler 220 that identifies and directs instructions that are undefined by and/or for the cores 120, 121 to the embedded partition 126 for execution” [Griffen ¶ 22].
Jahagirdar in view of Griffen fails to explicitly teach wherein: the first exception handler manages a special instruction table to list opcodes of the special instructions; searches the special instruction table for an opcode of the first target instruction and, if the opcode of the first target instruction is listed in the special instruction table, the first exception handler determines that the first target instruction is one of the special instructions.
However, Shafi teaches:
wherein: the first exception handler manages a special instruction table to list opcodes of (patched) the special instructions; “In certain embodiments, receipt of an instruction for decoding causes execution of enhanced patch code 612, which compares that instruction, e.g., its opcode, to a list of opcodes for patched instruction(s)” [Shafi ¶ 88].
searches the special instruction table for an opcode of the first target instruction and, if the opcode of the first target instruction is listed in the special instruction table, the first exception handler determines that the first target instruction is one of the (patched) special instructions. “In certain embodiments, an instruction is received (e.g., by a microcode sequencer) for decoding, and it is determined (e.g., by the comparing the opcode of that instruction to a list of opcodes for patched instructions) that the instruction is one that is to-be-patched (e.g., using additional and/or different micro-operations than those stored in read-only memory 604)” [Shafi ¶ 88].
Shafi is considered to be analogous to the claimed invention because it is in the same field of instruction decode. Jahagirdar teaches an interrupt handler which determines if an instruction is included in a set of special instructions and Shafi teaches using an instruction table to determine if an instruction is one of a set of instructions. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jahagirdar in view of Griffen to incorporate the teachings of Shafi and include: the first exception handler manages a special instruction table to list opcodes of the special instructions; searches the special instruction table for an opcode of the first target instruction and, if the opcode of the first target instruction is listed in the special instruction table, the first exception handler determines that the first target instruction is one of the special instructions. Doing so would allow for the first target instruction to be compared with the special instructions using opcodes of the instructions. “… by the comparing the address, pointer, or opcode of that instruction to a list of addresses, pointers, or opcodes for patched instructions … [Shafi ¶ 84].
With regard to claim 14, it is a method type claim having similar limitations as claim 3 above. Therefore, it is rejected under the same rationale.
Claim(s) 4, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jahagirdar et al. US 2014/0026146 A1 (hereafter Jahagirdar) in view of Rogers et al. US 2008/0209563 A1 (hereafter Rogers).
With regard to claim 4, Jahagirdar teaches:
The computer system as claimed in claim 1, as referenced above.
wherein: in response to a general-purpose (interrupt) exception, the first-type core runs a second (interrupt) exception handler; “The processor 102 may determine that the first core 104 is incapable of executing at least one of the instructions 154 (e.g., the first instruction set 120 does not include at least one of the instructions 154) and generate the interrupt 220. An interrupt handler 222 associated with the operating system 148 may receive the interrupt 220 generated by the processor 102” [Jahagirdar ¶ 38].
the second (interrupt) exception handler determines whether a second target instruction causing the general-purpose exception is one of the special instructions; “If the instructions 154 include specialized instructions, such as multimedia instructions, the interrupt handler 222 may instruct the interrupt handler 222 to migrate the threads 152 to a multimedia type of core” [Jahagirdar ¶ 39]. “The threads 152 may include specialized instructions (e.g., multimedia instructions) that the cores 104 and 106 are incapable of executing. When the specialized instructions of the threads 152 are scheduled for execution by the second core, the processor 102 or the operating system 148 may migrate 158 the threads 152 from the second core 106 to a specialized core (e.g., the third core 402) that is capable of executing the specialized instructions” [Jahagirdar ¶ 53].
and in response to the second target instruction being one of the special instructions, the second (interrupt) exception handler calls an operating system scheduler to relate the application with the second-type core and schedule the second-type core to run the application. “In some instances, the interrupt 220 may instruct the interrupt handler 222 to migrate the threads 152 to a particular type of core. For example, if the instructions 154 are computationally intensive, the interrupt 220 may instruct the interrupt handler 222 to migrate the threads 152 to a core that is faster or more powerful (e.g., greater throughput). If the instructions 154 include specialized instructions, such as multimedia instructions, the interrupt handler 222 may instruct the interrupt handler 222 to migrate the threads 152 to a multimedia type of core” [Jahagirdar ¶ 39].
Jahagirdar fails to explicitly teach a general-purpose exception … a second exception handler.
However, Griffen teaches a general-purpose exception … a second exception handler “There can also be general exception handlers that handle exceptions that are not anticipated by the designers of the system” [Rogers ¶ 53].
Rogers is considered to be analogous to the claimed invention because it is in the same field of exception handling. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jahagirdar to incorporate the teachings of Rogers and include: a general-purpose exception … a second exception handler. Doing so would allow for the handling of unanticipated exceptions. “There can also be general exception handlers that handle exceptions that are not anticipated by the designers of the system” [Rogers ¶ 53].
With regard to claim 15, it is a method type claim having similar limitations as claim 4 above. Therefore, it is rejected under the same rationale.
Claim(s) 5, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jahagirdar et al. US 2014/0026146 A1 (hereafter Jahagirdar) in view of Rogers et al. US 2008/0209563 A1 (hereafter Rogers) in view of Wang et al. US 2022/0206815 A1 (hereafter Wang).
With regard to claim 5, Jahagirdar in view of Rogers teaches the computer system as claimed in claim 4, as referenced above. Jahagirdar further teaches the second exception handler determines whether the second target instruction is one of the special instructions. “The interrupt handler 222 may migrate the threads 152 based on information include in the interrupt 220, the migration policies 218, or both” [Jahagirdar ¶ 38]. “If the instructions 154 include specialized instructions, such as multimedia instructions, the interrupt handler 222 may instruct the interrupt handler 222 to migrate the threads 152 to a multimedia type of core” [Jahagirdar ¶ 39]. “The threads 152 may include specialized instructions (e.g., multimedia instructions) that the cores 104 and 106 are incapable of executing. When the specialized instructions of the threads 152 are scheduled for execution by the second core, the processor 102 or the operating system 148 may migrate 158 the threads 152 from the second core 106 to a specialized core (e.g., the third core 402) that is capable of executing the specialized instructions” [Jahagirdar ¶ 53].
Jahagirdar in view of Rogers fails to explicitly teach wherein: according to an exception code of the general-purpose exception.
However, Wang teaches wherein: according to an exception code of the general-purpose exception, “If an exception occurs, the processor 110 executes the microcode handler of the exception according to the exception code stored in the exception vector table. That is, the exception handler corresponding to the above exception code is executed” [Wang ¶ 112].
Wang is considered to be analogous to the claimed invention because it is in the same field of exception handling. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jahagirdar in view of Rogers to incorporate the teachings of Wang and include: according to an exception code of the general-purpose exception. Doing so would allow for identification of the exception and how to handle it. “When the exception flag is the first exception value, the value of the exception code field is the exception code, which is usually represented by an integer value” [Wang ¶ 78].
With regard to claim 16, it is a method type claim having similar limitations as claim 5 above. Therefore, it is rejected under the same rationale.
Claim(s) 6, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jahagirdar et al. US 2014/0026146 A1 (hereafter Jahagirdar) in view of Rogers et al. US 2008/0209563 A1 (hereafter Rogers) in view of Wang et al. US 2022/0206815 A1 (hereafter Wang) in view of Zhu et al. US 2017/0344375 A1 (hereafter Zhu).
With regard to claim 6, Jahagirdar in view of Rogers teaches the computer system as claimed in claim 4, as referenced above. Jahagirdar further teaches the second exception handler determines whether the second target instruction is one of the special instructions. “The interrupt handler 222 may migrate the threads 152 based on information include in the interrupt 220, the migration policies 218, or both” [Jahagirdar ¶ 38]. “If the instructions 154 include specialized instructions, such as multimedia instructions, the interrupt handler 222 may instruct the interrupt handler 222 to migrate the threads 152 to a multimedia type of core” [Jahagirdar ¶ 39]. “The threads 152 may include specialized instructions (e.g., multimedia instructions) that the cores 104 and 106 are incapable of executing. When the specialized instructions of the threads 152 are scheduled for execution by the second core, the processor 102 or the operating system 148 may migrate 158 the threads 152 from the second core 106 to a specialized core (e.g., the third core 402) that is capable of executing the specialized instructions” [Jahagirdar ¶ 53].
Jahagirdar in view of Rogers fails to explicitly teach according to an opcode of the second target instruction as well as an exception code of the general-purpose exception.
However, Wang teaches according to an opcode of the second target instruction as well as an exception code of the general-purpose exception, “If an exception occurs, the processor 110 executes the microcode handler of the exception according to the exception code stored in the exception vector table. That is, the exception handler corresponding to the above exception code is executed” [Wang ¶ 112].
It would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jahagirdar in view of Rogers to incorporate the teachings of Wang and include: according to an opcode of the second target instruction as well as an exception code of the general-purpose exception. Doing so would allow for identification of the exception and how to handle it. “When the exception flag is the first exception value, the value of the exception code field is the exception code, which is usually represented by an integer value” [Wang ¶ 78].
Jahagirdar in view of Rogers in view of Wang fails to explicitly teach wherein: according to an opcode of the second target instruction.
However, Zhu teaches wherein: according to an opcode of the second target instruction “As illustrated in the figure, a special opcode is included in the first tokens of the instructions so that the decoder may determine whether or not the instruction is a special loop instruction” [Zhu ¶ 38].
Zhu is considered to be analogous to the claimed invention because it is in the same field of instruction decode. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jahagirdar in view of Rogers in view of Wang to incorporate the teachings of Zhu and include: according to an opcode of the second target instruction. Doing so would allow for the determination of whether the target instruction is one of the special instructions using the opcodes of the instructions. “… so that the decoder may determine whether or not the instruction is a special loop instruction” [Zhu ¶ 38].
With regard to claim 17, it is a method type claim having similar limitations as claim 6 above. Therefore, it is rejected under the same rationale.
Claim(s) 7-10 and 18-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jahagirdar et al. US 2014/0026146 A1 (hereafter Jahagirdar) in view of Mubeen et al. US 2022/0058029 A1 (hereafter Mubeen) in view of Samih et al. US 2020/0201671 A1 (hereafter Samih).
With regard to claim 7, Jahagirdar teaches:
The computer system as claimed in claim 1, as referenced above.
further comprising: a system memory; “The device 802 may include one or more processors, such as the processor 102, a clock generator 804, the memory 132, an input/output control hub 806, and a power source 808 (e.g., a battery or a power supply)” [Jahagirdar ¶ 66].
reading an identification code from each core for identification of the first-type core and the second-type core, “The processor 102 may provide information about the characteristics 108, 110, and 204 of the cores 104, 106, and 202 to the operating system 148 via an identifier, such as the core characteristics identifier 206 (identification code)… In some implementations, the operating system 148 may use the read core characteristics instruction 216 to read the contents of the core characteristics identifier 206” [Jahagirdar ¶ 40-41]. “The first core 104 may have an associated set of first characteristics 108. The second core 106 may have an associated set of second characteristics 110. The first set of characteristics 108 may include one or more characteristics, such as a first operating frequency 112, a first throughput 114 (e.g., an average number of instructions executed per second), a first power usage 116, first thermal characteristics 118, a first instruction set 120, another characteristic associated with the first core 102, or any combination thereof. The second set of characteristics 110 may include one or more characteristics, such as a second operating frequency 122, a second throughput 124 (e.g., an average number of instructions executed per second), a second power usage 126, second thermal characteristics 128, a second instruction set 130, another characteristic associated with the second core 104, or any combination thereof” [Jahagirdar ¶ 17]. “The core characteristics identifier 206 may be implemented as a bit mask, a data structure, or another type of identifier. For example, when the cores 104, 106, and 202 include two types of cores, the core characteristics identifier 206 may be a bit mask in which "0" identifies a first type of core (e.g., a lower power usage and lower performance type of core) and "1" identifies a second type of core (e.g., a higher power usage and higher performance core)” [Jahagirdar ¶ 33].
and stores the identification code of each core in the system memory, to be read by an operating system later to form core information; “The processor 102 may provide information about the characteristics 108, 110, and 204 of the cores 104, 106, and 202 to the operating system 148 via an identifier, such as the core characteristics identifier 206. The processor 102 may periodically monitor the characteristics 108, 110, or 204 and periodically or dynamically (e.g., in response to a particular characteristic satisfying a predetermined threshold) update one or more of the identifiers 208, 210, or 212 based on the characteristics 108, 110, or 204. In some implementations, the operating system 148 may use the read core characteristics instruction 216 to read the contents of the core characteristics identifier 206” [Jahagirdar ¶ 40-41]. “The memory 132 may be used to a store a core characteristics identifier 206 that identifies one or more characteristics of the multiple cores in the processor 102. In some implementations, the core characteristics identifier 206 may include multiple identifiers, with each identifier corresponding to a core of the processor 102” [Jahagirdar ¶ 31].
and the operating system migrates the application process based on the core information, to switch to the second-type core to run the application. “The processor 102 or the operating system 148 may determine to migrate 156 the threads 152 (e.g., initiate migration of the threads 152) from the first core 104 to the second core 106 based on the instructions 154, the first characteristics 108, the second characteristics 110, the migration policies 134, the core characteristics identifier 206, or any combination thereof” [Jahagirdar ¶ 44].
Jahagirdar fails to explicitly teach and a basic input and output system.
However, Mubeen teaches and a basic input and output system, “In yet other embodiments, power management operations to be performed by p-unit 608 may be implemented within BIOS or other system software” [Mubeen ¶ 44].
Mubeen is considered to be analogous to the claimed invention because it is in the same field of initialization of multiprocessor systems. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jahagirdar to incorporate the teachings of Mubeen and include: a basic input and output system. Doing so would allow for the implementation of power management operations. “In yet other embodiments, power management operations to be performed by p-unit 608 may be implemented within BIOS or other system software” [Mubeen ¶ 44].
Jahagirdar in view of Mubeen fails to explicitly teach wherein: the operating system generates an application process corresponding to the application.
However, Samih teaches wherein: the operating system generates an application process corresponding to the application; “In embodiments, each thread 140 is generated by an application or process initiated by an operating system 150 executed by the processor circuitry 130” [Samih ¶ 38].
Jahagirdar teaches the processing of application threads and Samih teaches thread initiation. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jahagirdar in view of Mubeen to incorporate the teachings of Samih and include: the operating system generates an application process corresponding to the application. Doing so would combine the elements as claimed by known methods, and the elements would preform the same functions as they do separately. A person of ordinary skill in the art would have recognized that the results of this combination were predictable.
With regard to claim 8, Jahagirdar in view Mubeen in view of Samih teaches the computer system as claimed in claim 7, as referenced above. Jahagirdar further teaches:
wherein: the basic input and output system creates an advanced configuration and power interface (identifier) table for each core, “In some implementations, the core characteristics identifier 206 may include multiple identifiers, with each identifier corresponding to a core of the processor 102” [Jahagirdar ¶ 31]. “The core characteristics identifier 206 may identify one or more of the characteristics 108, 110, or 204 associated with the cores 104, 106, or 202” [Jahagirdar ¶ 32]. “The first set of characteristics 108 may include one or more characteristics, such as a first operating frequency 112, a first throughput 114 (e.g., an average number of instructions executed per second), a first power usage 116, first thermal characteristics 118, a first instruction set 120, another characteristic associated with the first core 102, or any combination thereof” [Jahagirdar ¶ 17].
and the basic input and output system programs the advanced configuration and power interface (identifier) table of each core into the system memory, to be read by an operating system later to form the core information. “The processor 102 may provide information about the characteristics 108, 110, and 204 of the cores 104, 106, and 202 to the operating system 148 via an identifier, such as the core characteristics identifier 206. The processor 102 may periodically monitor the characteristics 108, 110, or 204 and periodically or dynamically (e.g., in response to a particular characteristic satisfying a predetermined threshold) update one or more of the identifiers 208, 210, or 212 based on the characteristics 108, 110, or 204. In some implementations, the operating system 148 may use the read core characteristics instruction 216 to read the contents of the core characteristics identifier 206” [Jahagirdar ¶ 40-41]. “The memory 132 may be used to a store a core characteristics identifier 206 that identifies one or more characteristics of the multiple cores in the processor 102. In some implementations, the core characteristics identifier 206 may include multiple identifiers, with each identifier corresponding to a core of the processor 102” [Jahagirdar ¶ 31].
Jahagirdar fails to teach an advanced configuration and power interface table … and programs the identification code of each core into a flag field in the corresponding advanced configuration and power interface table.
However, Mubeen teaches:
an advanced configuration and power interface table “In some embodiments, at block 703, the microcode or BIOS then shares the APIC IDs of the cores ranked based on efficiency to the operation system (or kernel). For example, the microcode or BIOS shares the APIC IDs of the cores ranked based on efficiency to the OS via ACPI (Advanced Configuration and Power Interface) tables such as the MADT (multiple interrupt controller table)” [Mubeen ¶ 53].
“In some embodiments, the firmware shares the ranked APIC IDs via an Advanced Configuration and Power Interface (ACPI) table” [Mubeen ¶ 48].
and programs the identification code of each core into a flag field in the corresponding advanced configuration and power interface table; “As such, microcode or BIOS calculates and ranks core APIC IDs based on efficiency around LFM frequencies… In some embodiments, at block 703, the microcode or BIOS then shares the APIC IDs of the cores ranked based on efficiency to the operation system (or kernel). For example, the microcode or BIOS shares the APIC IDs of the cores ranked based on efficiency to the OS via ACPI (Advanced Configuration and Power Interface) tables such as the MADT (multiple interrupt controller table)” [Mubeen ¶ 52-53].
With regard to claim 9, Jahagirdar in view of Mubeen in view of Samih teaches the computer system as claimed in claim 7, as referenced above. Jahagirdar further teaches wherein: the basic input and output system executes an acquiring identification code instruction on each core to obtain the identification code of each core. “In some implementations, the operating system 148 may use the read core characteristics instruction 216 to read the contents of the core characteristics identifier 206” [Jahagirdar ¶ 41].
Jahagirdar fails to teach wherein: the basic input and output system executes an acquiring identification code instruction on each core to obtain the identification code of each core.
However, Mubeen teaches wherein: the basic input and output system executes an acquiring identification code instruction on each core to obtain the identification code of each core. “In that context, at block 701, the microcode (e.g., pCode) or BIOS (built-in input output system) reads the fuses or NVM that store the per-core V min values. These fuses are programmed during HVM. Upon reading the fuses or NVM, the microcode or BIOS calculates and ranks the cores as discussed with reference to FIG. 5. As such, microcode or BIOS calculates and ranks core APIC IDs based on efficiency around LFM frequencies” [Mubeen ¶ 52].
With regard to claim 10, Jahagirdar in view of Mubeen in view of Samih teaches the computer system as claimed in claim 7, as referenced above. Jahagirdar further teaches wherein: each core stores the identification code “The memory 132 may be used to a store a core characteristics identifier 206 that identifies one or more characteristics of the multiple cores in the processor 102. In some implementations, the core characteristics identifier 206 may include multiple identifiers, with each identifier corresponding to a core of the processor 102” [Jahagirdar ¶ 31].
Jahagirdar fails to teach wherein: each core stores the identification code in a model-specific register to be read by the basic input and output system.
However, Mubeen teaches wherein: each core stores the identification code in a model-specific register to be read by the basic input and output system. “If the SoC supports dynamic HW feedback, then the process proceeds to block 707 where pCode (or any suitable microcode or firmware) shares the updated efficiency core ranking via shared memory or model-specific register (MSR) interface” [Mubeen ¶ 55]. “In that context, the microcode (e.g., pCode) or BIOS 5520 (built-in input output system) reads the fuses or NVM that store the per-core V min values. These fuses or NVM are programmed during HVM. Upon reading the fuses or NVM, the microcode or BIOS 5520 calculates and ranks the cores. As such, microcode (e.g., pCode) or BIOS 5520 calculates and ranks core APIC IDs based on efficiency around LFM (low frequency mode) frequencies” [Mubeen ¶ 135].
With regard to claim 18, it is a method type claim having similar limitations as claim 7 above. Therefore, it is rejected under the same rationale.
Jahagirdar teaches the further limitation of and programming the identification code of each core into a system memory “The processor 102 may provide information about the characteristics 108, 110, and 204 of the cores 104, 106, and 202 to the operating system 148 via an identifier, such as the core characteristics identifier 206. The processor 102 may periodically monitor the characteristics 108, 110, or 204 and periodically or dynamically (e.g., in response to a particular characteristic satisfying a predetermined threshold) update one or more of the identifiers 208, 210, or 212 based on the characteristics 108, 110, or 204. In some implementations, the operating system 148 may use the read core characteristics instruction 216 to read the contents of the core characteristics identifier 206” [Jahagirdar ¶ 40-41]. “The memory 132 may be used to a store a core characteristics identifier 206 that identifies one or more characteristics of the multiple cores in the processor 102. In some implementations, the core characteristics identifier 206 may include multiple identifiers, with each identifier corresponding to a core of the processor 102” [Jahagirdar ¶ 31].
Mubeen teaches the further limitation of operating a basic input and output system to read an identification code from each core “In that context, the microcode (e.g., pCode) or BIOS 5520 (built-in input output system) reads the fuses or NVM that store the per-core V min values. These fuses or NVM are programmed during HVM. Upon reading the fuses or NVM, the microcode or BIOS 5520 calculates and ranks the cores. As such, microcode (e.g., pCode) or BIOS 5520 calculates and ranks core APIC IDs based on efficiency around LFM (low frequency mode) frequencies” [Mubeen ¶ 135].
With regard to claim 19, it is a method type claim having similar limitations as claim 8 above. Therefore, it is rejected under the same rationale.
With regard to claim 20, it is a method type claim having similar limitations as claim 9 above. Therefore, it is rejected under the same rationale.
With regard to claim 21, it is a method type claim having similar limitations as claim 10 above. Therefore, it is rejected under the same rationale.
Claim(s) 11 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jahagirdar et al. US 2014/0026146 A1 (hereafter Jahagirdar) in view of Mubeen et al. US 2022/0058029 A1 (hereafter Mubeen) in view of Samih et al. US 2020/0201671 A1 (hereafter Samih) in view of Tang US 2023/0325187 A1 (hereafter Tang).
With regard to claim 11, Jahagirdar in view of Mubeen in view of Samih teaches the computer system as claimed in claim 7, as referenced above. Jahagirdar in view of Mubeen in view of Samih fails to teach wherein: when the operating system starts, the operating system registers a first exception handler and a second exception handler.
However, Tang teaches wherein: when the operating system starts, the operating system registers a first exception handler and a second exception handler. “Specifically, the Android system registers two handlers, i.e., a second default thread exception handler (LoggingHandler) and a first
default thread exception handler (KillApplicationHandler), with all threads on its startup” [Tang ¶ 17].
Tang is considered to be analogous to the claimed invention because it is in the same field of arrangements for executing machine instructions. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jahagirdar in view of Mubeen in view of Samih to incorporate the teachings of Tang and include: when the operating system starts, the operating system registers a first exception handler and a second exception handler. Doing so would allow for the processing of exceptions in the system. “The two handlers are default processors that may be configured to process an exception when the exception has occurred in a thread of the Android system” [Tang ¶ 17].
With regard to claim 22, it is a method type claim having similar limitations as claim 11 above. Therefore, it is rejected under the same rationale.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARI F RIGGINS whose telephone number is (571)272-2772. The examiner can normally be reached Monday-Friday 7:00AM-4:30PM.
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/A.F.R./Examiner, Art Unit 2197
/JOANNE G MACASIANO/Examiner, Art Unit 2197
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