Prosecution Insights
Last updated: April 19, 2026
Application No. 18/630,129

SWITCHING POWER CONVERTERS CONFIGURED TO INJECT CURRENT INTO AN OUTPUT NODE

Non-Final OA §102§112
Filed
Apr 09, 2024
Examiner
TORRES-RIVERA, ALEX
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Maxim Integrated Products Inc.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
2y 3m
To Grant
98%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allow Rate
648 granted / 752 resolved
+18.2% vs TC avg
Moderate +12% lift
Without
With
+11.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
32 currently pending
Career history
784
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
52.8%
+12.8% vs TC avg
§102
27.7%
-12.3% vs TC avg
§112
16.4%
-23.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 752 resolved cases

Office Action

§102 §112
DETAILED ACTION This action is in response to the Application filed on 04/09/2024. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Information Disclosure Statement The information disclosure statement(s) (IDS) submitted on 04/09/2024 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner. Specification The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 2 recites “the injection capacitor”. Claim 1 claims a blocking capacitor, however, it is unclear if Applicant is attempting to claim a different capacitor or if it corresponds to the blocking capacitor. For examination purpose, the Examiner is going to assume that the “injection capacitor” is the same as the “blocking capacitor”. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1 – 19 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US Pub. No. 2024/0405678; (hereinafter Nisimoto). Regarding claim 1, Nishimoto [e.g. Fig. 1] discloses a switching power converter, comprising: a plurality of power stages, each power stage including a respective power transformer [e.g. TR1, TR2, …, TRN]; and a blocking capacitor [e.g. C3]; wherein the blocking capacitor and a respective secondary winding [e.g. Ls1, Ls2, Lsn] of each power transformer are electrically coupled in series between an output power node [e.g. T2] of the switching power converter and a reference node [e.g. ground] of the switching power converter. Regarding claim 2, Nishimoto [e.g. Fig. 1] discloses further comprising a tuning inductor [e.g. L2] electrically coupled in series with the injection capacitor [e.g. C3] and the respective secondary winding of each power transformer. Regarding claim 3, Nishimoto [e.g. Fig. 1] discloses further comprising a controller [e.g. 10] configured to control duty cycle of the plurality of power stages to regulate at least one parameter of the switching power converter [e.g. paragraph 09 recites “An object of the present disclosure is to provide a voltage regulator capable of suppressing ripples of an output current while maintaining a high response to a load fluctuation without using a large noise filter in a voltage regulator such as TLVR, and a power converter apparatus including the voltage regulator”. Further, paragraph 032 recites “The step-down chopper operation (or step-down switching operation) of each of the step-down chopper circuits B1 to Bn is controlled based on gate control signals Sg11, Sg12; Sg21, Sg22; . . . ; Sgn1, Sgn2 from the control circuit 10. That is, the step-down chopper circuits B1 to Bn include switching circuits 11-1 to 11-n, respectively, and the switching circuits 11-1 to 11-n switch the input voltage Vin according to gate control signals Sg11, Sg12; Sg21, Sg22; . . . ; Sgn1, Sgn2 to convert the input voltage Vin into an AC voltage and output the AC voltage to inductors Lp1 to Lpn of primary windings of transformers TR1 to TRn”]. Regarding claim 4, Nishimoto [e.g. Fig. 1] discloses wherein each power transformer includes a respective primary winding [e.g. Lp1, Lp2, …, Lpn] electrically coupled to the output power node of the switching power converter [e.g. T2]. Regarding claim 5, Nishimoto [e.g. Fig. 1] discloses wherein the switching power converter is configured such that current flowing through the secondary windings of the power transformers at least partially cancels ripple current flowing through the primary windings of the power transformers, at the output power node of the switching power converter [e.g. paragraph 014 recites “according to the voltage regulator according to one aspect of the present disclosure, it is possible to significantly suppress ripples of the output current”]. Regarding claim 6, Nishimoto [e.g. Fig. 1] discloses wherein the switching power converter is configured such that current flowing through the secondary windings of the power transformers [e.g. I1] adds to alternating current flowing through the primary windings of the power transformers [e.g. I3], at the output power node of the switching power converter [e.g. T2]. Regarding claim 7, Nishimoto [e.g. Fig. 1] discloses wherein each power stage further includes a respective switching stage [e.g. St1, Sb1, St2, Sb2,…Stn, Sbn] electrically coupled to the primary winding of the respective power transformer of the power stage. Regarding claim 8, Nishimoto [e.g. Fig. 1] discloses wherein the switching power converter has a buck-type topology [e.g. Abstract recites “A voltage regulator includes chopper circuits connected in parallel, and a second series circuit”, as shown in Fig. 1, the chopper constitute a buck converter topology]. Regarding claim 9, Nishimoto [e.g. Fig. 1] discloses a switching power converter, comprising: a first power stage, the first power stage including: a first switching stage [e.g. St1, Sb1], a first power transformer [e.g. TR1] including a first primary winding [e.g. Lp1] and a first secondary winding [e.g. Ls1], the first primary winding being electrically coupled between the first switching stage and an output power node of the switching power converter [e.g. T2]; a second power stage, the second power stage including: a second switching stage [e.g. St2, Sb2], a second power transformer [e.g. TR2] including a second primary winding [e.g. Lp2] and a second secondary winding [e.g. Ls2], the second primary winding being electrically coupled between the second switching stage and the output power node of the switching power converter; and a blocking capacitor [e.g. C2]; wherein the blocking capacitor, the first secondary winding, and the second secondary winding are electrically coupled in series between the output power node [e.g. T2] of the switching power converter and a reference node [e.g. ground] of the switching power converter. Regarding claim 10, Nishimoto [e.g. Fig. 1] discloses further comprising a third power stage, the third power stage including: a third switching stage [e.g. Stn, Sbn]; and a third power transformer [e.g. TRn] including a third primary winding [e.g. Lpn] and a third secondary winding [e.g. Lsn], the third primary winding being electrically coupled between the third switching stage and the output power node of the switching power converter; wherein the blocking capacitor, the first secondary winding, the second secondary winding, and the third secondary winding are electrically coupled in series between the output power node of the switching power converter and the reference node of the switching power converter [e.g. as shown]. Regarding claim 11, Nishimoto [e.g. Fig. 1] discloses further comprising a controller [e.g. 10], the controller being configured to control at least the first switching stage and the second switching stage to regulate at least one parameter of the switching power converter [e.g. paragraph 09 recites “An object of the present disclosure is to provide a voltage regulator capable of suppressing ripples of an output current while maintaining a high response to a load fluctuation without using a large noise filter in a voltage regulator such as TLVR, and a power converter apparatus including the voltage regulator”. Further, paragraph 032 recites “The step-down chopper operation (or step-down switching operation) of each of the step-down chopper circuits B1 to Bn is controlled based on gate control signals Sg11, Sg12; Sg21, Sg22; . . . ; Sgn1, Sgn2 from the control circuit 10. That is, the step-down chopper circuits B1 to Bn include switching circuits 11-1 to 11-n, respectively, and the switching circuits 11-1 to 11-n switch the input voltage Vin according to gate control signals Sg11, Sg12; Sg21, Sg22; . . . ; Sgn1, Sgn2 to convert the input voltage Vin into an AC voltage and output the AC voltage to inductors Lp1 to Lpn of primary windings of transformers TR1 to TRn”]. Regarding claim 12, Nishimoto [e.g. Fig. 10] discloses a switching power converter, comprising: a plurality of power stages [e.g. B1-Bn], each power stage including a respective power transfer winding [e.g. Ls1-Lsn]; a boost winding [e.g. L2] forming at least one turn around a respective leakage magnetic flux path of each power transfer winding [e.g. magnetic flux between L2 and Ls1-Lsn]; and a blocking capacitor [e.g. C3]; wherein the blocking capacitor and the boost winding are electrically coupled in series between an output power node [e.g. T2] of the switching power converter and a reference node of the switching power converter [e.g. ground]. Regarding claim 13 Nishimoto [e.g. Fig. 10] discloses further comprising a controller [e.g. 10] configured to control duty cycle of the plurality of power stages to regulate at least one parameter of the switching power converter [e.g. paragraph 09 recites “An object of the present disclosure is to provide a voltage regulator capable of suppressing ripples of an output current while maintaining a high response to a load fluctuation without using a large noise filter in a voltage regulator such as TLVR, and a power converter apparatus including the voltage regulator”. Further, paragraph 032 recites “The step-down chopper operation (or step-down switching operation) of each of the step-down chopper circuits B1 to Bn is controlled based on gate control signals Sg11, Sg12; Sg21, Sg22; . . . ; Sgn1, Sgn2 from the control circuit 10. That is, the step-down chopper circuits B1 to Bn include switching circuits 11-1 to 11-n, respectively, and the switching circuits 11-1 to 11-n switch the input voltage Vin according to gate control signals Sg11, Sg12; Sg21, Sg22; . . . ; Sgn1, Sgn2 to convert the input voltage Vin into an AC voltage and output the AC voltage to inductors Lp1 to Lpn of primary windings of transformers TR1 to TRn”]. Regarding claim 14, Nishimoto [e.g. Fig. 10] discloses wherein each power stage further includes a respective switching stage [e.g. St1, Sb1, St2, Sb2,…, Stn, Sbn] electrically coupled to the respective power transfer winding of the power stage [e.g. Ls1-Lsn]. Regarding claim 15, Nishimoto [e.g. Fig. 10] discloses further comprising a controller [e.g. 10] configured to control the respective switching stage of each power stage to regulate at least one parameter of the switching power converter [e.g. paragraph 09 recites “An object of the present disclosure is to provide a voltage regulator capable of suppressing ripples of an output current while maintaining a high response to a load fluctuation without using a large noise filter in a voltage regulator such as TLVR, and a power converter apparatus including the voltage regulator”. Further, paragraph 032 recites “The step-down chopper operation (or step-down switching operation) of each of the step-down chopper circuits B1 to Bn is controlled based on gate control signals Sg11, Sg12; Sg21, Sg22; . . . ; Sgn1, Sgn2 from the control circuit 10. That is, the step-down chopper circuits B1 to Bn include switching circuits 11-1 to 11-n, respectively, and the switching circuits 11-1 to 11-n switch the input voltage Vin according to gate control signals Sg11, Sg12; Sg21, Sg22; . . . ; Sgn1, Sgn2 to convert the input voltage Vin into an AC voltage and output the AC voltage to inductors Lp1 to Lpn of primary windings of transformers TR1 to TRn”]. Regarding claim 16, Nishimoto [e.g. Fig. 10] discloses further comprising a tuning inductor [e.g. L3] electrically coupled in series with the blocking capacitor and the boost winding. Regarding claim 17, Nishimoto [e.g. Fig. 1] discloses wherein the switching power converter is configured such that current flowing through the boost winding at least partially cancels ripple current flowing through the power transfer windings of the power stages, at the output power node of the switching power converter [e.g. paragraph 014 recites “according to the voltage regulator according to one aspect of the present disclosure, it is possible to significantly suppress ripples of the output current”]. Regarding claim 18, Nishimoto [e.g. Fig. 10] discloses wherein the switching power converter is configured such that current flowing through the boost winding [e.g. I1] adds to alternating current flowing through the power transfer windings [e.g. I3] of the power stages, at the output power node of the switching power converter [e.g. T2]. Regarding claim 19, Nishimoto [e.g. Fig. 10] discloses wherein the switching power converter has a buck-type topology [e.g. Abstract recites “A voltage regulator includes chopper circuits connected in parallel, and a second series circuit”, as shown in Fig. 1, the chopper constitute a buck converter topology]. Examiner's Note Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention. Allowable Subject Matter Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The primary reason for the indication of the allowability of claim 20 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “further comprising a transformer, wherein the boost winding is electrically coupled in series with the blocking capacitor via the transformer”. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alex Torres-Rivera whose telephone number is (571)272-5261. The examiner can normally be reached M-F 9:00-5:30 ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MONICA LEWIS can be reached at (571) 272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ALEX TORRES-RIVERA/Primary Examiner, Art Unit 2838
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Prosecution Timeline

Apr 09, 2024
Application Filed
Jan 07, 2026
Non-Final Rejection — §102, §112 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
98%
With Interview (+11.9%)
2y 3m
Median Time to Grant
Low
PTA Risk
Based on 752 resolved cases by this examiner. Grant probability derived from career allow rate.

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