DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
For Examiner’s Interview fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html).
Status of claim(s) to be treated in this office action:
Independent: 1, 9 and 16.
Pending: 1-20.
Withdrawn: 1-8.
Information Disclosure Statement
Applicant’s IDS(s) submitted on 4/9/2024 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have considered by the examiner and made of record.
Election/Restrictions
Applicant's election with traverse of Species I claim 9-20 in the reply filed on 7/10/2026 is acknowledged. The traversal is on the ground(s) that species are not mutually exclusive. This is not found persuasive because in species II require to have a first overlay pattern and a second overlay pattern are spaced apart from each other, a pitch formed between the upper and lower pattern (DBOu and DBOI) wherein a distance is between upper and lower pattern, the distance is the same in all four overlay marks while cannot concurrently exist while species I require to have a first overlay pattern and a second overlay pattern are spaced apart from each other, a pitch formed between the main and vernier overlay pattern wherein a higher pitch is form on the edge of the overlay pattern and smaller pitch is form in the center of the overlay pattern, while cannot concurrently exist while species III require to have first overlay pattern 110c wherein the main and vernier pattern forming in a same plane and include advanced image metrology overlay marks, while cannot concurrently exist while species IV require to have a plurality of upper patterns DBOu and a plurality of lower patterns DBOI. In a plan view, the plurality of upper patterns DBOu may respectively overlap the plurality of lower patterns DBOI in a vertical direction (Z direction). Each of the plurality of upper patterns DBOu may have the same pitch as each of the plurality of lower patterns DBOI, while cannot concurrently exist while species V require to have a plurality of upper patterns DBOu and a plurality of lower patterns DBOI. In a plan view, the plurality of upper patterns DBOu may not overlap the plurality of lower patterns DBOI in a vertical direction (Z direction), therefore, there are mutually exclusive species.
Specification
The disclosure is objected to because of the following informalities:
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE HAVING ADJACENT OVERLAY AND TEST ELEMENT PATTERNS.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 9-10, 13-15 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Hajaj et al., US PG pub. 20220334501 A1.
Re: Independent Claim 9, Hajaj discloses a semiconductor substrate (12, fig. 1a) including an in-cell region and a scribe lane (¶0005; image an overlay target located in the scribe lines of the semiconductor substrate (the lines separating adjacent dies)) defining the in-cell region;
a first test pattern (fig. 3c) on the semiconductor substrate (12, fig. 1a); and
a second test pattern (fig. 3b) adjacent to the first test pattern (fig. 3c), wherein the first test pattern (fig. 3c) includes a first overlay pattern (330, 332, 334, 336, 338, 340, 342, and 344, fig. 3c),
the first test pattern (fig. 3c) includes a plurality of lower marks (38, fig. 1a-1b) and a plurality of upper marks (40, fig. 1a-1b) that are at different vertical levels,
at least one of the plurality of lower marks (38, fig. 1a-1b) and at least one of the plurality of upper marks (40, fig. 1a-1b) overlap each other in a vertical direction, and
a pitch (¶0057) of each of the plurality of lower marks (38, fig. 1a-1b) is different from a pitch (¶0057) of each of the plurality of upper marks (40, fig. 1a-1b).
Re: Claim 10, Hajaj disclose(s) all the limitations of claim 9 on which this claim depends. Hajaj further discloses: wherein the second test pattern (fig. 3b) comprises a first sub-pattern (38, fig. 1a) and a second sub-pattern (40, fig. 1a) respectively corresponding to a first cell pattern (314, fig. 3b) and a second cell pattern (316, fig. 3b) that are at different vertical levels (¶0057 38 and 40 with layer 38 below layer 40 which has different vertical levels) in the in-cell region (322, fig. 3b).
Re: Claim 13, Hajaj disclose(s) all the limitations of claim 9 on which this claim depends. Hajaj further discloses: wherein a length of each of the plurality of lower marks (38, fig. 1a-1b) and a length of each of the plurality of upper marks (40, fig. 1a-1b) are greater than a length (since upper marks and lower marks 40 and 38 include both region 3b and 3c the length would have a greater length than fig. 3b alone) of a mark of the second test pattern (fig. 3b).
Re: Claim 14, Hajaj disclose(s) all the limitations of claim 9 on which this claim depends. Hajaj further discloses: wherein the plurality of lower marks (38, fig. 1a-1b) and the plurality of upper marks (40, fig. 1a-1b) are arranged in a Moire pattern (as shown in figure 3a-3c).
Re: Claim 15, Hajaj disclose(s) all the limitations of claim 9 on which this claim depends. Hajaj further discloses: wherein the first test pattern (fig. 3c) and the second test pattern (fig. 3b) correspond to one test pattern group (fig. 3a), and the test pattern group is on the scribe lane (¶0005; image an overlay target located in the scribe lines of the semiconductor substrate, the lines separating adjacent dies).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11 and 12 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Hajaj et al., US PG pub. 20220334501 A1.
Re: Claim 11, Hajaj discloses all the limitations of claim 9 on which this claim depends. Hajaj further discloses: wherein the second test pattern (fig. 3b) comprises a plurality of marks (306, 308, 310, 312, 314, 316, 318, and 320, fig. 3b).
Hajaj is silent regarding: the plurality of marks for measuring a critical dimension (CD).
However, according to the MPEP, Section 2113, "Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process”. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985)
Re: Claim 12, Hajaj discloses all the limitations of claim 9 on which this claim depends. Hajaj further discloses: wherein the pitch (¶0057) of each of the plurality of lower marks (38, fig. 1a-1b) and the plurality of upper marks (40, fig. 1a-1b)
Hajaj is silent regarding: the plurality of marks is in a range from about 300 nanometers to about 900 nanometers. However, thickness range it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention because, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 105 USPQ 223, 235 (CCPA 1955). Furthermore, the specification contains no disclosure of either the critical nature of the claimed dimensions of any unexpected results arising therefrom. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2sd 1934, 1936 (Fed. Cir. 1990).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the system of Hajaj to have a smaller refine range of overlay marks since modification would have only involved a mere change in working range which involves only routine skill in the art one would have been motivated to make such modification to make those layer to have a thinner thickness to achieve the predictable result of miniaturization the overlay marks thereby improve by increase the usable area of the device.
Claim(s) 16-20 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Hajaj et al., US PG pub. 20220334501 A1;In view of Jung et al., US PG pub. 20210116803 A1.
Re: Independent Claim 16, Hajaj discloses a semiconductor substrate (12, fig. 1a) including an in-cell region and a scribe lane (¶0005; image an overlay target located in the scribe lines of the semiconductor substrate (the lines separating adjacent dies)) defining the in-cell region;
a first overlay pattern (330, 332, 334, 336, 338, 340, 342, and 344, fig. 3c) on the semiconductor substrate (12, fig. 1a); and
a second overlay pattern (306, 308, 310, 312, 314, 316, 318, and 320, fig. 3b) surrounded by the first overlay pattern (330, 332, 334, 336, 338, 340, 342, and 344, fig. 3c), wherein the first overlay pattern (330, 332, 334, 336, 338, 340, 342, and 344, fig. 3c) includes a plurality of lower marks (38, fig. 1a-1b) and a plurality of upper marks (40, fig. 1a-1b) that are at different vertical levels,
at least one of the plurality of lower marks (38, fig. 1a-1b) and at least one of the plurality of upper marks (40, fig. 1a-1b) overlap each other in a vertical direction,
a pitch (¶0057) of each of the plurality of lower marks (38, fig. 1a-1b) is different from a pitch (¶0057) of each of the plurality of upper marks (40, fig. 1a-1b), Hajaj further discloses in paragraph [0040] first layer 38 may be a process layer, and second layer 40 may be a resist layer, which is deposited over the process layer. Alternatively both of layers 38 and 40 may be process layers. In order to measure the overlay error between the patterns in layer 40 and the patterns in underlying layer 38 on substrate 12, overlay targets having a first and second sub-target suited for the two fields of view, as shown in the figures that follow, have been formed in the photolithographic process in layers 38 and 40 and in paragraph [0043] teaches measuring the overlay error between the patterns in layer 40 and the patterns in underlying layer 38 on substrate 12 using OPT1, controller 18 commands motion assembly 20 to bring the substrate under objective lens 22, so that the central part of an overlay target is in the field of view FOV1 of OPT1 and so that the combined optics of objective lens 22 and lens 26 image the substrate onto sensor 28, i.e., the substrate and the sensor are located at optical conjugate planes.
Hajaj is silent regarding: the first overlay pattern (330, 332, 334, 336, 338, 340, 342, and 344, fig. 3c) comprises an after development inspection (ADI) overlay pattern, and
the second overlay pattern (306, 308, 310, 312, 314, 316, 318, and 320, fig. 3b) comprises an after cleaning inspection (ACI) overlay pattern.
Jung teaches the use of after development inspection (ADI) overlay pattern and after cleaning inspection (ACI) overlay pattern (¶0019 and ¶0021).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include the combined ADI and ACI integration overlay pattern since by comparing the overlay measured at ADI vs the overlay measure at ACI on the same wafer can isolate how much offset etch step itself introduces. This can build an etch-bias correction and apply as feedforward or feedback term in future exposures such that the ADI measurements become a more reliable predictor over time.
Re: Claim 17, Hajaj and Jung discloses all the limitations of claim 16 on which this claim depends. Hajaj further discloses: wherein the first overlay pattern (330, 332, 334, 336, 338, 340, 342, and 344, fig. 3c) comprises a first line-and-space pattern (336, fig. 3c) extending in a first horizontal direction and a second line-and-space pattern (334, fig. 3c) extending in a second horizontal direction, and the second overlay pattern (306, 308, 310, 312, 314, 316, 318, and 320, fig. 3b) includes a third line-and-space pattern (344, fig. 3c) extending in the first horizontal direction and a fourth line-and-space pattern (342, fig. 3c) extending in the second horizontal direction.
Re: Claim 18, Hajaj and Jung discloses all the limitations of claim 17 on which this claim depends. Hajaj is silent regarding: wherein a length of each of the first and second line-and-space patterns (334 and 336, fig. 3c) is in a range from about 5 micrometers to about 35 micrometers, and a length of each of the third and fourth line-and-space patterns is in a range from about 3 micrometers to about 20 micrometers.
However, thickness range it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention because, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 105 USPQ 223, 235 (CCPA 1955). Furthermore, the specification contains no disclosure of either the critical nature of the claimed dimensions of any unexpected results arising therefrom. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2sd 1934, 1936 (Fed. Cir. 1990).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the system of Hajaj to have a smaller refine range of overlay marks since modification would have only involved a mere change in working range which involves only routine skill in the art one would have been motivated to make such modification to make those layer to have a thinner thickness to achieve the predictable result of miniaturization the overlay marks thereby improve by increase the usable area of the device.
Re: Claim 19, Hajaj and Jung discloses all the limitations of claim 16 on which this claim depends. Hajaj further discloses: wherein the first overlay pattern (330, 332, 334, 336, 338, 340, 342, and 344, fig. 3c) and the second overlay pattern (306, 308, 310, 312, 314, 316, 318, and 320, fig. 3b) correspond to one overlay pattern group (fig. 3a), and the overlay pattern group (fig. 3a) is on the in-cell region or the scribe lane (¶0005; image an overlay target located in the scribe lines of the semiconductor substrate (the lines separating adjacent dies)).
Re: Claim 20, Hajaj and Jung discloses all the limitations of claim 16 on which this claim depends. Hajaj further discloses: wherein a horizontal area of the first overlay pattern (330, 332, 334, 336, 338, 340, 342, and 344, fig. 3c) is greater than a horizontal area of the second overlay pattern (306, 308, 310, 312, 314, 316, 318, and 320, fig. 3b).
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
* (“Blanton et al., US Patent 12717246 B2”) Discloses a semiconductor die with overlay marks, electronic devices that include semiconductor dies with overlay marks, and methods of measuring overlay. In one embodiment, a semiconductor die includes multiple overlay marks, including a first overlay mark and a second overlay mark. The first overlay mark is at a first position on the semiconductor die and includes a first set of patterns with a first orientation. The second overlay mark is at a second position on the semiconductor die and includes a second set of patterns with a second orientation. The first position of the first mark and the second position of the second mark are non-overlapping. In addition, the first orientation of the patterns in the first mark is substantially orthogonal to the second orientation of the patterns in the second mark.
* (“Sezginer et al., US PG pub. 20050012928 A1”) discloses a method for measuring overlay in a sample includes obtaining an image of an overlay target that includes a series of grating stacks each having an upper and lower grating, each grating stack having a unique offset between its upper and lower grating. The image is obtained with a set of illumination and collection optics where the numerical aperture of the collection optics is larger than the numerical aperture of the illumination optics and with the numerical apertures of the illumination and collection optics are selected so that the unit cells of gratings are not resolved, the grating stacks are resolved and they appear to have a uniform color within the image of the overlay target.
* (“Adel et al., US PG pub. 20160047744 A1”) discloses a scatterometry mark for determining an overlay error, critical dimension, or profile of the mark. The mark includes a first plurality of periodic structures on a first layer, a second plurality of periodic structures on a second layer, and a third plurality of periodic structures on a third layer that is underneath the first and second layer. The third periodic structures are perpendicular to the first and second structures, and the third periodic structures have one or more characteristics so as to result in a plurality of lower structures beneath the third periodic structures being screened from significantly affecting at least part of a spectrum of a plurality of scattered signals detected from the first and second periodic structures for determining an overlay error, critical dimension, or profile of the first and second periodic structures or at least one of such detected scattered signals.
* (“Yang et al., US Patent 7046361 B1”) discloses alignment system for aligning two elements includes an alignment target with periodic patterns on each element. The alignment target includes two locations, at least one of which has a designed in offset. If desired, both locations may have designed in offsets of the same magnitude but in opposite directions. The diffraction patterns produced at the two locations are compared. If the difference between the patterns is at a minimum, the elements are properly aligned. When an alignment error is introduced, however, the calculated difference can be used to determine the error. In another embodiment, bands in the moire fringes from the different locations may be compared to determine the alignment error. The two elements may then be moved relative to each other to minimize the alignment error. Thus, the alignment target may advantageously be used in any alignment system, such as an exposure tool.
* (“Oh et al., US Patent 9846359 B1”) discloses a first grating and a second grating, disposed in a region of vertical overlap of the first and second gratings on different levels, respectively, having substantially the same pitch, and inclined with respect to each other, such that a bias value between the first and second gratings is changed along a length direction of the first and second gratings, using a lithography process. A method may include emitting a beam to the first and second gratings; and obtaining trend information associated with a diffracted beam from an image pattern of a beam from the first and second gratings, using the emitted beam, in which the trend information may concern changes in the intensity of the diffracted beam according to the bias value. An overlay error in at least one grating may be determined based on the trend information and an intensity of a diffracted beam.
* (“Park et al., US Patent 9857678 B1”) discloses a method of controlling distortion of an exposure process is provided. The method includes aligning an exposure mask with a wafer, forming a first test pattern on the wafer by performing a first exposure with the exposure mask and a first illumination system, forming a photoresist layer on an entire surface of the wafer including the first test pattern, performing a second exposure with the exposure mask and a second illumination system to form a second test pattern overlapping with the first test pattern, extracting a distortion value between the first test pattern and the second test pattern, and correcting the exposure mask or fabricating a corrected exposure mask using the distortion value.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST).
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/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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