DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Jones et al (US 20250086124, Jones) in view of Stewart et al (US 7421532, Stewart).
As to claim 12, Jones discloses a device (fig. 1) comprising:
at least a first computerized peer (processing elements 110);
at least a first direct mapping address (DMA) endpoint (storage 300) communicatively coupling the first computerized peer to at least one Peripheral Computer Interconnect Express (PCle) fabric (par. 52), the DMA endpoint comprising at least one host side network interface (interface 104) and at least one fabric side network interface (interface to 116) with at least one DMA engine therebetween (fig. 3, DMA engine 314).
Jones does not disclose the DMA endpoint being configured for switching based on PCIe memory addresses associated with destination endpoints converted from network addresses instead of switching based on respective networking addresses of destination endpoints. In the same field of art (data transferring), Stewart discloses a switching environment 100 includes a switch 110 and a number of end points 120a, 120b, 120c, 120d in a point-to-point communications network (col 2 ln 1-5). In one embodiment, Stewart discloses the switch switches based on PCIe memory addresses (col 7 ln 1-5 “second memory address domain”) associated with destination endpoints converted from network addresses (col 6 ln 65-67 “destination addresses”) instead of switching based on respective networking addresses of destination endpoints (col 4 ln 33-38). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Jones and Stewart, by configuring the DMA endpoint for switching based on PCIe memory addresses associated with destination endpoints converted from network addresses instead of switching based on respective networking addresses of destination endpoints. The motivation is to improve the compatibility of the system (col 1 ln 30-45).
As to claim 13, Jones/Stewart discloses the device of Claim 12, wherein at least one of the network interfaces comprises an ethernet style interface (Jones, par. 43 “over Ethernet”).
As to claim 14, Jones/Stewart discloses the device of Claim 12, wherein at least one of the network interfaces comprises a basic address register (BAR) as a window into the endpoint (Jones, par. 69).
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Jones in view of Stewart and further in view of Sankaran et al (US 20200004703, Sankaran).
As to claim 15, Jones/Stewart discloses the device of Claim 14, but does not disclose wherein the BAR comprises a BAR0. In the same field of art (data transferring), Sankaran discloses systems include a controller and a command queue to buffer incoming write requests into the device (abstract). In one embodiment, Sankaran further discloses a BAR comprises a BAR0 (par. 34). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Jones/Stewart and Sankaran, by comprising a BAR0. The motivation is to improve the performance of the system at lower energy (par. 2).
As to claim 16, Jones/Stewart/Sankaran discloses the device of Claim 14, wherein the BAR comprises a BAR2 (Sankaran, par. 44).
As to claim 17, Jones/Stewart/Sankaran discloses the device of Claim 14, wherein the BAR comprises a BAR4 (Sankaran, par. 47).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Jones in view of Stewart and further in view of et al Schmisseur et al (US 20200322287, Connor).
As to claim 18, Jones/Stewart discloses the device of Claim 12, but does not disclose wherein the endpoint comprises at least one data structure in hardware that correlates media access code (MAC) addresses to respective PCle memory windows. In the same field of art (data transferring), Schmisseur discloses a switch device coupled to the two or more physical servers (abstract). In one embodiment, Schmisseur discloses wherein an endpoint comprises at least one data structure in hardware that correlates media access code (MAC) addresses to respective PCle memory windows (par. 70). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Jones/Stewart and Schmisseur, by comprising at least one data structure in hardware that correlates media access code (MAC) addresses to respective PCle memory windows. The motivation is to improve the performance of the system (par. 2).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Jones in view of Stewart and further in view of Singh et al (US 20160034415, Singh).
As to claim 19, Jones/Stewart discloses the device of Claim 18, but does not disclose wherein multiple hosts can write to one PCIe memory window with writes queued in at least one first in first out (FIFO) buffer. In the same field of art (data transferring), Singh discloses a method providing a fixed QoS to multiple hosts accessing a PCIe based NAND storage device via PCIe functions (par. 8). In one embodiment, Singh discloses the method includes multiple hosts (fig. 2 host 202, 208) that can write to one PCIe memory window with writes queued in at least one first in first out (FIFO) buffer (par. 34 “queues the command”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Jones/Stewart and Singh, by comprising multiple hosts which can write to one PCIe memory window with writes queued in at least one first in first out (FIFO) buffer. The motivation is to improve the reliability of the system (par. 6).
Allowable Subject Matter
Claims 1-11 are allowed.
The following is an examiner’s statement of reasons for allowance:
The primary reason for allowance of claims 1 and 7 in the instant application is the limitations “for a message to be sent from a transmitting peer to a destination peer, converting a network ID in the message to a corresponding destination window segment address using the mapping; writing the message to the corresponding destination window segment address; at the destination peer, placing the message from the corresponding destination window segment address into a receiving first in first out (FIFO) storage for further processing” and the limitations “the endpoint of the destination peer comprising at least one receive buffer queue (RXQ), at least one segmented memory window in BAR, and at least one DMA engine configured for controlling messages through the endpoint; wherein the DMA engine of the endpoint of the transmitting peer is configured to convert a destination peer address to a destination window segment address using the data structure stored in hardware to write at least a first message to the destination window segment address through the PCIe fabric”, in combination with other steps/elements in the claims. The prior art of record including the disclosures of Jones and Stewart neither anticipates nor renders obvious the above limitation. Because claims 2-6, and 8-11 depend directly or indirectly on either one of claims 1 and 7, these claims are considered allowable for at least the same reasons noted above.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/D.P/Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184