DETAILED ACTION
This action is responsive to the following communication: the response filed 7/13/26. The changes and remarks disclosed therein have been considered.
Claim(s) status: 1-20 pending.
Claim Objections
The claim(s) is/are objected to because of the following informalities:
Claim 19: it appears that “send a read command to the nonvolatile memory device,” in line(s) 8-9 is repeated.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, 9-16, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al. (US 2016/0180898 “Hwang”) in view of Jeter et al. (US 2016/0209866 “Jeter”).
Regarding claim 1, Hwang discloses a storage device comprising:
a nonvolatile memory device (200; fig. 1) including a plurality of memory blocks (i.e. coomprsing word lines WL0 through WL63 and bit lines BL0 through BLn of array 220; fig. 2); and
a controller (100; fig. 1) electrically coupled with the nonvolatile memory device (200),
wherein the controller (100) is configured to send (S110, S120; fig. 4) first data bits (PDATA; fig. 4), a first data strobe signal (PDQS; fig. 4), and a write command (PP_CMD; fig. 4) to the nonvolatile memory device (200),
the controller (140) is configured to subsequently send (S130; fig. 4) a read command (PR_CMD; fig. 4) to the nonvolatile memory device (200),
the nonvolatile memory device (200) is configured to send (S140; fig. 4) the first data bits (the first data bits PDATA is sent as RDATA; fig. 4) and the first data strobe signal (the first data strobe signal PDQS is sent as RDQS; fig. 4) to the controller (100) in response to the read command (PR_CMD),
the controller (100) is configured to (i.e. shift) a delay of the first data strobe signal (a phase shift block shifts a delay, i.e. lower frequency, of the first data strobe signal to generate L_RDATA; fig. 3 [0066+]) to determine (S160; fig. 4) pass or fail of the first data bits (pass/fail is based on comparing S160 the first data bits with L_RDATA; fig. 4), and
the controller is configured to adjust delays (i.e. in a read training operation [0070]) of the first data bits to align the first data bits with the first data strobe signal (fig. 6) based on a determination of the pass or the fail (based on the pass/fail; fig. 4).
Hwang does not expressly disclose sweep a delay.
Jeter discloses sweep a delay (sweeping data strobe signal at delay points to perform calibrations; fig. 2).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Hwang is modifiable as taught by Jeter for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0006 of Jeter), which is common and well known in the prior art to secure the integrity of data storage.
Regarding claim 2, Jeter discloses the storage device of claim 1, wherein the controller is configured to input the first data bits (DQ(Write); fig. 1) along with the first data strobe signal (WrDQS; fig. 1) having a first delay (an applied delay to WrDQS; para 0016), and read second data bits (DQ(Read); fig. 1) along with a second data strobe signal (RdDQS; fig. 1) from the nonvolatile memory device.
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Hwang is modifiable as taught by Jeter for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0006 of Jeter), which is common and well known in the prior art to secure the integrity of data storage.
Regarding claim 3, Jeter discloses the storage device of claim 2, wherein the first delay is more advanced than a previous delay of the first data strobe signal used in a write operation (each point of a calibration procedure is a write then read operation; para 0022, further, applying a write calibration procedure for a write operation, the first delay of WrDQS can be any point in the calibration that is more advanced toward a lower/upper end than a previous delay of any previous point; fig. 2).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Hwang is modifiable as taught by Jeter for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0006 of Jeter), which is common and well known in the prior art to secure the integrity of data storage.
Regarding claim 4, Jeter discloses the storage device of claim 2, wherein the first delay is more delayed than a previous delay of the first data strobe signal used in a write operation (each point of a calibration procedure is a write then read operation; para 0022, further, applying a write calibration procedure for a write operation, the first delay of WrDQS can be any point in the calibration that is more/less delayed toward a lower/upper end than a previous delay of any previous point; fig. 2).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Hwang is modifiable as taught by Jeter for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0006 of Jeter), which is common and well known in the prior art to secure the integrity of data storage.
Regarding claim 5, Jeter discloses the storage device of claim 2, wherein the controller is configured to input the first data bits along with the first data strobe signal having a second delay (any point in a calibration procedure after the first delay represents a second delay; fig. 2), and read second data bits (DQ(Read); fig. 1) along with the second data strobe signal (RdDQS; fig. 1) from the nonvolatile memory device.
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Hwang is modifiable as taught by Jeter for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0006 of Jeter), which is common and well known in the prior art to secure the integrity of data storage.
Regarding claim 6, Jeter discloses the storage device of claim 5, wherein the second delay is more advanced than a previous delay of the first data strobe signal used in a write operation (each point of the calibration procedure is a write then read operation; para 0022, further, applying a write calibration procedure for a write operation, the second delay of WrDQS can be any point in the calibration that is more advanced toward a lower/upper end than a previous delay of any previous point; fig. 2).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Hwang is modifiable as taught by Jeter for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0006 of Jeter), which is common and well known in the prior art to secure the integrity of data storage.
Regarding claim 7, Jeter discloses the storage device of claim 5, wherein the second delay is more delayed than a previous delay of the first data strobe signal used in a write operation (each point of the calibration procedure is a write then read operation; para 0022, further, applying a write calibration procedure for a write operation, the second delay of WrDQS can be any point in the calibration that is more/less delayed toward a lower/upper end than a previous delay of any previous point; fig. 2).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Hwang is modifiable as taught by Jeter for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0006 of Jeter), which is common and well known in the prior art to secure the integrity of data storage.
Regarding claim 9, Jeter discloses the storage device of claim 1, wherein the controller is configured to sweep the delay of the first data strobe signal at least twice (fig. 2).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Hwang is modifiable as taught by Jeter for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0006 of Jeter), which is common and well known in the prior art to secure the integrity of data storage.
Regarding claim 10, Hwang discloses a method of operating a storage device including a memory device and a controller, the method comprising:
sending (S110, S120; fig. 4), by the controller (100; fig. 1), first data bits (PDATA; fig. 4), a first data strobe signal (PDQS; fig. 4), and a write command (PP_CMD; fig. 4) to the nonvolatile memory device (200);
subsequently sending (S130; fig. 4), by the controller (100), a read command (PR_CMD; fig. 4) to the nonvolatile memory device (200), while (i.e. shift) a delay of the first data strobe signal (a phase shift block shifts a delay, i.e. lower frequency, of the first data strobe signal to generate L_RDATA; fig. 3 [0066+]) to determine (S160; fig. 4) pass or fail of the first data bits (pass/fail is based on comparing S160 the first data bits with L_RDATA; fig. 4);
receiving, by the controller (100), the first data bits (the first data bits PDATA received as RDATA; fig. 4) from the nonvolatile memory device (200) and the first data strobe signal (the first data strobe signal PDQS received as RDQS; fig. 4) in response to the read command (PR_CMD); and
adjusting, by the controller (100), delays (i.e. in a read training operation [0070]) of the first data bits to align the first data bits with the first data strobe signal (fig. 6) based on a determination of the pass or the fail (based on the pass/fail; fig. 4).
Hwang does not expressly disclose sweeping a delay.
Jeter discloses sweep a delay (sweeping data strobe signal at delay points to perform calibrations; fig. 2).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Hwang is modifiable as taught by Jeter for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0006 of Jeter), which is common and well known in the prior art to secure the integrity of data storage.
Regarding claim 11, Jeter discloses the method of claim 10, wherein the sending comprises: inputting the first data bits (DQ(Write); fig. 1) along with the first data strobe signal (WrDQS; fig. 1) having a first delay (an applied delay to WrDQS; para 0016), and reading second data bits (RdDQS; fig. 1) along with a second data strobe signal (RdDQS; fig. 1) from the nonvolatile memory device.
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Hwang is modifiable as taught by Jeter for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0006 of Jeter), which is common and well known in the prior art to secure the integrity of data storage.
Regarding claim 12, Jeter discloses the method of claim 11, wherein the first delay is more advanced than a previous delay of the first data strobe signal used in a write operation (each point of a calibration procedure is a write then read operation; para 0022, further, applying a write calibration procedure for a write operation, the first delay of WrDQS can be any point in the calibration that is more advanced toward a lower/upper end than a previous delay of any previous point; fig. 2).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Hwang is modifiable as taught by Jeter for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0006 of Jeter), which is common and well known in the prior art to secure the integrity of data storage.
Regarding claim 13, Jeter discloses the method of claim 11, wherein the first delay is more delayed than a previous delay of the first data strobe signal used in a write operation (each point of a calibration procedure is a write then read operation; para 0022, further, applying a write calibration procedure for a write operation, the first delay of WrDQS can be any point in the calibration that is more/less delayed toward a lower/upper end than a previous delay of any previous point; fig. 2).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Hwang is modifiable as taught by Jeter for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0006 of Jeter), which is common and well known in the prior art to secure the integrity of data storage.
Regarding claim 14, Jeter discloses the method of claim 10, wherein the sending further comprises: inputting the first data bits along with the first data strobe signal having a second delay (any point in a calibration procedure after the first delay represents a second delay; fig. 2); and reading second data bits (DQ(Read); fig. 1) along with a second data strobe signal (RdDQS; fig. 1) from the nonvolatile memory device.
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Hwang is modifiable as taught by Jeter for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0006 of Jeter), which is common and well known in the prior art to secure the integrity of data storage.
Regarding claim 15, Jeter discloses the method of claim 14, wherein the second delay is more advanced than a previous delay of the first data strobe signal used in a write operation (each point of the calibration procedure is a write then read operation; para 0022, further, applying a write calibration procedure for a write operation, the second delay of WrDQS can be any point in the calibration that is more advanced toward a lower/upper end than a previous delay of any previous point; fig. 2).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Hwang is modifiable as taught by Jeter for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0006 of Jeter), which is common and well known in the prior art to secure the integrity of data storage.
Regarding claim 16, Jeter discloses the method of claim 14, wherein the second delay is more delayed than a previous delay of the first data strobe signal used in a write operation (each point of the calibration procedure is a write then read operation; para 0022, further, applying a write calibration procedure for a write operation, the second delay of WrDQS can be any point in the calibration that is more/less delayed toward a lower/upper end than a previous delay of any previous point; fig. 2).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Hwang is modifiable as taught by Jeter for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0006 of Jeter), which is common and well known in the prior art to secure the integrity of data storage.
Regarding claim 18, Jeter discloses the method of claim 10, wherein the inputting comprises: sweeping the delay of first data strobe signal at least twice (fig. 2).
Claim(s) 8, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al. (US 2016/0180898 “Hwang”) in view of Jeter et al. (US 2016/0209866 “Jeter”), further in view of Stott et al. (US 2018/0082725 “Stott”).
Regarding claim 8, Hwang does not expressly disclose the storage device of claim 2, wherein the nonvolatile memory device is configured to receive a read enable signal from the controller and output the second data strobe signal to the controller, and the second data strobe signal is delayed from the read enable signal.
Jeter discloses wherein the nonvolatile memory device is configured to receive a read enable signal (para 0015) from the controller and output the second data strobe signal (fig. 1).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Hwang is modifiable as taught by Jeter for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0006 of Jeter), which is common and well known in the prior art to secure the integrity of data storage.
Stott discloses output the second data strobe signal to the controller (fig. 1B), and the second data strobe signal (152-2; fig. 1B) is delayed from the read enable signal (dynamically adjusting a timing offset between the enable signal and the data strobe signal; para 0034).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Hwang is further modifiable as taught by Stott for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0036 of Stott), which is common and well known in the prior art to secure the integrity of data storage.
Regarding claim 17, Hwang does not expressly disclose the method of claim 11, further comprising: receiving, by the nonvolatile memory device, a read enable signal from the controller; and generating the second data strobe signal by delaying the read enable signal.
Jeter discloses receiving, by the nonvolatile memory device, a read enable signal from the controller (para 0015); and generating the second data strobe signal (fig. 1).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Hwang is modifiable as taught by Jeter for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0006 of Jeter), which is common and well known in the prior art to secure the integrity of data storage.
Stott discloses by delaying the read enable signal (dynamically adjusting a timing offset between the enable signal and the data strobe signal; para 0034).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Hwang is further modifiable as taught by Stott for the purpose of facilitating data accessing schemes by calibrating propagation of data with an optimized clock (para 0036 of Stott), which is common and well known in the prior art to secure the integrity of data storage.
Allowable Subject Matter
Claim(s) 19-20 are allowed.
The following is an examiner’s statement of reasons for allowance: the prior art made of record and not relied upon is considered pertinent to applicant’s disclosure does not teach or suggest the claimed invention having the following limitation, in combination with the remaining claimed limitations.
With respect to independent claim 19 (and all dependent claim(s) therefrom), the prior art fails to teach or suggest the claimed limitations, namely read the first data bits along with a second data strobe signal from the nonvolatile memory device in response to the first read command, and determine pass or fail of the first data bits, and subsequently send a second read command to the nonvolatile memory device, read the first data bits along with the second data strobe signal from the nonvolatile memory device in response to the second read command, and determine the pass or the fail of the first data bits.
The allowable claims are supported in at least fig. 4 of the instant application.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to the pending claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/UYEN SMET/
Primary Examiner, Art Unit 2824______
