Prosecution Insights
Last updated: August 17, 2026
Application No. 18/630,387

SECURE, SCALABLE DOORBELL MECHANISM BETWEEN PEERS IN A PCIE FABRIC

Non-Final OA §102
Filed
Apr 09, 2024
Examiner
UNELUS, ERNEST
Art Unit
2181
Tech Center
2100 — Computer Architecture & Software
Assignee
Sony Group Corporation
OA Round
3 (Non-Final)
77%
Grant Probability
Favorable
3-4
OA Rounds
9m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
423 granted / 548 resolved
+22.2% vs TC avg
Strong +39% interview lift
Without
With
+38.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
20 currently pending
Career history
576
Total Applications
across all art units

Statute-Specific Performance

§101
5.6%
-34.4% vs TC avg
§103
40.8%
+0.8% vs TC avg
§102
46.1%
+6.1% vs TC avg
§112
2.5%
-37.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 548 resolved cases

Office Action

§102
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . RESPONSE TO AMENDMENT Claim rejections based on prior art A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/28/2026 has been entered. Applicant’s arguments filed on 04/28/2026 with respect to claims 1-6 and 11-24 have been fully considered but are moot in view of newly cited reference. OBJECTIONS TO THE CLAIMS Claims 6 and 19 are objected to as being indefinite for failing to particularly point out and distinctly claim the subject matter which applicant regards as the invention. As per claim 6, line 3 discloses the phrase ‘the host’. There is insufficient antecedent basis for this limitation in the claim. ‘A host’ was not previously disclosed. Claim 19 has the same problem. Correction is needed. REJECTIONS BASED ON PRIOR ART Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 1. Claims 1-6 and 11-24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xiong et al. (US pub. # 2016/0062944), hereinafter, “Xiong”. At the outset, Applicant is reminded that claims subject to examination will be given their broadest reasonable interpretation in light of the supporting disclosure. In re Morris, 127 F.3d 1048, 1054-55, 44 USPQ2d 1023,1027-28 (Fed. Cir. 1997). With this in mind, the discussion will focus on how the terms and relationships between the terms in the claims are met by the references. 2. As per claim 1, Xiong discloses a method comprising: identifying a doorbell event (source data, send data 320, as disclose in paragraphs 0029 and 0030) in a transmitting peer (local node 300 of fig. 3a; see paragraph 0029, which discloses “examples of read and write operations using tagged messages are illustrated in FIGS. 3a and 3b. As shown in the tagged message write operation of FIG. 3a, a block of source data is transferred from a local node 300 to a remote node 302 via an interconnect 304. In further detail, local node 300 includes a source buffer 306 in which the source data is stored, and an RMA write module 308, while remote node 302 includes an AM write request handler 310, an RMA progress module 312, and an RMA address space 314”); in response to identifying the doorbell event (send data 320, as discloses in paragraph 0029) (see paragraph 0019, which discloses “an RMA write of a block of source data 116 from source buffer 104 to RMA address space 112 proceeds as follows. Source data 116 is read from source buffer 104 via RMA write module 106, which generates an AM write request 118 that is sent over interconnect 114 to AM handler 110”), generating a zero byte write (ZBW) (AM write request 316, as disclose in paragraph 0030 and fig. 3a) having only a destination address and zero bytes of payload data (see paragraph 0030, which discloses “the tagged message write operation proceeds as follows. The RMA write comprises an AM write request 316 followed by a send operation 318. AM write request 316 carries only the information about the remote address range, without any data payload; rather, the send data 320 is transferred via the subsequent send operation 318”); sending the ZBW from the transmitting peer to a destination peer (remote node 302) (see paragraph 0030); and identifying, at the destination peer, a notification based on the ZBW(see paragraph 0030). 3. As per claim 2, Xiong discloses “The method of Claim 1” [See rejection to claim 1 above], comprising: identifying a doorbell register write in the transmitting peer, the write being addressed to a memory window; and generating the ZBW to the destination peer window (see paragraphs 0019 and 0030). 4. As per claims 3 and 13, Xiong discloses comprising sending the ZBW over a peripheral computer interconnect express (PCIe) fabric (see paragraph 0039). 5. As per claims 4 and 17, Xiong discloses, comprising associating the doorbell event with a unique, one-to-one or many-to-one mapping of local system interrupts (see paragraphs 0019 and 0030). 6. As per claims 5 and 18, Xiong discloses, comprising: mapping a memory window at the destination peer receiving the ZBW to a local doorbell event; and posting the doorbell event to a doorbell counter (see paragraphs 0019 and 0030). 7. As per claims 6 and 19, Xiong discloses, comprising: responsive to determining that the doorbell event is enabled to interrupt the host, triggering a local host interrupt (see paragraphs 0019 and 0030). 8. As per claim 11, Xiong discloses an apparatus, comprising: at least one transmitting peer (local node 300 of fig. 3a; see paragraph 0029, which discloses “examples of read and write operations using tagged messages are illustrated in FIGS. 3a and 3b. As shown in the tagged message write operation of FIG. 3a, a block of source data is transferred from a local node 300 to a remote node 302 via an interconnect 304. In further detail, local node 300 includes a source buffer 306 in which the source data is stored, and an RMA write module 308, while remote node 302 includes an AM write request handler 310, an RMA progress module 312, and an RMA address space 314”); at least one destination peer (remote node 302) (see paragraph 0030); at least one peripheral computer interconnect express (PCIe) fabric (interconnect 304; see paragraph 0039) communicatively coupling the transmitting peer to the destination peer (see fig. 3a); the transmitting peer comprising circuitry configured for: identifying a doorbell event (source data, send data 320, as disclose in paragraphs 0029 and 0030); in response to identifying the doorbell event (send data 320, as discloses in paragraph 0029) (see paragraph 0019, which discloses “an RMA write of a block of source data 116 from source buffer 104 to RMA address space 112 proceeds as follows. Source data 116 is read from source buffer 104 via RMA write module 106, which generates an AM write request 118 that is sent over interconnect 114 to AM handler 110”), generating a zero byte write (ZBW) (AM write request 316, as disclose in paragraph 0030 and fig. 3a) having only a destination address and zero bytes of payload data (see paragraph 0030, which discloses “the tagged message write operation proceeds as follows. The RMA write comprises an AM write request 316 followed by a send operation 318. AM write request 316 carries only the information about the remote address range, without any data payload; rather, the send data 320 is transferred via the subsequent send operation 318”); and sending the ZBW from the transmitting peer to the destination peer (see paragraph 0030). 9. As per claim 12, Xiong discloses wherein the destination peer comprises circuitry configured for: identifying a notification based on the ZBW (see paragraphs 0019 and 0030). 10. As per claim 14, Xiong discloses wherein the circuitry of the transmitting peer is configured for: identifying a write, the write being addressed to a memory window; and generating a doorbell event for the memory window (see paragraphs 0019 and 0030). 11. As per claim 15, Xiong discloses wherein the circuitry of the transmitting peer is configured for: responsive to writing the doorbell event to a doorbell register, mapping a destination ID associated with the doorbell event to a memory window of the destination peer, the memory window being shared with the transmitting peer; and sending the doorbell event to the memory window of the destination peer (see paragraphs 0019 and 0026). 12. As per claim 16, Xiong discloses wherein the circuitry of the transmitting peer is configured for: sending the doorbell event to the destination peer as a regular PCIe write transaction (see paragraphs 0030 and 0039). 13. As per claim 20, Xiong discloses a network comprising: a transmitting host (local node 300 of figs. 3a and 5; see paragraph 0029, which discloses “examples of read and write operations using tagged messages are illustrated in FIGS. 3a and 3b. As shown in the tagged message write operation of FIG. 3a, a block of source data is transferred from a local node 300 to a remote node 302 via an interconnect 304. In further detail, local node 300 includes a source buffer 306 in which the source data is stored, and an RMA write module 308, while remote node 302 includes an AM write request handler 310, an RMA progress module 312, and an RMA address space 314”) coupled to a peripheral computer interconnect express (PCIe) fabric over a first PCIe link (a first link of optical link 560 of fig. 5) and comprising a first messaging direct memory access endpoint (see paragraph 0040), the transmitting host comprising: a doorbell register (source buffer 306); and a first processor (see fig. 5) to transmit a zero byte write (ZBW) having only a destination address and zero bytes of payload data (see paragraph 0030, which discloses “the tagged message write operation proceeds as follows. The RMA write comprises an AM write request 316 followed by a send operation 318. AM write request 316 carries only the information about the remote address range, without any data payload; rather, the send data 320 is transferred via the subsequent send operation 318”); a destination host (remote node 302) coupled to the PCIe fabric over a second PCIe link (a second link of optical link 560 of fig. 5) and comprising a second messaging direct memory access endpoint (see figs. 3a, 5 and paragraph 0040), the destination host comprising: a memory window to receive the ZBW (see paragraphs 0019 and 0030); and a doorbell counter to maintain a list of received ZBWs (see paragraph 0024); and a management host (a second remote node 302) coupled to the PCIe fabric (see fig. 5). 14. As per claim 21, Xiong discloses wherein the management host manages the transfer of the ZBW from the first processor of the transmitting host to the memory window of the destination host (see fig. 5 and paragraphs 0019 and 0030. Note, this limitation is not calling for all the hosts to be ‘coupled’ simultaneously). 15. As per claim 22, Xiong discloses wherein the first PCle link and the second PCIe link are non-transparent bridges (see fig. 5). 16. As per claim 23, Xiong discloses wherein the first PCIe link and the second PCIe link are configured by the management host (see fig. 5 and paragraphs 0019 and 0030). 17. As per claim 24, Xiong discloses wherein the first processor in the transmitting host is not capable of writing the ZBW to the memory window of the destination host (see fig. 5. Note, this claim function takes place when power is removed from the system). CLOSING COMMENTS CONCLUSION a. STATUS OF CLAIMS IN THE APPLICATION The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i): a (1) CLAIMS REJECTED IN THE APPLICATION Per the instant office action, claims 1-6 and 11-24 have received a first action on the merits and are subject of a first action non-final. b. DIRECTION OF FUTURE CORRESPONDENCES Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Ernest Unelus whose telephone number is (571) 272- 8596. The examiner can normally be reached on Monday to Friday 9:00 AM to 5:00 PM. IMPORTANT NOTE If attempts to reach the above noted Examiner by telephone are unsuccessful, the Examiner's supervisor, Mr. Idriss Alrobaye, can be reached at the following telephone number: Area Code (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PMR system, see her//pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217- 91 97 (toll-free). /Ernest Unelus/ Primary Examiner Art Unit 2181
Read full office action

Prosecution Timeline

Show 1 earlier event
Jun 17, 2025
Non-Final Rejection mailed — §102
Oct 17, 2025
Response Filed
Jan 28, 2026
Final Rejection mailed — §102
Apr 27, 2026
Applicant Interview (Telephonic)
Apr 27, 2026
Examiner Interview Summary
Apr 28, 2026
Request for Continued Examination
May 02, 2026
Response after Non-Final Action
Jul 28, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
77%
Grant Probability
99%
With Interview (+38.7%)
3y 1m (~9m remaining)
Median Time to Grant
High
PTA Risk
Based on 548 resolved cases by this examiner. Grant probability derived from career allowance rate.

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