DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This action is in response to application filed on April 9, 2024.
Drawings
3. The drawings were received on April 9, 2024. These drawings are accepted.
Claim Rejections - 35 USC § 102
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
5. Claims 1-2 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ranta et al (US 2020/0007088).
Regarding claim 1, Ranta et al discloses a circuit (i.e. circuit of Figure 4K), comprising:
a first transistor (Fig. 4K, transistor 440a) having first (Fig. 4K, source terminal of transistor 440a directly connected to source VDD) and second terminals (Fig. 4K, drain terminal of transistor 440a directly connected to transistor 420);
a first current source (Fig. 4K, current source 410) having first (Fig. 4K, terminal of transistor current source 410 directly connected to source VDD) and second terminals (Fig. 4K, terminal of current source 410 not directly connected to source VDD), the first terminal (Fig. 4K, terminal of transistor current source 410 directly connected to source VDD) of the first current source (Fig. 4K, current source 410) coupled to the first terminal (Fig. 4K, source terminal of transistor 440a directly connected to source VDD) of the first transistor (Fig. 4K, transistor 440a), and the second terminal (Fig. 4K, terminal of current source 410 not directly connected to source VDD) of the first current source (Fig. 4K, current source 410) coupled to the second terminal (Fig. 4K, drain terminal of transistor 440a directly connected to transistor 420) of the first transistor (Fig. 4K, transistor 440a) (i.e. the drain terminal of transistor 440a is coupled to the terminal of current source 410 not directly connected to source VDD via transistor 420);
a second transistor (Fig. 4K, transistor 420) having a control terminal (Fig. 4K, gate terminal of transistor 420) and first (Fig. 4K, source terminal of transistor 420 directly connected to node 430) and second terminals (Fig. 4K, drain terminal of transistor 420 directly connected to transistor 440a), the control terminal (Fig. 4K, gate terminal of transistor 420) of the second transistor (Fig. 4K, transistor 420) coupled to the second terminal (Fig. 4K, terminal of current source 410 not directly connected to source VDD) of the first current source (Fig. 4K, transistor 420), and the first terminal (Fig. 4K, source terminal of transistor 420 directly connected to node 430) of the second transistor (Fig. 4K, transistor 420) coupled to the second terminal (Fig. 4K, terminal of current source 410 not directly connected to source VDD) of the first current source (Fig. 4K, current source 410) (i.e. source terminal of transistor 420 is coupled to the terminal of current source 410 not directly connected to source VDD via transistor 415);
a third transistor (Fig. 4K, transistor 440b) having first (Fig. 4K, gate terminal of transistor 440b) and second terminals (Fig. 4K, source terminal of transistor 440b directly connected to source VDD), the first terminal (Fig. 4K, gate terminal of transistor 440b) of the third transistor (Fig. 4K, transistor 440b) coupled to the second terminal (Fig. 4K, drain terminal of transistor 420 directly connected to transistor 440a) of the second transistor (Fig. 4K, transistor 420); and
a fourth transistor (Fig. 4K, transistor 415) having first (Fig. 4K, drain terminal of transistor 415 directly connected to current source 410) and second terminals (Fig. 4K, gate terminal of transistor 415), the first terminal (Fig. 4K, drain terminal of transistor 415 directly connected to current source 410) of the fourth transistor (Fig. 4K, transistor 415) coupled to the second terminal (Fig. 4K, terminal of current source 410 not directly connected to source VDD) of the first current source (Fig. 4K, current source 410), and the second terminal (Fig. 4K, gate terminal of transistor 415) of the fourth transistor (Fig. 4K, transistor 415) coupled to the second terminal (Fig. 4K, source terminal of transistor 440b directly connected to source VDD) of the third transistor (Fig. 4K, transistor 440b) (i.e. gate terminal of transistor 415 is coupled to source terminal of transistor 440b via transistors 420 and 440a).
Regarding claim 2, Ranta et al further discloses a voltage source (Fig. 4K, source VDD) coupled to the first terminal (Fig. 4K, terminal of transistor current source 410 directly connected to source VDD) of the first current source (Fig. 4K, current source 410).
Regarding claim 7, Ranta et al further discloses wherein the first transistor (Fig. 4K, transistor 440a) has a control terminal (Fig. 4K, gate terminal of transistor 440a), the third transistor (Fig. 4K, transistor 440b) has a control terminal (Fig. 4K, gate terminal of transistor 4K), and the fourth transistor (Fig. 4K, transistor 415) has a control terminal (Fig. 4K, gate terminal of transistor 415), the circuit (i.e. circuit of Figure 4K) further comprising a controller (i.e. controller of Figure 30) having respective output terminals coupled to the control terminals of the first transistor (Fig. 4K, transistor 440a), third transistor (Fig. 4K, transistor 440b), and fourth transistor (Fig. 4K, transistor 415).
Allowable Subject Matter
6. Claims 8-20 are allowed.
7. Claims 3-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
8. The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, the prior art fails to disclose or suggest the emboldened and italicized features below:
A circuit, further comprising
a power converter having a first high-side transistor coupled to a switch node, wherein the second terminal of the third transistor is coupled to the switch node, and wherein the second terminal of the first current source is coupled to a control terminal of the first high-side transistor.
Regarding claims 4-6, the prior art fails to disclose or suggest the emboldened and italicized features below:
A circuit, further comprising:
a fifth transistor having first and second terminals, the first terminal of the fifth transistor coupled to the first terminal of the first current source;
a second current source having first and second terminals, the first terminal of the second current source coupled to the first terminal of the fifth transistor, and the second terminal of the second current source coupled to the second terminal of the fifth transistor;
a sixth transistor having a control terminal and first and second terminals, the control terminal of the sixth transistor coupled to the second terminal of the second current source, and the first terminal of the sixth transistor coupled to the second terminal of the second current source;
a seventh transistor having first and second terminals, the first terminal of the seventh transistor coupled to the second terminal of the sixth transistor; and
an eighth transistor having first and second terminals, the first terminal of the eighth transistor coupled to the second terminal of the second current source, and the second terminal of the eighth transistor coupled to the second terminal of the seventh transistor and to the second terminal of the third transistor.
Regarding claims 8-20, the prior art fails to disclose or suggest the emboldened and italicized features below:
A circuit, comprising:
a power converter comprising first and second high-side transistors arranged to form a high-side switch device coupled between a switch node and an output terminal of the power converter;
a controller configured to provide first, second, and third control signals; and
a high-side driver circuit coupled to the controller, the high-side driver circuit configured to:
provide gate control signals having first voltages based on the first control signal having a first value to cause the first and second high-side transistors to be conductive in a forward direction at a first time at a first conductive state;
provide gate control signals having second voltages based on the first control signal having a second value and second and third control signals to have the second value; and
responsive to the second and third control signals, provide, by the high-side driver circuit, the gate control signals having second voltages at the gate terminals of the first and second high-side transistors to cause the first and second high-side transistors to be conductive in the forward direction at a second time at a second conductive state, wherein the second conductive state is less conductive than the first conductive state.
Conclusion
9. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Neidorff et al (US 2019/0058394) deals with increasing efficiency of a switched mode power converter, Wu et al (US 2021/0296986) deals with a gate driver for DC-DC converters, Barrenscheen et al (US 10,855,183) deals with a method and device to operate a power switch in multiple modes, and Aslan et al (US 7,541,861) deals with matching for time multiplexed transistors.
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to GARY NASH whose telephone number is (571) 270-3349. The examiner can normally be reached on Monday-Friday 8am-4pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner‘s supervisor, Thienvu Tran can be reached on (571) 270-1276. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GARY A NASH/Primary Examiner, Art Unit 2838