DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's arguments filed on 01/05/2026 with respect to independent claim 15 regarding the new amendments to independent claim 15 have been considered but since the amendments contain new amended subject matter, which has not been examined prior, arguments regarding the new amended subject matter will not be addressed for the sake of brevity, however how the prior art reads on the amended subject matter in the claims is addressed in the rejection in the current office action found below.
Applicant’s arguments filed on 01/05/2026 for claim 2 and similar claim 20 have been fully considered but they are not persuasive.
The applicant argues on page 12, fifth paragraph and the end of page 14 to the top of page 15 “Murao fails to disclose at least "an upstream circuit block electrically connected to respective first ends of each of the plurality of capacitive elements" and "a selection circuit electrically connected to respective second ends of each of the plurality of capacitive elements".
The examiner respectfully disagrees with the applicant’s position. In the non-final rejection the examiner relied upon the light detection circuit 40 as an upstream circuit block which electrically connected to respective first ends of each of the plurality of capacitive coupling capacitance Cin elements in imaging element 15. In the non-final rejection the examiner relied upon the input transfer transistor 51 as a selection circuit electrically connected to respective second ends of each of the plurality of capacitive coupling capacitance Cin elements.
The applicant further argues on page 12, sixth paragraph “The Office Action maps Murao's Correlated Double Sampling (CDS) circuit 34 to the claimed upstream circuit block”, page 13, fourth paragraph “because Murao's CDS circuit 34 operates on "the signal levels of the second imaging signals which are output from the pixel value storage circuits 50," Murao at para. [0063], the CDS circuit 34 is structurally downstream of the pixel value storage circuits' outputs and cannot be positioned at, or electrically connected to, an "input end" of the coupling capacitance Cin capacitor within the pixel value storage circuit 501 (i.e., at an opposite end of the coupling capacitance Cin capacitor from the input transfer transistor 51”. The examiner non-final rejection did not state that the CDS circuit 34 was the upstream circuit as the applicant argues, instead the light detection circuit 40 as an upstream circuit block which electrically connected to respective first ends of each of the plurality of capacitive coupling capacitance Cin elements in imaging element 15. See the rejection below.
Dependent claims 3, 4, 16, 19, and 21 are not allowable for being dependent on independent claims 2, 15, and 20 which is not allowable for the reasons discussed above.
The examiner objections to the claim 15 have been withdrawn in view of the amendments the applicant made in response on 01/05/2025.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2 – 14, and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 – 10 and 16 of U.S. Patent No. 11,974,057 Asakura et al. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims in this application are broader than the claims in Asakura et al 11,974,057.
Regarding claim 2 Asakura et al 11,974,057 discloses of applicant’s A solid-state imaging element comprising: a plurality of capacitive elements; an upstream circuit block electrically connected to respective first ends of each of the plurality of capacitive elements, wherein the upstream circuit block outputs each of a reset level and a plurality of signal levels each corresponding to an exposure amount to the plurality of capacitive elements; a selection circuit electrically connected to respective second ends of each of the plurality of capacitive elements, wherein the selection section sequentially selectively connects and disconnects selected ones of the plurality of capacitive elements to a downstream node; and a downstream circuit that reads each of the reset level and the plurality of signal levels via the downstream node (claim 1, A solid-state imaging element comprising: a predetermined number or capacitive elements; an upstream circuit block that generates each of a predetermined reset level and a plurality of signal levels each corresponding to an exposure amount and causes the capacitive elements, different from each other, to hold the reset level and the plurality of signal levels; a selection section that sequentially performs control to connect the capacitive element in which the reset level is held among the predetermined number of capacitive elements to a predetermined downstream node, control to disconnect the predetermined number of capacitive elements from the downstream node, and control to connect the capacitive element in which any of the plurality of signal levels is held among the predetermined number of capacitive elements to the downstream node; a downstream reset transistor that initializes a level of the downstream node when the predetermined number of capacitive elements are disconnected from the downstream node; and a downstream circuit that sequentially reads each of the reset level and the plurality of signal levels via the downstream node and claim 4 the first and second capacitive elements respectively have first ends connected in common to the first upstream node).
Regarding claim 3 Asakura et al 11,974,057 discloses of applicant’s further comprising: a downstream reset transistor that initializes a level of the downstream node (claim 1, a downstream reset transistor that initializes a level of the downstream node).
Regarding claim 4 Asakura et al 11,974,057 discloses of applicant’s wherein the upstream circuit block is provided on a first chip, and the plurality of capacitive elements, the selection circuit, the downstream reset transistor, and the downstream circuit are provided on a second chip (claim 16, wherein the upstream circuit block is provided on a first chip, and the predetermined number of capacitive elements, the selection section, the downstream reset transistor, and the downstream circuit are provided on a second chip).
Regarding claim 5 Asakura et al 11,974,057 discloses of applicant’s wherein the plurality of capacitive elements include first and second capacitive elements and third and fourth capacitive elements, the upstream circuit block includes: a first upstream circuit electrically connected to respective first ends of the first and second capacitive elements, wherein the first upstream circuit outputs a first reset level and a first signal level to the first and second capacitive elements; and a second upstream circuit electrically connected to respective first ends of the third and fourth capacitive elements, wherein the second upstream circuit outputs a second reset level and a second signal level to the third and fourth capacitive elements (claim 2, wherein the predetermined number of capacitive elements include first and second capacitive elements and third and fourth capacitive elements, the upstream circuit block includes: a first upstream circuit that sequentially generates a first reset level and a first signal level and causes the first and second capacitive elements to hold the first reset level and the first signal level; and a second upstream circuit that sequentially generates a second reset level and a second signal level and causes the third and fourth capacitive elements to hold the second reset level and the second signal level, and the selection section includes: a first selection circuit that connects any of the first and second capacitive elements to the downstream node; and a second selection circuit that connects any of the third and fourth capacitive elements to the downstream node and claim 4 the third and fourth capacitive elements respectively have first ends connected in common to the second upstream node).
Regarding claim 6 Asakura et al 11,974,057 discloses of applicant’s wherein the selection circuit includes: a first selector circuit electrically connected to respective second ends of the first and second capacitive elements, wherein the first selector circuit selectively connects any of the first and second capacitive elements to the downstream node; and a second selector circuit electrically connected to respective second ends of the third and fourth capacitive elements, wherein the second selector circuit selectively connects any of the third and fourth capacitive elements to the downstream node (claim 2, wherein the predetermined number of capacitive elements include first and second capacitive elements and third and fourth capacitive elements, the upstream circuit block includes: a first upstream circuit that sequentially generates a first reset level and a first signal level and causes the first and second capacitive elements to hold the first reset level and the first signal level; and a second upstream circuit that sequentially generates a second reset level and a second signal level and causes the third and fourth capacitive elements to hold the second reset level and the second signal level, and the selection section includes: a first selection circuit that connects any of the first and second capacitive elements to the downstream node; and a second selection circuit that connects any of the third and fourth capacitive elements to the downstream node and claim 4 the third and fourth capacitive elements respectively have first ends connected in common to the second upstream node).
Regarding claim 7 Asakura et al 11,974,057 discloses of applicant’s wherein the first upstream circuit includes: a first photoelectric conversion element; a first upstream transfer transistor that transfers a charge from the first photoelectric conversion element to a first floating diffusion layer; a first reset transistor that initializes the first floating diffusion layer; and a first upstream amplification transistor that amplifies a voltage of the first floating diffusion layer, and the second upstream circuit includes: a second photoelectric conversion element; a second upstream transfer transistor that transfers a charge from the second photoelectric conversion element to a second floating diffusion layer; a second reset transistor that initializes the second floating diffusion layer; and a second upstream amplification transistor that amplifies a voltage of the second floating diffusion layer (claim 3, wherein the first upstream circuit includes: a first photoelectric conversion element; a first upstream transfer transistor that transfers a charge from the first photoelectric conversion element to a first floating diffusion layer; a first reset transistor that initializes the first floating diffusion layer; and a first upstream amplification transistor that amplifies a voltage of the first floating diffusion layer, and the second upstream circuit includes: a second photoelectric conversion element; a second upstream transfer transistor that transfers a charge from the second photoelectric conversion element to a second floating diffusion layer; a second reset transistor that initializes the second floating diffusion layer; and a second upstream amplification transistor that amplifies a voltage of the second floating diffusion layer).
Regarding claim 8 Asakura et al 11,974,057 discloses of applicant’s wherein the first upstream circuit further includes a first current source transistor connected to a first upstream node, the second upstream circuit further includes a second current source transistor connected to a second upstream node, the first upstream amplification transistor amplifies the voltage of the first floating diffusion layer and outputs the amplified voltage to the first upstream node, the second upstream amplification transistor amplifies the voltage of the second floating diffusion layer and outputs the amplified voltage to the second upstream node, the first and second capacitive elements respectively have first ends connected in common to the first upstream node and second ends connected to the first selector circuit, and the third and fourth capacitive elements respectively have first ends connected in common to the second upstream node and second ends connected to the second selector circuit (claim 4, wherein the first upstream circuit further includes a first current source transistor connected to a first upstream node, the second upstream circuit further includes a second current source transistor connected to a second upstream node, the first upstream amplification transistor amplifies the voltage of the first floating diffusion layer and outputs the amplified voltage to the first upstream node, the second upstream amplification transistor amplifies the voltage of the second floating diffusion layer and outputs the amplified voltage to the second upstream node, the first and second capacitive elements respectively have first ends connected in common to the first upstream node and second ends connected to the first selection circuit, and the third and fourth capacitive elements respectively have first ends connected in common to the second upstream node and second ends connected to the second selection circuit).
Regarding claim 9 Asakura et al 11,974,057 discloses of applicant’s wherein the first and second upstream transfer transistors transfer the charges to the first and second floating diffusion layers at a predetermined exposure start timing, and the first and second reset transistors initialize the first and second photoelectric conversion elements together with the first and second floating diffusion layers, and the first and second upstream transfer transistors transfer the charges to the first and second floating diffusion layers at a predetermined exposure end timing (claim 5, wherein the first and second upstream transfer transistors transfer the charges to the first and second floating diffusion layers at a predetermined exposure start timing, and the first and second reset transistors initialize the first and second photoelectric conversion elements together with the first and second floating diffusion layers, and the first and second upstream transfer transistors transfer the charges to the first and second floating diffusion layers at a predetermined exposure end timing).
Regarding claim 10 Asakura et al 11,974,057 discloses of applicant’s wherein the selection circuit sequentially performs control to connect one of the first and second capacitive elements to the downstream node, control to connect another of the first and second capacitive elements to the downstream node, control to connect one of the third and fourth capacitive elements to the downstream node, and control to connect another of the third and fourth capacitive elements to the downstream node (claim 6, wherein the selection section sequentially performs control to connect one of the first and second capacitive elements to the downstream node, control to connect another of the first and second capacitive elements to the downstream node, control to connect one of the third and fourth capacitive elements to the downstream node, and control to connect another of the third and fourth capacitive elements to the downstream node).
Regarding claim 11 Asakura et al 11,974,057 discloses of applicant’s wherein the selection circuit sequentially performs control to connect both one of the first and second capacitive elements and one of the third and fourth capacitive elements to the downstream node and control to connect both another of the first and second capacitive elements and another of the third and fourth capacitive elements to the downstream node in a predetermined addition mode (claim 7, wherein the selection section sequentially performs control to connect both one of the first and second capacitive elements and one of the third and fourth capacitive elements to the downstream node and control to connect both another of the first and second capacitive elements and another of the third and fourth capacitive elements to the downstream node in a predetermined addition mode).
Regarding claim 12 Asakura et al 11,974,057 discloses of applicant’s wherein the first upstream circuit further includes a first upstream selection transistor that outputs the voltage amplified by the first upstream amplification transistor to a predetermined upstream node in accordance with a predetermined first selection signal, the second upstream circuit includes: a second upstream selection transistor that outputs the voltage amplified by the second upstream amplification transistor to the upstream node in accordance with a predetermined second selection signal; and a current source transistor connected to the upstream node, the first and second capacitive elements respectively have first ends connected in common to the upstream node and second ends connected to the first selector circuit, and the third and fourth capacitive elements respectively have first ends connected in common to the upstream node and second ends connected to the second selector circuit (claim 8, wherein the first upstream circuit further includes a first upstream selection transistor that outputs the voltage amplified by the first upstream amplification transistor to a predetermined upstream node in accordance with a predetermined first selection signal, the second upstream circuit includes: a second upstream selection transistor that outputs the voltage amplified by the second upstream amplification transistor to the upstream node in accordance with a predetermined second selection signal; and a current source transistor connected to the upstream node, the first and second capacitive elements respectively have first ends connected in common to the upstream node and second ends connected to the first selection circuit, and the third and fourth capacitive elements respectively have first ends connected in common to the upstream node and second ends connected to the second selection circuit).
Regarding claim 13 Asakura et al 11,974,057 discloses of applicant’s wherein the first and second upstream selection transistors sequentially transition to a closed state immediately before a predetermined exposure end timing and after the exposure end timing, the first reset transistor initializes the first floating diffusion layer when the first upstream selection transistor is in the closed state, the second reset transistor initializes the second floating diffusion layer when the second upstream selection transistor is in the closed state, the first and second upstream selection transistors sequentially transition to the closed state immediately after the exposure end timing, and the first and second upstream transfer transistors transfer the charges at a predetermined exposure end timing (claim 9, wherein the first and second upstream selection transistors sequentially transition to a closed state immediately before a predetermined exposure end timing and after the exposure end timing, the first reset transistor initializes the first floating diffusion layer when the first upstream selection transistor is in the closed state, the second reset transistor initializes the second floating diffusion layer when the second upstream selection transistor is in the closed state, the first and second upstream selection transistors sequentially transition to the closed state immediately after the exposure end timing, and the first and second upstream transfer transistors transfer the charges at a predetermined exposure end timing).
Regarding claim 14 Asakura et al 11,974,057 discloses of applicant’s further comprising a short-circuit transistor that opens and closes a path between a first downstream node and a second downstream node, wherein the plurality of capacitive elements include first, second, third, fourth, fifth, sixth, seventh, and eighth capacitive elements, and the selection circuit includes: a first selector circuit that connects any of the first and second capacitive elements to the first downstream node; a second selector circuit that connects any of the third and fourth capacitive elements to the first downstream node; a third selector circuit that connects any of the fifth and sixth capacitive elements to the second downstream node; and a fourth selector circuit that connects any of the seventh and eighth capacitive elements to the second downstream node (claim 10, further comprising a short-circuit transistor that opens and closes a path between a first downstream node and a second downstream node, wherein the predetermined number of capacitors include first, second, third, fourth, fifth, sixth, seventh, and eighth capacitive elements, and the selection section includes: a first selection circuit that connects any of the first and second capacitive elements to the first downstream node; a second selection circuit that connects any of the third and fourth capacitive elements to the first downstream node; a third selection circuit that connects any of the fifth and sixth capacitive elements to the second downstream node; and a fourth selection circuit that connects any of the seventh and eighth capacitive elements to the second downstream node).
Regarding claim 20 Asakura et al 11,974,057 discloses of applicant’s A solid-state imaging element comprising: a plurality of photoelectric conversion elements that convert incident light into charges; an upstream amplification transistor that respectively converts the charges into a voltage; a plurality of capacitive elements, wherein a first end of each capacitive element is connected to an output of the upstream amplification transistor; a plurality of selection transistors each having a first end connected to a second end of a corresponding one of the plurality of capacitive elements and having a second end connected to a downstream node; and a downstream amplification transistor that has a gate connected to the downstream node and outputs a pixel signal (claim 20, A solid-state imaging element comprising: a first photoelectric conversion element that converts incident light into a charge; a second photoelectric conversion element that converts incident light into a charge; an upstream amplification transistor that converts the charges into voltages; a predetermined number of capacitive elements each having first end connected to as upstream node which is an output destination of the upstream amplification transistor; a predetermined number of selection transistors inserted in each of paths between each of second ends of the predetermined number of capacitive elements and a predetermined downstream node; a reset transistor having a source or a drain connected to the downstream node; and a downstream amplification transistor that has a gate connected to the downstream node and outputs a pixel signal).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 2 – 4, 15, 16, and 19 – 21 is/are rejected under 35 U.S.C. 102b as being anticipated by Murao et al US Publication No. 2018/0295303.
Regarding claim 2 Murao discloses of Fig. 1 – 36 of applicant’s a solid-state imaging element (paragraph 0089 the stacked imaging element with first and second chips in the imaging element are a solid-state imaging element) comprising: a plurality of capacitive elements (paragraph 0110 – 0011 of a circuit diagram illustrating the light detection circuit 40 and the pixel value storage circuit 501 in the imaging element 15, pixel value storage circuit 501 is obtained by adding a coupling capacitance Cin to the pixel value storage circuit 50 such that there is plurality of capacitive coupling capacitance Cin elements in the imaging element 15);
Murao further discloses of applicant’s an upstream circuit block electrically connected to respective first ends of each of the plurality of capacitive elements, wherein the upstream circuit block outputs each of a reset level and a plurality of signal levels each corresponding to an exposure amount to the plurality of capacitive elements (paragraph 0058 of a layout of the imaging element 15 there is a Correlated Double Sampling circuit (CDS) 34, (paragraph 0063) the CDS circuit 34 outputs, as pixel values, difference values between dark level values corresponding to dark level signals which are obtained when the floating diffusions in the pixel value storage circuits 50 are reset and pixel values corresponding to the signal levels of the second imaging signals which are output from the pixel value storage circuits 50. Paragraph 0110 – 0011 of a circuit diagram illustrating the light detection circuit 40 and the pixel value storage circuit 501 in the imaging element 15, pixel value storage circuit 501 is obtained by adding a coupling capacitance Cin to the pixel value storage circuit 50. Paragraph 0055 system control MCU 19 calculates an exposure control value indicating the exposure setting of the imaging element 15 on the basis of the brightness information included in the color space information DCD output from the signal processing circuit 18 and controls the exposure setting and the gain setting of the imaging element 15 such that the light detection circuit 40 is an upstream circuit block which electrically connected to respective first ends of each of the plurality of capacitive coupling capacitance Cin elements in imaging element 15, wherein the upstream light detection circuit 40 block outputs each of a reset level values and a plurality of signal level values each corresponding to an exposure amount to the plurality of capacitive coupling capacitance Cin elements);
Murao further discloses of applicant’s a selection circuit electrically connected to respective second ends of each of the plurality of capacitive elements, wherein the selection section sequentially selectively connects and disconnects selected ones of the plurality of capacitive elements to a downstream node (paragraph 0111 the coupling capacitance Cin is inserted in the wire coupling the terminal where the micro bump is provided to the input transfer transistor 51 where (paragraph 0067 - 0072) the open/closed state of the input transfer transistor 51 is controlled on the basis of a storage control signal TXmi and where the input transfer transistor 51 is connected to the memory capacitance Cm and a second floating diffusion FDmc such that input transfer transistor 51 is a selection circuit electrically connected to respective second ends of each of the plurality of capacitive coupling capacitance Cin elements, wherein the input transfer transistor 51 selection section sequentially selectively closes (connects) and opens (disconnects) selected ones of the plurality of capacitive coupling capacitance Cin elements to a downstream node FDmc);
Murao further discloses of applicant’s and a downstream circuit that reads each of the reset level and the plurality of signal levels via the downstream node (paragraph 0120 – 0121) charge transfer in the imaging element 15 has the reset voltage which provides the dark level and the light detection circuit 40 outputs the first imaging signal voltage Vopx from the source follower circuit. Paragraph 0063 the CDS circuit 34 outputs, as pixel values, difference values between dark level values corresponding to dark level signals which are obtained when the floating diffusions in the pixel value storage circuits 50 are reset and pixel values corresponding to the signal levels of the second imaging signals which are output from the pixel value storage circuits 50 such that the pixel value storage circuits 50 is a downstream circuit that reads each of the reset level value and the plurality of signal level values via the downstream node Vmc whose values are output to the CDS circuit 34).
Regarding claim 3 Murao further discloses of applicant’s further comprising: a downstream reset transistor that initializes a level of the downstream node (paragraph 0067 – 0070 the pixel value storage circuit 50 has a second reset transistor 53 which gives a second reset voltage to the floating diffusion FDmc in response to a second reset signal RSmc such that a downstream reset transistor 53 that initializes a level of the downstream floating diffusion FDmc node).
Regarding claim 4 Murao further discloses of applicant’s wherein the upstream circuit block is provided on a first chip, and the plurality of capacitive elements, the selection circuit, the downstream reset transistor, and the downstream circuit are provided on a second chip (paragraph 0064 imaging element 15 according to Embodiment 1 has one of characteristic features in the light detection circuits 40 formed in the chip A and the pixel value storage circuits 50 formed in the chip B where (paragraph 0067) the pixel value storage circuit 50 has an input transfer transistor 51, a second reset transistor 53, and (paragraph 0110 – 0011) of a circuit diagram illustrating the light detection circuit 40 and the pixel value storage circuit 501 in the imaging element 15, pixel value storage circuit 501 is obtained by adding a coupling capacitance Cin, for each of the imaging element 15, to the pixel value storage circuit 50 such that the upstream light detection circuit 40 block is provided on a first chip A, and the plurality of capacitive elements Cin, for each of the imaging element 15, the selection circuit 51, the downstream reset transistor 53, and the pixel value storage circuit 501 (50) downstream circuit are provided on a second chip B).
Regarding claim 15, claim 15 is rejected for being fully encompassed by the reasons found in rejected claim 2 above and where Murao further discloses the additional claim limitation of applicant's a first photoelectric conversion element that converts incident light into a first charge; a second photoelectric conversion element that converts incident light into a second charge (paragraph 0050 imaging element 15 has a photoelectric conversion element photodiodes that converts received light pixel information obtained from the light receiving element to a digital value. Paragraph 0065 each of the light detection circuit 40 has a photodiode PD such that a first and second photoelectric conversion element PD converts incident light into a first and second charge for each of the light detection circuits 40);
Murao further discloses of applicant’s a first upstream amplification transistor that converts the first charge into a first voltage; a second upstream amplification transistor that converts the second charge into a second voltage (paragraph 0065 each of the light detection circuits 40 have an amplification transistor 43 where (paragraph 0074) the charges generated in the photodiode PD exposed to light are transferred to the floating diffusion FDpx and, in response thereto, the amplification transistor 43 outputs the first imaging signal voltage Vopx such that first and second upstream amplification transistor 43 that converts the first charge into a first and second voltage for each of the light detection circuits 40);
Murao further discloses of applicant’s a first plurality of capacitive elements, wherein a first end of each of the first plurality of capacitive element is connected to an output of the first upstream amplification transistor (paragraph 0065 of the light detection circuit, each of the light detection circuits 40 have an amplification transistor 43. Paragraph 0110 – 0011 of a circuit diagram illustrating the light detection circuit 40 and the pixel value storage circuit 501 in the imaging element 15, pixel value storage circuit 501 is obtained by adding a coupling capacitance Cin to the pixel value storage circuit 50. Paragraph 0067 the pixel value storage circuit 50 has an input transfer transistor 51 where the first imaging signal voltage Vopx output from the light detection circuit 40 is input to the pixel value storage circuit 50 via a micro bump MB. The input transfer transistor 51 has a drain to which the first imaging signal voltage Vopx is input and (paragraph 0074) the charges generated in the photodiode PD exposed to light are transferred to the floating diffusion FDpx and, in response thereto, the amplification transistor 43 outputs the first imaging signal voltage Vopx such that a first plurality group of capacitive elements Cin, wherein a first end of each of the first plurality of capacitive element Cin is connected to an output of the first upstream amplification transistor 43 of the light detection circuit as seen in Fig. 12);
Murao further discloses of applicant’s a second plurality of capacitive elements, wherein a first end of each of the second plurality of capacitive elements is connected to an output of the second upstream amplification transistor (paragraph 0065 of the light detection circuit, each of the light detection circuits 40 have an amplification transistor 43. Paragraph 0110 – 0011 of a circuit diagram illustrating the light detection circuit 40 and the pixel value storage circuit 501 in the imaging element 15, pixel value storage circuit 501 is obtained by adding a coupling capacitance Cin to the pixel value storage circuit 50. Paragraph 0067 the pixel value storage circuit 50 has an input transfer transistor 51 where the first imaging signal voltage Vopx output from the light detection circuit 40 is input to the pixel value storage circuit 50 via a micro bump MB. The input transfer transistor 51 has a drain to which the first imaging signal voltage Vopx is input and (paragraph 0074) the charges generated in the photodiode PD exposed to light are transferred to the floating diffusion FDpx and, in response thereto, the amplification transistor 43 outputs the first imaging signal voltage Vopx such that a second plurality group of capacitive elements Cin, wherein a first end of each of the second plurality of capacitive elements Cin is connected to an output of the second upstream amplification transistor 43 of the light detection circuit as seen in Fig. 12);
Murao further discloses of applicant’s a plurality of selection transistors each having a first end connected to a second end of a corresponding one of the first plurality of capacitive elements or second plurality of capacitive element and having a second end connected to a downstream node (paragraph 0110 - 0111 of the light detection circuit, each of the light detection circuits 40 and the pixel value storage circuit 501, the coupling capacitance Cin is inserted in the wire coupling the terminal where the micro bump is provided to the input transfer transistor 51 where (paragraph 0067 - 0072) the open/closed state of the input transfer transistor 51 is controlled on the basis of a storage control signal TXmi and where the input transfer transistor 51 is connected to the memory capacitance Cm and a second floating diffusion FDmc such that input transfer transistor 51 is a plurality of selection transistors in the light detection circuit each having a first end connected to a second end of a corresponding one of the first group plurality of capacitive elements Cin or second group plurality of capacitive element Cin and having a second end connected to a downstream node with the input transfer transistor 51 as seen in Fig. 12);
Murao further discloses of applicant’s and a downstream amplification transistor that has a gate connected to the downstream node and outputs a pixel signal (paragraph 0067 – 0070 the pixel value storage circuit 50 has a second amplification transistor 54 and a floating diffusion FDmc where the amplification transistor 54 outputs the second imaging signal on the basis of the potential in the floating diffusion FDmc such that a downstream amplification transistor 54 that has a gate connected to the downstream node FDmc and outputs a pixel image signal as seen in Fig. 12).
Regarding claim 16 Murao further discloses of applicant’s further comprising: a downstream reset transistor that initializes a level of the downstream node (paragraph 0067 – 0070 the pixel value storage circuit 50 has a second reset transistor 53 which gives a second reset voltage to the floating diffusion FDmc in response to a second reset signal RSmc such that a downstream reset transistor 53 that initializes a level of the downstream floating diffusion FDmc node).
Regarding claim 19 Murao further discloses of applicant’s a first upstream transfer transistor that transfers the first charge from the first photoelectric conversion element to a first floating diffusion layer; and a first reset transistor that initializes the first floating diffusion layer, wherein the first upstream amplification transistor amplifies a voltage of the first floating diffusion layer (paragraph 0065 each of the light detection circuits 40 has a photodiode PD, a transfer transistor 41, a first reset transistor 42, a first amplification transistor 43, and floating diffusion FDpx. Paragraph 0092 the photodiodes PD, of the light detection circuits 40, are simultaneously exposed to light. The charges generated in the plurality of photodiodes PD by the exposure are simultaneously transferred to the floating diffusions FDpx and are subjected to the resetting process performed by the reset transistors 42 via the transfer transistors 41. Then, the amplification transistors 43 provided in the individual light detection circuits 40 generate the first imaging signals on the basis of voltages resulting from the charges transferred to the floating diffusions FDpx provided to correspond to the respective amplification transistors 43 such that first upstream transfer transistor 41 that transfers the first charge from the first photoelectric conversion element PD to a first floating diffusion FDpx layer for each of the light detection circuits 40; and a first reset transistor 42 that initializes the first floating diffusion FDpx layer, wherein the first upstream amplification transistor 43 amplifies a voltage of the first floating diffusion FDpx layer for each of the light detection circuits 40; a second upstream transfer transistor 41 that transfers the second charge from the first photoelectric conversion element PD to a second floating diffusion FDpx layer for each of the light detection circuits 40; and a second reset transistor 42 that initializes the second floating diffusion FDpx layer, wherein the second upstream amplification transistor 43 amplifies a voltage of the second floating diffusion FDpx layer for each of the light detection circuits 40).
Regarding claim 20, claim 20 is rejected for being fully encompassed by the reasons found in rejected claim 15 above and where Murao further discloses the additional claim limitation of applicant's a plurality of photoelectric conversion elements that convert incident light into charges; an upstream amplification transistor that respectively converts the charges into a voltage (paragraph 0050 imaging element 15 has a photoelectric conversion element photodiodes that converts received light pixel information obtained from the light receiving element to a digital value. Paragraph 0065 each of the light detection circuit 40 has a photodiode PD. Paragraph 0065 each of the light detection circuits 40 have an amplification transistor 43 where (paragraph 0074) the charges generated in the photodiode PD exposed to light are transferred to the floating diffusion FDpx and, in response thereto, the amplification transistor 43 outputs the first imaging signal voltage Vopx. Paragraph 0145 the light detection circuit 40a has two pairs of the photodiodes PD and transfer transistors for the one amplification transistor 43. In FIG. 20, the circuit is configured such that the charges generated in a photodiode PD1 are transferred to the floating diffusion FDpx via a transfer transistor 411 and the charges generated in a photodiode PD2 are transferred to the floating diffusion FDpx via a transfer transistor 412 such that plurality of photoelectric conversion elements PD1 and PD2 that convert incident light into charges; an upstream amplification transistor 43 that respectively converts the charges into a voltage).
Regarding claim 21 Murao further discloses of applicant’s further comprising: a downstream reset transistor that initializes a level of the downstream node (paragraph 0067 – 0070 the pixel value storage circuit 50 has a second reset transistor 53 which gives a second reset voltage to the floating diffusion FDmc in response to a second reset signal RSmc such that a downstream reset transistor 53 that initializes a level of the downstream floating diffusion FDmc node).
Allowable Subject Matter
Claims 17 and 18 are objected to as being dependent upon or ultimately dependent on a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARK T MONK whose telephone number is (571)270-7454. The examiner can normally be reached Monday thru Friday 8am to 4pm.
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/MARK T MONK/Primary Examiner, Art Unit 2637
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