DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Change in Assigned Examiner
The examiner assigned to your application has changed. To aid in correlating any papers for this application, all further correspondence regarding this application should be directed to examiner Timothy J. Henn in Art Unit 2639. The examiner may be reached at (571) 272-7310.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 13 July 2026 has been entered.
Response to Arguments
Applicant’s arguments, see response, filed 13 July 2026, with respect to the rejections of the claims have been fully considered and are persuasive. The rejections of the claims have been withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 15-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Milkov et al. (US 2019/0327432 A1) in view of Official Notice.[claim 15]
Regarding claim 15, Milkov discloses a solid-state imaging element comprising:
a first photoelectric conversion element that converts incident light into a first charge (Figure 1, 10; Paragraphs 0026-0030; PPD in a first pixel of an array);
a second photoelectric conversion element that converts incident light into a second charge Figure 1, 10; Paragraphs 0026-0030; PPD in a second pixel of the array);
a first upstream amplification transistor that converts the first charge into a first voltage (Figure 1, Misf; Paragraph 0027; source follower transistor in a first pixel of the array);
a second upstream amplification transistor that converts the second charge into a second voltage Figure 1, Misf; Paragraph 0027; source follower transistor in a second pixel of the array);
a first plurality of capacitive elements, wherein a first end of each of the first plurality of capacitive elements is connected to an output of the first upstream amplification transistor (Figure 7, Cr_hg and Cs_lg capacitors corresponding to first pixel);
a second plurality of capacitive elements, wherein a first end of each of the second plurality of capacitive elements is connected to an output of the second upstream amplification transistor (Figure 7, Cr_hg and Cs_lg capacitors corresponding to second pixel);
a plurality of selection switches each having a first end connected to a second end of a corresponding one of the first plurality of capacitive elements or second plurality of capacitive element and having a second end connected to a downstream node (Figure 7, sel_hg and sel_lg connecting capacitor nodes to downstream node Vsf 77); and
a downstream amplification transistor that has a gate connected to the downstream node and outputs a pixel signal (Figure 7, 42).
Milkov does not disclose that the plurality of selection switches are formed by transistors.
Official Notice is taken that it is well known in the art to form switches in a semiconductor device such as the solid-state imaging element of Milkov using transistors. By using transistors as switches, the switches may be formed using a common process during manufacturing of the device through conventional semiconductor processing technologies.
Therefore, it would have been obvious to form the switches described by Milkov using transistors so that the switches may be formed using a common process during manufacturing of the device through conventional semiconductor processing technologies. [claim 16]
Regarding claim 16, Milkov discloses a reset switch having a source or drain connected to the downstream node (Figure 7, Mclr). Additionally, see the rejection of claim 16 above and note that it would be obvious to form the switch using a transistor for the same reasons described.[claim 17]
Regarding claim 17, Milkov discloses wherein the first plurality of capacitive elements includes first and second capacitive elements (Figure 7, Cr_hg and Cs_lg for first pixel),
the second plurality of capacitive elements includes third and fourth capacitive elements (Figure 7, Cr_hg and Cs_lg for second pixel),
respective first ends of the first and second capacitive elements are connected to an output of the first upstream amplification transistor (Figure 7, Cr_hg and Cs_lg for first pixel are connected to Misf via switches 72/82 and connection line 30/16 between first and second layer), and
respective first ends of the third and fourth capacitive elements are connected to an output of the second upstream amplification transistor (Figure 7, Cr_hg and Cs_lg for second pixel are connected to Misf via switches 72/82 and connection line 30/16 between first and second layer).[claim 18]
Regarding claim 18, Milkov discloses wherein the first plurality of capacitive elements further includes fifth and sixth capacitive elements (Figure 7, Cs_hg and Cr_lg for first pixel), and
the second plurality of capacitive elements further includes seventh and eighth capacitive elements (Figure 7, Cs_hg and Cr_lg for second pixel),
respective first ends of the fifth and sixth capacitive elements are connected to an output of the first upstream amplification transistor (Figure 7, Cs_hg and Cr_lg for first pixel are connected to Misf via switches 72/82 and connection line 30/16 between first and second layer), and
respective first ends of the seventh and eighth capacitive elements are connected to an output of the second upstream amplification transistor (Figure 7, Cs_hg and Cr_lg for second pixel are connected to Misf via switches 72/82 and connection line 30/16 between first and second layer).[claim 19]
Regarding claim 19, Milkov discloses a first upstream transfer transistor that transfers the first charge from the first photoelectric conversion element to a first floating diffusion layer (Figure 1, Mtg for first pixel); and
a first reset transistor that initializes the first floating diffusion layer, wherein the first upstream amplification transistor amplifies a voltage of the first floating diffusion layer (Figure 1, Mrst for first pixel resetting node Vfd which is amplified by Misf);
a second upstream transfer transistor that transfers the second charge from the first photoelectric conversion element to a second floating diffusion layer (Figure 1, Mtg for second pixel); and
a second reset transistor that initializes the second floating diffusion layer, wherein the second upstream amplification transistor amplifies a voltage of the second floating diffusion layer (Figure 1, Mrst for second pixel resetting node Vfd which is amplified by Misf).[claim 20]
Regarding claim 20, see the rejection of claim 15 above.[claim 21]
Regarding claim 21, see the rejection of claim 16 above.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 15-21 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 20 of U.S. Patent No. 11,974,057 B2 in view of Milkov et al. (US 2019/0327432 A1). Although the claims at issue are not identical, they are not patentably distinct from each other.[claim 15]
15. (Previously presented) A solid-state imaging element comprising:
a first photoelectric conversion element that converts incident light into a first charge;
a second photoelectric conversion element that converts incident light into a second charge;
a first upstream amplification transistor that converts the first charge into a first voltage;
a second upstream amplification transistor that converts the second charge into a second voltage;
a first plurality of capacitive elements, wherein a first end of each of the first plurality of capacitive elements is connected to an output of the first upstream amplification transistor;
a second plurality of capacitive elements, wherein a first end of each of the second plurality of capacitive elements is connected to an output of the second upstream amplification transistor;
a plurality of selection transistors each having a first end connected to a second end of a corresponding one of the first plurality of capacitive elements or second plurality of capacitive element and having a second end connected to a downstream node; and
a downstream amplification transistor that has a gate connected to the downstream node and outputs a pixel signal.
20. A solid-state imaging element comprising:
a first photoelectric conversion element that converts incident light into a charge;
a second photoelectric conversion element that converts incident light into a charge;
an upstream amplification transistor that converts the charges into voltages;
a predetermined number of capacitive elements each having first end connected to as upstream node which is an output destination of the upstream amplification transistor;
a predetermined number of selection transistors inserted in each of paths between each of second ends of the predetermined number of capacitive elements and a predetermined downstream node;
a reset transistor having a source or a drain connected to the downstream node; and
a downstream amplification transistor that has a gate connected to the downstream node and outputs a pixel signal.
While ‘057 does not claim a second upstream amplification transistor or a second plurality of capacitive elements, such an arrangement is known in the prior art. For example, Milkov teaches a vertically integrated pixel which consists of a pixel portion and a sampling capacitor/processing circuitry portion configured to store signal and reset levels to allow a global-shutter operation which provides simultaneous sampling of signal/reset levels for all pixels of the pixel array (e.g. Paragraphs 0053-0056). Therefore, it would have been obvious to provide a sampling capacitor and processing circuit for each pixel in the system of ‘057 so that each pixel may simultaneously sample and store signal/reset levels during a global shutter operation.[claim 16]
Regarding claim 16, see claim 20 of ‘057.[claims 17 and 18]
Regarding claim 18, while ‘057 does not explicitly claim first, second, third and fourth capacitors for each of a first and second pixel, Milkov discloses providing four capacitors for each pixel (resulting in first-eight capacitors as claimed) so that signal and reset for high and low conversion gain samples may be stored (e.g. Figure 7).
Therefore, it would have been obvious to provide four capacitors as the predetermined number in ‘057 to store signal and reset levels for high and low conversion gain samples.[claim 19]
Regarding claim 19, ‘057 does not claim a first upstream transfer transistor that transfers the first charge from the first photoelectric conversion element to a first floating diffusion layer; and a first reset transistor that initializes the first floating diffusion layer, wherein the first upstream amplification transistor amplifies a voltage of the first floating diffusion layer; a second upstream transfer transistor that transfers the second charge from the first photoelectric conversion element to a second floating diffusion layer; and a second reset transistor that initializes the second floating diffusion layer, wherein the second upstream amplification transistor amplifies a voltage of the second floating diffusion layer.
However, Milkov teaches such a pixel arrangement (see rejection of claim 19 above). By providing a transfer/reset transistor, a global shutter operation may be provided. Therefore, it would have been obvious to provide a transistor and reset transistor as taught by Milkov to provide a global shutter operation in the pixels.[claims 20 and 21]
Regarding claims 20 and 21, see the rejection of claims 15 and 16 above.
Allowable Subject Matter
Claims 2-14 are allowed.[claims 2-14]
Since the Applicant’s arguments of record filed on 13 July 2026 (page(s) 9-15) are persuasive regarding the currently claimed subject matter which is/are not taught nor suggested by the prior art of record, either alone or in combination, the reasons for allowance have been fully addressed and complied according to MPEP 1302.14(I).
Additionally, while the prior art teaches similar systems, the particular requirements recited in claims 2-14 are not taught or suggested by the prior art.
For example, Milkov (discussed above) recites a similar solid-state imaging element. However, the capacitors of Milkov are connected to the upstream node via switches and thus are not electrically connected in common as recited in the claims.
Furthermore, the system of Milkov outputs a correlated double sampling signal and does not output each of a reset level and plurality of signal levels as recited in claims 2-14.
Hsieh et al. (US 2022/0247953 A1 – Figure 5), Wu (US 2021/0006739 A1 – Figure 1), Xu et al. (US 2017/0180660 A1 – Figure 6), Weale et al. (US 7,286,174 B1 – Figure 6) and Hashimoto et al. (US 2005/0146617 A1 – Figure 1) recite similar systems including storage capacitors, but like Milkov do not teach the particular requirements of claims 2-14.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOTHY J HENN whose telephone number is (571)272-7310. The examiner can normally be reached Monday-Friday ~10-6.
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/Timothy J Henn/Primary Examiner, Art Unit 2639
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