DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings received on 04/09/24 are acceptable.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 11 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US 6,275,100 B1).
Park et al. disclose a reference voltage generators including first and second transistors of same conductivity type and at least one switch in Figures 6-11.
With regard to claim 1. An apparatus comprising (Figure 11): a first resistor (20), a first negative threshold transistor (29), a second resistor (22) and a second negative threshold transistor (24) coupled in series between a first voltage bus (Vss) and a second voltage bus (Vcc); and a first positive threshold transistor connected between a common node of the second resistor and the first negative threshold transistor, and the first voltage bus, wherein a first reference voltage is generated on a first reference voltage bus (Vref), and wherein the first reference voltage bus is coupled to a common node (23) of a drain/source terminal of the second negative threshold transistor (24) and the second resistor (22) (see col. 7, lines 23-62).
With regard to claim 11. A method comprising (Figure 11): providing a first voltage reference apparatus comprising a first resistor (20), a first negative threshold transistor (29), a second resistor (22) and a second negative threshold transistor (24) coupled in series between a first voltage bus (Vss) and a second voltage bus (Vcc), and a first positive threshold transistor (29) connected between a common node of the second resistor (22) and the first negative threshold transistor (29), and the first voltage bus (Vss); and configuring the first voltage reference apparatus to generate a first reference voltage on a first reference voltage bus (Vref), wherein the first reference voltage is equal to a sum of a voltage on the first voltage bus (Vss), a gate-to-source voltage of the first positive threshold transistor and a source-to-gate voltage of the second negative threshold transistor (24) (see col. 7, lines 23-62).
With regard to claim 12. The method of claim 11, wherein: the first reference voltage bus (Vref) is connected to a common node of a source of the second negative threshold transistor (24) and the second resistor (22).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Suzu et al. (US 6,108,247) in view of Park et al. (US 6,275,100 B1).
Suzu et al. disclose a voltage generation circuit for multivalued cell type mask ROM in Figures 1-3. Suzu et al. disclose the claimed invention plurality of voltage reference apparatus except for the details of the voltage apparatus. Part et al. disclose the claimed detail of the voltage reference apparatus.
Park et al. disclose two resistors (20, 22) and two negative threshold transistors (29, 24) coupled in series; and one positive threshold transistor (28) connected in parallel with a circuit branch comprising one negative threshold transistor and one resistor connected in series, wherein: the first voltage bus is connected to ground (Vss); and the second voltage bus (Vcc) is connected to a bias voltage source (see col. 7, lines 23-62)
It would have been obvious to one having ordinary skill in the art at the time of filing to provide the detail of the voltage reference apparatus of Part et al. in Suzu et al. circuit in order to provide a plurality of voltage reference apparatus relatively insensitive to variation in threshold voltage due to device fabrication.
Allowable Subject Matter
Claims 2-10, 13-16, 18 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 2 is allowed because the prior art of record fails to disclose or suggest an apparatus including the limitation “wherein: the first voltage bus is connected to ground; the second voltage bus is connected to a bias voltage source; and the first negative threshold transistor, the second negative threshold transistor and the first positive threshold transistor are n-type transistors“ in addition to other limitations recited therein.
Claim 3 is allowed because the prior art of record fails to disclose or suggest an apparatus including the limitation “wherein: a drain of the first negative threshold transistor is connected to the second resistor; a source of the first negative threshold transistor is connected to the first resistor; and a gate of the first negative threshold transistor is connected to the first voltage bus “ in addition to other limitations recited therein.
Claim 4 is allowed because the prior art of record fails to disclose or suggest an apparatus including the limitation “wherein: a drain of the second negative threshold transistor is connected to the second voltage bus; a source of the second negative threshold transistor is connected to the second resistor; and a gate of the second negative threshold transistor is connected to the common node of the second resistor and the first negative threshold transistor“ in addition to other limitations recited therein.
Claim 5 is allowed because the prior art of record fails to disclose or suggest an apparatus including the limitation “wherein: a drain of the first positive threshold transistor is connected to the common node of the second resistor and the first negative threshold transistor; a source of the first positive threshold transistor is connected to the first voltage bus; and a gate of the first positive threshold transistor is connected to the common node of the second resistor and the first negative threshold transistor “ in addition to other limitations recited therein.
Claim 6 is allowed because the prior art of record fails to disclose or suggest an apparatus including the limitation “further comprising: a capacitor connected between the common node of the second resistor and the second negative threshold transistor, and the first voltage bus“ in addition to other limitations recited therein.
Claim 7 is allowed because the prior art of record fails to disclose or suggest an apparatus including the limitation “further comprising: a low-pass filter connected between the common node of the second resistor and the second negative threshold transistor, and the first voltage bus, and wherein the low-pass filter comprises a filter resistor and a filter capacitor, and wherein: the filter resistor is connected between the common node of the second resistor and the second negative threshold transistor, and the first reference voltage bus; and the filter capacitor is connected between the first reference voltage bus and the first voltage bus“ in addition to other limitations recited therein.
Claim 8 is allowed because the prior art of record fails to disclose or suggest an apparatus including the limitation “further comprising: a first low-pass filter connected between the common node of the second resistor and the second negative threshold transistor, and the first voltage bus; and a second low-pass filter connected between the second voltage bus and the second negative threshold transistor, wherein the first low-pass filter comprises a first filter resistor and a first filter capacitor, and the second low-pass filter comprises a second filter resistor and a second filter capacitor, and wherein: the first filter resistor is connected between the common node of the second resistor and the second negative threshold transistor, and the first reference voltage bus; the first filter capacitor is connected between the first reference voltage bus and the first voltage bus; the second filter resistor is connected between the second reference voltage bus and the second negative threshold transistor; and the second filter capacitor is connected between a common node of the second filter resistor and the second negative threshold transistor, and the first voltage bus “ in addition to other limitations recited therein.
Claim 9 is allowed because the prior art of record fails to disclose or suggest an apparatus including the limitation “further comprising: a third resistor, a third negative threshold transistor, a fourth resistor and a fourth negative threshold transistor coupled in series between the first reference voltage bus and the second voltage bus; and a second positive threshold transistor connected between a common node of the fourth resistor and the third negative threshold transistor, and the first reference voltage bus, wherein a second reference voltage is generated on a second reference voltage bus, and wherein the second reference voltage bus is connected to a common node of a drain/source terminal of the fourth negative threshold transistor and the fourth resistor“ in addition to other limitations recited therein.
Claim 10 is allowed because the prior art of record fails to disclose or suggest an apparatus including the limitation “ further comprising: a third resistor, a third negative threshold transistor, a fourth resistor and a fourth negative threshold transistor coupled in series between the first reference voltage bus and the second voltage bus; a second positive threshold transistor connected between a common node of the fourth resistor and the third negative threshold transistor, and the first reference voltage bus, wherein a second reference voltage is generated on a second reference voltage bus, and wherein the second reference voltage bus is connected to a common node of a drain/source terminal of the fourth negative threshold transistor and the fourth resistor; a fifth resistor, a fifth negative threshold transistor, a sixth resistor and a sixth negative threshold transistor coupled in series between the second reference voltage bus and the second voltage bus; and a third positive threshold transistor connected between a common node of the sixth resistor and the fifth negative threshold transistor, and the second reference voltage bus, wherein a third reference voltage is generated on a third reference voltage bus, and wherein the third reference voltage bus is connected to a common node of a drain/source terminal of the sixth negative threshold transistor and the sixth resistor“ in addition to other limitations recited therein.
Claim 13 is allowed because the prior art of record fails to disclose or suggest a method including the limitation “wherein: a drain of the first negative threshold transistor is connected to the second resistor; a source of the first negative threshold transistor is connected to the first resistor; a gate of the first negative threshold transistor is connected to the first voltage bus; a drain of the second negative threshold transistor is connected to the second voltage bus; a source of the second negative threshold transistor is connected to the second resistor; a gate of the second negative threshold transistor is connected to the common node of the second resistor and the first negative threshold transistor; a drain of the first positive threshold transistor is connected to the common node of the second resistor and the first negative threshold transistor; a source of the first positive threshold transistor is connected to the first voltage bus; and a gate of the first positive threshold transistor is connected to the common node of the second resistor and the first negative threshold transistor “ in addition to other limitations recited therein.
Claim 14 is allowed because the prior art of record fails to disclose or suggest a method including the limitation “further comprising: providing a second voltage reference apparatus over the first voltage reference apparatus, wherein the second voltage reference apparatus comprises a third resistor, a third negative threshold transistor, a fourth resistor and a fourth negative threshold transistor coupled in series between the first reference voltage bus and the second voltage bus, and a second positive threshold transistor connected between a common node of the fourth resistor and the third negative threshold transistor, and the first reference voltage bus; and configuring the second voltage reference apparatus to generate a second reference voltage on a second reference voltage bus, wherein the second reference voltage is equal to a sum of the first reference voltage, a source-to-gate voltage of the fourth negative threshold transistor and a gate-to-source voltage of the second positive threshold transistor“ in addition to other limitations recited therein.
Claim 15 is allowed because the prior art of record fails to disclose or suggest a method including the limitation “further comprising: providing a second voltage reference apparatus over the first voltage reference apparatus and a third voltage reference apparatus over the second voltage reference apparatus, wherein: the second voltage reference apparatus comprises a third resistor, a third negative threshold transistor, a fourth resistor and a fourth negative threshold transistor coupled in series between the first reference voltage bus and the second voltage bus, and a second positive threshold transistor connected between a common node of the fourth resistor and the third negative threshold transistor, and the first reference voltage bus; and the third voltage reference apparatus comprises a fifth resistor, a fifth negative threshold transistor, a sixth resistor and a sixth negative threshold transistor coupled in series between the second reference voltage bus and the second voltage bus, and a third positive threshold transistor connected between a common node of the sixth resistor and the fifth negative threshold transistor, and the second reference voltage bus; configuring the second voltage reference apparatus to generate a second reference voltage on a second reference voltage bus, wherein the second reference voltage is equal to a sum of the first reference voltage, a source-to-gate voltage of the fourth negative threshold transistor and a gate-to-source voltage of the second positive threshold transistor; and configuring the third voltage reference apparatus to generate a third reference voltage on a third reference voltage bus, wherein the third reference voltage is equal to a sum of the second reference voltage, a source-to-gate voltage of the sixth negative threshold transistor and a gate-to-source voltage of the third positive threshold transistor “ in addition to other limitations recited therein.
Claim 16 is allowed because the prior art of record fails to disclose or suggest a method including the limitation “wherein: the second reference voltage bus is connected to a common node of a source of the fourth negative threshold transistor and the fourth resistor; and the third reference voltage bus is connected to a common node of a source of the sixth negative threshold transistor and the sixth resistor“ in addition to other limitations recited therein.
Claim 18 is allowed because the prior art of record fails to disclose or suggest a method including the limitation “ wherein the voltage reference system comprises a second voltage reference apparatus stacked over a first voltage reference apparatus, and wherein: the first voltage reference apparatus comprises a first resistor, a first negative threshold transistor, a second resistor and a second negative threshold transistor coupled in series between the first voltage bus and the second voltage bus, and a first positive threshold transistor connected between a common node of the second resistor and the first negative threshold transistor, and the first voltage bus, and wherein a first reference voltage is generated on a first reference voltage bus, and wherein the first reference voltage bus is connected to a source of the second negative threshold transistor and the second resistor; and the second voltage reference apparatus comprises a third resistor, a third negative threshold transistor, a fourth resistor and a fourth negative threshold transistor coupled in series between the first reference voltage bus and the second voltage bus, and a second positive threshold transistor connected between a common node of the fourth resistor and the third negative threshold transistor, and the first reference voltage bus, and wherein a second reference voltage is generated on a second reference voltage bus, and wherein the second reference voltage bus is connected to a source of the fourth negative threshold transistor and the fourth resistor“ in addition to other limitations recited therein.
Claim 19 is allowed because the prior art of record fails to disclose or suggest a system including the limitation “wherein the voltage reference system comprises a second voltage reference apparatus stacked over a first voltage reference apparatus, and a third voltage reference apparatus stacked over the second voltage reference apparatus, and wherein: the first voltage reference apparatus comprises a first resistor, a first negative threshold transistor, a second resistor and a second negative threshold transistor coupled in series between the first voltage bus and the second voltage bus, and a first positive threshold transistor connected between a common node of the second resistor and the first negative threshold transistor, and the first voltage bus, and wherein a first reference voltage is generated on a first reference voltage bus, and wherein the first reference voltage bus is connected to a source of the second negative threshold transistor and the second resistor; the second voltage reference apparatus comprises a third resistor, a third negative threshold transistor, a fourth resistor and a fourth negative threshold transistor coupled in series between the first reference voltage bus and the second voltage bus, and a second positive threshold transistor connected between a common node of the fourth resistor and the third negative threshold transistor, and the first reference voltage bus, and wherein a second reference voltage is generated on a second reference voltage bus, and wherein the second reference voltage bus is connected to a source of the fourth negative threshold transistor and the fourth resistor; and the third voltage reference apparatus comprises a fifth resistor, a fifth negative threshold transistor, a sixth resistor and a sixth negative threshold transistor coupled in series between the second reference voltage bus and the second voltage bus, and a third positive threshold transistor connected between a common node of the sixth resistor and the fifth negative threshold transistor, and the second reference voltage bus, and wherein a third reference voltage is generated on a third reference voltage bus, and wherein the third reference voltage bus is connected to a source of the sixth negative threshold transistor and the sixth resistor “ in addition to other limitations recited therein.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yuh et al. (US 11,953,927 B2) disclose a bias generating devices and methods for generating bias.
Ooiwa (US 11,681,318 B2) discloses a voltage generation circuit and semiconductor device.
Mori (US 5,369,354) discloses an intermediate voltage generating circuit having low output impedance.
Examiner has cited particular columns, line numbers and/or paragraphs in thereferences applied to the claims above for the convenience of the applicant. Althoughthe specified citations are representative of the teachings of the art and are applied tospecific limitations within the individual claim(s), other passages and figures may applyas well.
Additionally, in the event that other prior art is provided and made of record by theExaminer, as being relevant or pertinent to applicant's disclosure but not relied upon.The references are provided for the convenience of the applicant. The Examinerrequest that the references be considered in any subsequent amendments, as they arealso representative of the art and may apply to the specific limitations ofany newly amended claim(s).
It is respectfully requested from the applicant in preparing amendments or responses, to fully consider the references in their entirety as potentially teaching all or part of theclaimed invention, as well as the context of the passage as taught by the prior art and/ordisclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied upon inorder to ensure proper interpretation of the newly added limitations and toverify/ascertain the metes and bounds of the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADOLF D BERHANE whose telephone number is (571)272-2077. The examiner can normally be reached 7:00 AM to 4:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal Hammond can be reached at 571-270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ADOLF D BERHANE/Primary Examiner, Art Unit 2838